EX.

NO:2
DESIGN ENTRY AND SIMULATION OF SEQUENTIAL CIRCUITS
DATE:

AIM:

To write a verilog program for various flip flops to synthesize and simulate using Xilinx software
tool.

TOOLS REQUIRED:

SOFTWARE:

2. Xilinx ISE Design Suite 12.1

THEORY:

D-FLIP FLOP:

It has only a single data input. That data input is connected to the S input of RS-flip flop, while the
inverse of D is connected to the R input. This prevents that the input combination ever occurs. To
allow the flip flop to be in holding state, a D-flip flop has a second input called “clock”. The clock
input is AND-ed with the D input, such that when clock=0, the R and S inputs of the RS-flip flop are 0
and the state is held.

D Flip-flops are used as a part of memory storage elements and data processors as well. D flip-flop can be built
using NAND gate or with NOR gate. Due to its versatility they are available as IC packages. The major
applications of D flip-flop are to introduce delay in timing circuit, as a buffer, sampling data at specific intervals. D
flip-flop is simpler in terms of wiring connection compared to JK flip-flop. Here we are using NAND gates for
demonstrating the D flip flop
Whenever the clock signal is LOW, the input is never going to affect the output state. The clock has to be
high for the inputs to get active. Thus, D flip-flop is a controlled Bi-stable latch where the clock signal is the control
signal. Again, this gets divided into positive edge triggered D flip flop and negative edge triggered D flip-flop.

T-FLIP FLOP:
The name T flip-flop is termed from the nature of toggling operation. The major applications of T flip-flop are
counters and control circuits. T flip flop is modified form of JK flip-flop making it to operate in toggling region.
Whenever the clock signal is LOW, the input is never going to affect the output state. The clock has to be
high for the inputs to get active. Thus, T flip-flop is a controlled Bi-stable latch where the clock signal is the control
signal.

T flip – flop is also known as “Toggle Flip – flop”. To avoid the occurrence of intermediate state in SR
flip – flop, we should provide only one input to the flip – flop called Trigger input or Toggle input (T).
Then the flip – flop acts as a Toggle switch. Toggling means ‘Changing the next state output to
complement of the present state output’.
We can design the T flip – flop by making simple modifications to the JK flip – flop. The T flip – flop is
a single input device and hence by connecting J and K inputs together and giving them with single input
called T we can convert a JK flip – flop into T flip – flop. So a T flip – flop is sometimes called as single
input JK flip – flop.

The logic symbol of T flip – flop is shown below. It has one Toggle input (T) & one clock signal input
(CLK).

SR Flip-Flop
SR Flip-flops were used in common applications like MP3 players, Home theatres, Portable audio docks, and etc.
But now-a-days JK and D flip-flops are used instead, due to versatility. SR latch can be built with NAND gate or
with NOR gate. Either of them will have the input and output complemented to each other. Here we are
using NAND gates for demonstrating the SR flip flop.
Whenever the clock signal is LOW, the inputs S and R are never going to affect the output. The clock has to
be high for the inputs to get active. Thus, SR flip-flop is a controlled Bi-stable latch where the clock signal is the
control signal. Again, this gets divided into positive edge triggered SR flip flop and negative edge triggered
SR flip-flop.

The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic sequential logic
circuit possible. This simple flip-flop is basically a one-bit memory bistable device that has two inputs,
one which will “SET” the device (meaning the output = “1”), and is labelled S and one which will
“RESET” the device (meaning the output = “0”), labelled R.
Then the SR description stands for “Set-Reset”. The reset input resets the flip-flop back to its original
state with an output Q that will be either at a logic level “1” or logic “0” depending upon this set/reset
condition.

JK FLIP FLOP:
The name JK flip-flop is termed from the inventor Jack Kilby from texas instruments. Due to its versatility they are
available as IC packages. The major applications of JK flip-flop are Shift registers, storage registers, counters and
control circuits. Inspite of the simple wiring of D type flip-flop, JK flip-flop has a toggling nature. This has been an
added advantage. Hence they are mostly used in counters and PWM generation, etc. Here we are using NAND
gates for demonstrating the JK flip flop
Whenever the clock signal is LOW, the input is never going to affect the output state. The clock has to be
high for the inputs to get active. Thus, JK flip-flop is a controlled Bi-stable latch where the clock signal is the
control signal.

SHIFT REGISTERS (SISO, SIPO, PISO, PIPO)

This sequential device loads the data present on its inputs and then moves or “shifts” it to its output once
every clock cycle, hence the name Shift Register.
Generally, shift registers operate in one of four different modes with the basic movement of data through a
shift register being:
 Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time, with the
stored data being available at the output in parallel form.
 Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the register, one bit at a
time in either a left or right direction under clock control.
 Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register simultaneously and is
shifted out of the register serially one bit at a time under clock control.
 Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the register, and
transferred together to their respective outputs by the same clock pulse.

SYNCHRONOUS COUNTER

COUNTER :

A counter that can change state in either direction, under the control of an up or down selector input, is
known as an up/down counter. When the selector is in the up state, the counter increments its value. When
the selector is in the down state, the counter decrements the count. Likewise the counter counts in both the
directions continuously until attaining the end of the count. The count is initiated by the positive clock
pulse. The counter counts from 0000 to 1111 for up count and 1111 to 0000 for down count.

ASYNCHRONOUS COUNTER

MOD COUNTER
The “MODULO” or “MODULUS” OR MOD of a counter is the number of states the counter counts or
sequences through before repeating itself. The counter has four distinct states, it is also known as a “modulo-
4” or “mod-4” counter with each flip-flop output having a frequency value equal to one-fourth or a quarter
(1/4) that of the main clock frequency.

SEQUENCE GENERATOR
PRBS :
A PRBS is 'pseudorandom', because, although it is in fact deterministic, it seems to be random in a sense that
the value of an element is independent of the values of any of the other elements, similar to real random
sequences. A PRBS can be stretched to infinity by repeating it after elements, this in contrast to most random
sequences, such as sequences generated by radioactive decay or by white noise, that are 'infinite' by nature.
The PRBS is more general than the maximum length sequence, which is a special pseudo-random binary
sequence of N bits generated as the output of a linear shift register. A maximum length sequence always has
a 1/2 duty cycle and its number of elements .
SEQUENCE DETECTOR
ALGORITHM FOR SEQUENCE DETECTOR:

Step 1: Start the program.

Step 2: Declare the input, clk, reset.

Step 3: Declare the output as y.

Step 4: Draw the state diagram whose initial state is reset.

Step 5: If the input matches with a given sequence the present state transits to the next state.
Step 6: If the input does not match with a given sequence the state will be in present state or move to the
reset state as per the condition given.

Step 7: The output is always remains “0” until the whole sequence is received. Step 8:
When the sequence is fully received the output changes from “0” to “1”.
THEORY FOR SEQUENCE DETECTOR:
A sequence detector is the one which detects the next state when the reset value is given. The
transition takes place from the present state to the next state when the value is given or else the present state
will be the same state. It can be described using state diagrams. Each state is used to represent the present
state or the next state. The five bit sequence 11010 can be detected using this state diagram if reset is given
then it goes to the next state s1and attains the value 1or else it stays in the same state s0.

RING COUNTER

Connect the output of this shift register back to its input so that the output from the last flip-flop, QD becomes
the input of the first flip-flop, DA. We would then have a closed loop circuit that “recirculates” the same bit of
DATA around a continuous loop for every state of its sequence, and this is the principal operation of a Ring
Counter.
Then by looping the output back to the input, (feedback) we can convert a standard shift register circuit into a
ring counter.
A ring counter can be made to output any modulo number. A “mod-n” ring counter will require “n” number of
flip-flops connected together to circulate a single data bit providing “n” different output states. For example, a
mod-8 ring counter requires eight flip-flops and a mod-16 ring counter would require sixteen flip-flops.
JOHNSON RING COUNTER
The Johnson Ring Counter or “Twisted Ring Counters”, is another shift register with feedback exactly the
same as the standard Ring Counter above, except that this time the inverted output Q of the last flip-flop is
now connected back to the input D of the first flip-flop as shown below.
The main advantage of this type of ring counter is that it only needs half the number of flip-flops compared to
the standard ring counter then its modulo number is halved. So a “n-stage” Johnson counter will circulate a
single data bit giving sequence of 2n different states and can therefore be considered as a “mod-2n counter”.

FLIP FLOP

D (DATA)FLIP FLOP:
GATE LEVEL MODELLING

module dff_from_nand(clk, d, q, q_bar);

wire q,q_bar;
reg d,clk;
nand u1 (x,d,clk) ;
nand u2 (y,x,clk) ;
nand u3 (q,q_bar,x);
nand u4 (q_bar,q,y)

BEHAVIORAL LEVEL MODELLING:

module dff_beh (d,clk,rst,q);
input d,clk,rst;
output q;
reg q;
always @(posedge clk or posedge rst)
begin
if (rst)
q = 1'b0;
else
q = d;
end
endmodule
T (TRIGGER OR TOGGLE) FLIP FLOP:

T-FLIP FLOP USING JK FLIP FLOP

GATE LEVEL MODELLING

BEHAVIORAL LEVEL MODELLING:

module T_Flip_Flop (Q,clk,reset,t);

output Q;
input clk,reset,t;
reg Q;
always @(posedge clk)
begin
if (reset)
Q = 0;
else if (t == 0)
Q = Q;
else
Q = ~Q;
end
endmodule

JK (JACK KILBY) FLIP FLOP:

GATE LEVEL MODELLING

module jkffgl(j,k,clk,clr,q,qb);
input j,k,clk;
input cl;
output q,qb;
wire j1,k1,q1,qb1,j2,k2,q2,qb2,clk2;
not n(clk2,clk);
nand n1(j1,j,clk,qb2,cl);
nand n2(k1,k,clk,q2);
nand n3(q1,j1,qb1);
nand n4(qb1,k1,q1);
nand n5(j2,q1,clk2);
nand n6(k2,qb1,clk2);
nand n7(q2,j2,qb2);
nand n8(qb2,k2,q2,cl);
q=q2;
qb=qb2;
endmodule

BEHAVIORAL LEVEL MODELLING:

module JK_Flip_Flop (Q,Qbar,clk,reset,J,K);
output Q,Qbar;
input clk, reset,J,K;
reg Q;
always @(posedge clk)
begin
if (reset)
Q = 0;
else if (J == 0 && K == 0)
Q = Q;
else if (J == 0 && K == 1)
Q = 0;
else if (J == 1 && K == 0)
Q = 1;
else
Q = Qbar;
end
Qbar = ~Q;
endmodule
SR (SET RESET)FLIP FLOP:

GATE LEVEL MODELLING

module srffgl(s,r,clk,q,qb);
input s,r,clk;
inout q,qb;
wire s1,r1;
nand n1(s1,s,clk);
nand n2(r1,r,clk);
nand n3(q,s1,qb);
nand n4(qb,r1,q);
endmodule

BEHAVIORAL LEVEL MODELLING:

module SR_Flip_Flop (Q,Qbar,clk,reset,S,R);
output Q,Qbar;
input clk, reset,S,R;
reg Q;
always @(posedge clk)
begin
if (reset)
Q = 0;
else if (S == 0 && R == 0)
Q = Q;
else if (S == 0 && R == 1)
Q = 0;
else if (S == 1 && R == 0)
Q = 1;
else
Q = 1'bx;
end
Qbar = ~Q;
endmodule
SHIFT REGISTERS
4-bit Serial-in to Parallel-out (SIPO) Shift Register

GATE LEVEL MODELLING

BEHAVIORAL LEVEL MODELLING:

module sipo ( din ,clk ,reset ,dout );

output [3:0] dout ;
wire [3:0] dout ;
input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
reg [3:0]s;
always @ (posedge clk or posedge reset)
begin
if (reset)
s = 0;
else
s[3] = din;
s[2] = s[3];
s[1] = s[2];
s[0] = s[1];
end
dout = s;
endmodule
4-bit Serial-in to Serial-out (SISO) Shift Register

GATE LEVEL MODELLING

BEHAVIORAL LEVEL MODELLING:

module Serial_in_Serial_out ( din ,clk ,reset ,dout );
output dout ;
reg dout ;
input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
reg [2:0]s;
always @ (posedge clk or posedge reset)
begin
if (reset)
dout = 0;
else
s[0] = din ;
s[1] = s[0] ;
s[2] = s[1] ;
dout = s[2];
end
endmodule
4-bit Parallel-in to Serial-out (PISO) Shift Register

GATE LEVEL MODELLING

module piso1(sout,sin,clk);
output sout;
input [3:0]sin;
input clk;
wire [3:0]q;
inv u1(p,sl);
and1 u2(n,sin[1],p);
and1 u3(r,sl,q[0]);
or1 u4(s,n,r);
and1 u5(t,sin[2],p);
and1 u6(u,sl,q[1]);
or1 u7(v,u,t);
and1 u8(w,sin[3],p);
and1 u9(y,sl,q[2]);
or1 u10(z,w,y);
dff1 u11(q[0],sin[0],clk);
dff1 u12(q[1],s,clk);
dff1 u13(q[2],v,clk);
dff1 u14(q[3],z,clk);
assign sout = q[3];
endmodule
BEHAVIORAL LEVEL MODELLING:
module parallel_in_serial_out ( din ,clk ,reset ,load ,dout );
output dout ;
reg dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
wire load ;
reg [3:0]temp;
always @ (posedge clk or posedge reset)
begin
if (reset)
temp = 1;
else if (load)
temp = din;
else
dout = temp[3];
temp = {temp[2:0],1'b0};
end
endmodule
4-bit Parallel-in to Parallel -out (PIPO) Shift Register

GATE LEVEL MODELLING

BEHAVIORAL LEVEL MODELLING:

module PIPO ( din ,clk ,reset ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
always @ (posedge (clk)) begin
if (reset)
dout = 0;
else
dout = din;
end
endmodule
 SYNCHRONOUS COUNTER

4 BIT SYNCHRONOUS COUNTER USING D- FLIP FLOP

module a4bit_sync_dwn_cntr (c,q);

input c;
output reg [3:0] q;
always @ (posedge c)
begin
q <= q + 1;
end
endmodule

ASYNCHRONOUS / RIPPLE COUNTER

ASYNCHRONOUS UP COUNTER

GATE LEVEL MODELLING

4-BIT UP COUNTER USING BEHAVIORAL LEVEL MODELLING:

module upcounter(clk, clr,q);
input clk, clr;
output[3:0]q;
reg[3:0]tmp;
always @(posedge clk or posedge clr)
begin
if(clr)
tmp=4'b0000;
else
tmp=tmp+1'b1;
end
assign q=tmp;
endmodule

clr clk output

1 1 0000
0 0 0000
0 1 0001
0 0 0001
0 1 0010
0 0 0010
0 1 0011
0 0 0011
0 1 0100
0 0 0100
0 1 0101
0 0 0101

Output Wave for Up Counter:

ASYNCHRONOUS DOWN COUNTER

GATE LEVEL MODELLING

BEHAVIORAL LEVEL MODELLING:

module downcounter(clk,clr,q);
input clk,clr;
output [3:0]q;
reg [3:0]tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp=4'b1111;
else
tmp=tmp-1'b1;
end
assign q=tmp;
endmodule
clr clk output
1 1 1111
0 0 1111
0 1 1110
0 0 1110
0 1 1101
0 0 1101
0 1 1011
0 0 1011
0 1 1010
0 0 1010
0 1 1001
0 0 1001

Output Wave for Down Counter:

RIPPLE COUNTER USING D FLIP FLOP

module DFF(d,q,reset,clk);
input d,reset,clk;
output reg q;
always @(posedge reset or posedge clk)
begin
if(reset)
q=0;
else if(d) DOUBT PART
q=d;
else
q=q;
end
endmodule
 module RippleCounter(d,clk,reset,out);
input [3:0] d;
input clk, reset;
output [3:0] out; // 4bit
DFF a(d[0],out[0],reset,clk);
DFF b(d[1],out[1],reset,out[0]);
DFF c(d[2],out[2],reset,out[1]);
DFF dx(d[3],out[3],reset,out[2]);
endmodule

module RippleCounterTOP;
reg [3:0] d;
reg clk, reset;
wire [3:0] out;
RippleCounter r(d,clk,reset,out);
initial begin
d=0;clk=0;reset=1;
end
always begin
#5 d=d+1; clk=~clk;
end
endmodule

MOD 10 COUNTER / DECADE COUNTER

GATE LEVEL MODELLING

BEHAVIORAL LEVEL MODELLING:

module counter(clk,rst,enable,counter_output);
input clk,rst,enable;
output reg [3:0]counter_output;
always@ (posedge (clk))
begin
if( rst | counter_output==4'b1001)
counter_output <= 4'b0000;
else if(enable)
counter_output <= counter_output + 1;
else
counter_output <= 4'b0000;
end
endmodule

MOD 12 COUNTER
GATE LEVEL MODELLING

BEHAVIORAL LEVEL MODELLING:

module counter(clk,rst,enable,counter_output);
input clk,rst,enable;
output reg [3:0]counter_output;
always@ (posedge clk or posedge rst)
begin
if( rst counter_output==4'b1001)
counter_output <= 4'b0000;
else if(enable)
counter_output <= counter_output + 1;
else
counter_output <= 4'b0000;
end
endmodule

MOD 13 COUNTER
GATE LEVEL MODELLING
module mod13(qo,clk);
output [3:0]qo;
input clk;
inv u1 (qd,q3);
inv u2(qc,q2);
and1 u3 (a,q1,q0,q2);
and1 u4(b,q3,q2);
or1 u5(t3,a,b);
and1 u6(c,q1,q0);
and1 u7(d,q3,q2);
or1 u8(t2,c,d); DOUBT PART
ASSIGN T1=Q0;
or1 u9(t0,qd,qc);
tff u10(qo[0],t0,clk);
tff u12(qo[1],t1,clk);
tff u13(qo[2],t2,clk);
tff u14(qo[3],t3,clk);
assign {q3,q2,q1,q0}=qo;
endmodule

BEHAVIORAL LEVEL MODELLING:

MOD 6 COUNTER
OUTPUT OF MOD 6 COUNTER
 JOHNSON COUNTER

GATE LEVEL MODELLING

BEHAVIORAL LEVEL MODELLING:

module dff(q,d,clk);
output q;
input d,clk;
reg q;
assign q=1'b1;
always @ (posedge clk)
q=d;
endmodule

module dff1(q,d,clk);
output q;
input d,clk;
reg q;
initial q=1'b0;
always @ (posedge clk)
q=d;
endmodule

module johnson(q,clk);
output [3:0]q;
input clk; not
(qc,q[0]);
dff u1(q[3],qc,clk);
dff1 u2(q[2],q[3],clk);
dff1 u3(q[1],q[2],clk);
dff1 u4(q[0],q[1],clk);
endmodule

RING COUNTER
GATE LEVEL MODELLING

RING COUNTER USING BEHAVIORAL LEVEL MODELLING:

module dff(q,d,c);
output q;
input d,c;
reg q;
initial q=1'b1;
always @ (posedge c)
q=d;
endmodule

module dff1(q,d,clk);
output q;
input d,clk;
reg q;
initial q=1'b0;
always @ (posedge clk)
q=d;
endmodule

module
ring(q,clk);inout
[3:0]q;
input clk;
dff u1(q[0],q[3],clk);
dff1 u2(q[1],q[0],clk);
dff1 u3(q[2],q[1],clk);
dff1 u4(q[3],q[2],clk);
endmodule

SEQUENCE GENERATOR
GATE LEVEL MODELLING

BEHAVIORAL LEVEL MODELLING:

PSEUDO RANDOM BINARY SEQUENCE GENERATOR (4-BIT):

module prbs (a,clk,clr);

input clk,clr;
output [3:0] a;
wire a
reg [3:0] temp;
always @ (posedge clk or posedge clr)
begin
if(clr)
begin
tmp=4’b1111;
end
else
begin
tmp={tmp[0] ^ tmp[1],tmp[3],tmp[2],tmp[1] };
end
end
assign a=temp;
endmodule
Truth Table:

clk clr output(a)

1 1 0001
0 0 0001
1 0 1000
0 0 1000
1 0 0100
 0 0 0100
1 0 1001
0 0 1001
1 0 1100
0 0 1100
1 0 0110
0 0 0110
1 0 1011
0 0 1011
1 0 0101
0 0 0101
1 0 1010
0 0 1010

Output Wave for Pseudo Random Binary Sequence Generator:

SEQUENCE DETECTOR
GATE LEVEL MODELLING

BEHAVIORAL LEVEL MODELLING:

module me1(x,clk,rst,y);
input x,clk,rst;
output y;
reg[2:0]state;
reg y;
always @ (posedge clk)
begin
if(rst==1)begin
state<=3'b000;
y<=0;
end
else
begin case (state)
3'b000:begin if
(x) begin
state<=3'b001;
y<=0;
end
else begin
state<=3'b000;
y<=0;
end
end
3'b001:begin if
(x) begin
 state<=3'b010;
y<=0;
end
else begin
state<=3'b000; y<=0;
end
end
3'b010:begin if (x)
begin state<=3'b010;
y<=0;
end
else begin
state<=3'b011; y<=0;
end
end
3'b011:begin if (x)
begin state<=3'b100;
y<=0;
end
else begin
state<=3'b000; y<=0;
end
end
3'b100:begin if (x)
begin state<=3'b000;
y<=0;
end
else begin
state<=3'b101;
y<=1;
end
end
3'b101:begin if
(x) begin
state<=3'b001;
y<=0;
end
else begin
state<=3'b000;
y<=0;
end
end
endcase
end
end
endmodule

JOHNSON AND RING COUNTER

4- BIT RING COUNTER
GATE LEVEL MODELLING

BEHAVIORAL LEVEL MODELLING:

module dff(q,d,c);
output q;
input d,c;
reg q;
initial q=1'b1;
always @ (posedge c)
q=d;
endmodule

module dff1(q,d,clk);
output q;
input d,clk;
reg q;
initial q=1'b0;
always @ (posedge clk)
q=d;
endmodule

module ring(q,clk);
inout [3:0]q;
input clk;
dff u1(q[0],q[3],clk);
dff1 u2(q[1],q[0],clk);
dff1 u3(q[2],q[1],clk);
dff1 u4(q[3],q[2],clk);
endmodule
4- BIT JOHNSON RING COUNTER

JOHNSON COUNTER using GATE LEVEL MODELLING

module johnson(q,clk);
output [3:0]q;
input clk;
not (qc,q[0]);
dff u1(q[3],qc,clk);
dff1 u2(q[2],q[3],clk);
dff1 u3(q[1],q[2],clk);
dff1 u4(q[0],q[1],clk);
endmodule

BEHAVIORAL LEVEL MODELLING: