Beruflich Dokumente
Kultur Dokumente
DSP
RF Demodulation
B-Mode
Color Flow
Spectral Doppler
Scan Control
SOC (DSP+MPU)
Scan Conversion
Speckle Reduction
System Control
O/S
Display
Storage
Multi-core DSP
Console Ultrasound Solution
Decimation B-Mode Color Doppler System Ctrl
RF Demod Detection Wall Filter FFT MMI
Compression Velocity Est Peak/Mean Est
. Scan Conv Power Est . PACs i/f
Mode Switch
Speckle Red Scan Conv Cineloop Mgmt
Probe
C6657 (~3.5w)
McBSP
DAC
1 to 4
DDR3
control
data
Probe
DM814x
McBSP
DAC ARM®
Cortex™-A8 DISPLAY
DSS
MSMC 800 MHz
66x (x2) L1P: 32KB LCD
1GHz L1D: 32KB
L1P: 32KB Shared
SATA
AFE L2: 4MB 32-bit L2 : 256KB
L1D: 32KB 333/666MHz Storage
DDR
L2: 512KB
DDR2/3 Graphics Image
SRIOx4
Engine Engine
USB
1 to 4
DDR3
Printer
Beam-former Multicore Navigator DDR3
lanes Switch Fabric
GEmac
64-bit
1.33GHz PACs
SPI HL50 PCIe PCIe GPMC
16-bit200MHz
Flash control
data
McASP
DAC
ARM®
674x+ Cortex™-A8 DISPLAY
DSS
750MHz 1GHz
L1P: 32KB L1P: 32KB
L1D: 32KB LCD
L1D: 32KB
L2 : 256KB
SATA
32-bit L2 : 256KB
333/666 MHz Storage
DDR
AFE DDR 2/3 Graphics Image
Engine Engine
USB
Printer
Switch Fabric
GEmac
FPGA
PACs
Beam-former
RF Demod PCIe GPMC
16-bit 200 MHz
Flash control
data
Probe
DM814x
AM 3874
McBSP
C66x DAC ARM®
Cortex™-A8 DISPLAY
DSS
66x (x8) MSMC 800 MHz
1GHz L1P: 32KB LCD
L1P: 32 KB Shared L1D: 32KB
SATA
AFE L1D: 32KB L2: 4MB 32-bit L2 : 256KB
333/666MHz Storage
L2: 512KB
DDR
DDR2/3 Graphics Image
SRIOx 4
Engine Engine
USB
DDR3
1 to 4 Printer
Beam-former Multicore Navigator DDR3
lanes Switch Fabric
GEmac
64-bit
1.33GHz PACs
SPI HL 50 PCIe x2 PCIe GPMC
16-bit 200MHz
Flash control
data
TeraNet
Memory Architecture
TCP3d
– 1MB Local L2 per Core L1 L2 L1 L2
– 1MB Multicore Shared Memory (MSM)
– Boot ROM,DDR3-1600MHz (32-bit)
– Address Translation & ECC
Memory Subsystem Peripherals & IO
Interfaces Multicore Shared Memory Controller
– 4x RapidIO rev 2.1 (1x4, 2x2, 1x2+2x1) DDR3- (MSMC)
32b SGMII McBSP
– 2 lanes PCIe Gen II Shared Memory 1MB
– 10/100/1000 Mbps Ethernet SGMII ports
HyperLink
SRIO PCIe EMIF
– Universal Parallel Port (16-bit) Muxed with EMIF -16 System Elements x4 x2 16
– I2C, SPI, 2x McBSP (Mux), 32 GPIO, 2 x UART, 4x
Timers64, Semaphore Power Management SysMon I2C
uPP UART
Debug EDMA SPI
Other
– 2x VCP2, 1x TCP3d
– Multicore debugging (embedded trace per core / chip)
– 0.8 mm pitch flip chip package
– 21x21 package
– Ext Temp Range: -55C to 105C
– 40nm High Performance Node
– Smart reflex
TeraNet
• Queue Manager, Packet DMA DSP DSP DSP DSP IP Interfaces
• Multicore Shared Memory L1 L2 L1 L2 L1 L2 L1 L2 GbE
Switch
Controller
Memory Subsystem SGMII SGMII
• Low latency, high bandwidth memory access
Multicore Shared Memory Controller
• 3-port GigE Switch (Layer 2) DDR3- (MSMC)
64b
• PCIe gen-2, 2-lanes Shared Memory 4MB Peripherals & IO
SRIO PCIe EMIF
• SRIO gen-2, 4-lanes System Elements x4 x2 16
• HyperLink Power Management SysMon TSIP I2 C
Hyper UART
• 50G Baud Expansion Port Debug EDMA Link
2x SPI
• Transparent to Software 50
10
DM8148 Processor
Cores
ARM Cortex A8™ (MPU) up to 1 GHz
C674x™ Floating Point DSP Core up to 750 MHz
Memory
ARM: 32KB L1I-Cache, 32KB L1 D-Cache, 256K L2 DM8148
DSP: 32KB L1I-Cache, 32KB L1 D-Cache, 256K L2 Fixed/ ARM
HD Video Display
Two DDR-800 Controllers Floating micro- Coprocessor
Coprocessors/Subsystem point DSP processor (x1)
On-Screen
HD VICP 2.0 Accelerator at 320 MHz Display
– Real-Time HD Encode /Decode C674x ARM 3D Graphics Resizer
Package
23x23, 0.8mm pitch, 684 ball BGA Memory Interfaces
• Via Channels enable low cost design rules -- 4 mil traces DDR3 SDIO
Async
SATA2
EMIF/
and 10/20 mil escape vias x2 /SD NAND
x3
• TI’s low-power Davinci SoCs allow flexibility on the back-end SoC for
various display options, image filtering and target identification on a
single chip:
– C674x DSP (fixed-/floating-point DSPs)
– Cortex-A8 for peripheral and communications control
– 3D graphics engine for rich UIs
– Rich display sub-system for multiple HD displays
– HD video encode/decode accelerators (Davinci devices only)
SITARA™ Middleware/
Frameworks
ARM® MPU
Multimedia
Codecs
C6-INTEGRA™
Common IDE/
ARM® MPU + DSP Tools
Example SW
DAVINCI™ & Demos
FREE Development license to use our Linux, Android, or WinCE Board FREE
Support Packages (BSP) / Software Development Kits (SDK)
* For use on our ARM, ARM+DSP, and ARM+DSP+Multimedia Processors
* Each release seamlessly and scalable works across all products
Medical Software Toolkit 2.0
Input Data Size (Post RF Demod) Scan Samples/ Bytes/ Ensemble kB/ Loading DSP ARM ms/fm
Lines Scan Line Sample frame
https://gstreamer.ti.com/gf/project/med_ultrasound/
Medical Imaging DSP
Value Proposition
New & innovative algorithms in software
Improved image quality & emerging features
Field upgrades, Flexibility, Adaptive coding
C64x+™
Deterministic signal processing architecture
Supports latest real-time O/S for predictable & reliable performance
Sitara™
C6-Integra™
Portable imaging applications
Davinci™
Low power SOC’s replace PC. (DSP+ARM, Graphics, Video accl…)
Longer battery life. Smaller form factor.
C66x™
Scalable platforms: PortableValuePremium
Code compatible family of products
R&D Savings
Reuse (code, hardware, development environment)
No hardware spins, eco’s, & timing closure bottlenecks
Time to Market
State of the art development tools: (Compilers, trace, emulation)
Develop & debug in high level language
Imaglib & Medical Software toolkit, 3d parties