Slide 1

Field Effect Transistors (npn)

drain collector

gate base
source emitter
FET BJT
3 terminal device 3 terminal device
channel e- current from emitter to collector e-
source to drain controlled current controlled by
by the electric field the current injected into
generated by the gate the base

extremely high input

impedance for base
6.071 Field Effect Transistors 1

There are many types of transistors in addition to the bipolar junction transistor (BJT)
that we have discussed so far. An important class of 3 terminal transistors is the field
effect devices. For these the control parameter is the electric field over the junction, as
opposed to the current of the BJT. Since an electric field is associated with a voltage, the
important advantage of the field effect devices is that there does not need to be a current
into the control element (the gate). This results in a very high input impedance and a
very low leakage current.
The easiest to understand are the junction field effect transistors (JFETs) which we will
discuss first and in some detail. The metal oxide semiconductor FET (MOSFETs) are
very important for digital logic implementations.
Slide 2

Types of FETs

• In addition to carrier type (N or P channel), there are differences in

how the control element is constructed (Junction vs Insulated) and
those devices must be used differently
npn
Depletion mode junction FETs (JFET)
pnp
npn
Metal oxide semi-conductor FET (MOSFET)
pnp
– depletion/enhancement mode
– enhancement mode

(insulated gate FETs, IGFETs, are the same as MOSFETs)

6.071 Field Effect Transistors 2

As with the BJTs there are always two flavors of transistors, npn and pnp. The difference
is the majority carrier (electrons or holes).

Since FETs are controlled by variations of the electric field over the jmction, it is possible
to build a capacitor into the control element and thus to further reduce the leakage
current. The metal oxide of a MOSFET forms the capacitor at the input of the control
element (the gate).
Slide 3

Basic FET Operation #1

The simplest example of a JFET starts with N-doped Si.

source N drain

source - terminal into which the carrier current is injected

(n-type ∴ e- carriers)
At this level, the device is simply a resistor. Therefore, current
flows through the channel in proportion to the drain/source
voltage.

6.071 Field Effect Transistors 3

We will start by describing the operation and control of a JFET. The basic action of a
JFET may be understood by considering a conducting channel.
Start with n-doped silicon and add two terminals on either end. The device is now a
resistor whose resistance is given by the doping level.
The three terminals of the JFET are labeled source, drain and gate. The source is
analogous to the emitter of the BJT. The source is the source of the majority carrier. So
in an n-type material, the carriers are electrons and the source is thus the source of
electrons.
The drain is analogous to the collector of the BJT, and so the majority carrier current
flows from the source to the drain. Again in n-type material the carriers are electrons and
the conventional current flows in the opposite direction.
Slide 4

Basic FET Operation #2

Add a gate structure to form a channel.

gate
P

source N drain

gate
The two gate regions are actually connected together to define a
channel for the carrier current.
The control of the FET current (resistance) is gained by changing
the size of the depletion zones surrounding the gates.

6.071 Field Effect Transistors 4

The gates are two regions of p-type material that are arranged to create a channel for
conduction from the source to the drain. The two gate regions are almost always
connected together so that the user sees only one gate connection.
Notice, the above device is an npn JFET since the source is n-type, the gate is p-type and
the drain is n-type. Do not look down from the gate, channel, gate and call this a pnp
junction.
Slide 5

Basic FET Operation #3

Surrounding each gate is a depletion zone, as there is for any PN
junction.
gate
depletion zone P

source N drain

depletion zone
gate
The depletion zone reduces the effective size of the N-doped
channel and thus increases the apparent resistance of the channel.
By modulating the drain to gate potential, the electric field in the
depletion zone between the gate and drain varies and thus the size
of the depletion zone.

6.071 Field Effect Transistors 5

As with every pn junction there is a depletion zone surrounding the gate. This depletion
zone of course reduces the cross-sectional area of the n-type channel that is available for
electron conduction.
The action of the JFET is governed by varying the gate to drain potential and thus by
modifying the size of the depletion zone.
Slide 6

Basic FET Operation #4

depletion zone
P

N
VDS

Here the drain to source voltage, VDS, is equal to the drain to gate
voltage. As VDS increases, the depletion zones move together; and
the source resistance increases.

6.071 Field Effect Transistors 6

A simple example is to ground the gate voltage to the source so that the drain to gate
voltage is equal to the drain to source voltage. As the drain to gate voltage is increased,
the depletion zone increases and thus the conduction of the channel decreases.
For small voltages the resistance increases with voltage and this is described as the
ohmic region.
Above the pinch-off voltage the channel is saturated and the resistance becomes constant.
The pinch-off voltage may be pictured as the voltage where the depletion zones from the
two gates meet.
Slide 7

Basic FET Operation #5

Define an apparent resistance across the FET, the channel

resistance RC.
P

ID
N
VDS
P
V
RC =
ID I

VDS
6.071 Field Effect Transistors 7

We will characterize the device by the junction’s effective resistance. Now of course the
typical measurement to characterize a transistor is to measure the drain current as a
function of the drain-source voltage for a set of currents (or voltages) applied to the gate.
Recall that this is exactly how we ran the tests on the BJT.
Once we have measured the drain current as a function of the drain-source voltage we
have the information to calculate an effective DC resistance for this operating point.
Slide 8

Channel Resistance of FET

ID RC

IP

VP VBR VDS VP VBR VDS

• As VDS increases, the depletion zone grows and the effective

resistance slowly increases.
• As VDS = VP (the pinch-off voltage) the two depletion zones
meet, no additional current can flow and the resistance increases
rapidly with VDS.
• At VBR there is a “drain-to-gate avalanche”, which we will
describe later.
6.071 Field Effect Transistors 8

At left is the drain current vs the drain to source voltage for a grounded gate.
The region from zero to the pinch-off voltage is the ohmic region, the flat region is the
saturation area and at higher voltages there is a breakdown region where the conduction
of the channel increases quickly. Many devices will be destroyed if operated in this
breakdown region, though (just like zener diodes) there are devices that are designed to
function in this avalanche region.
The plot at right shows the corresponding resistance. In the ohmic region the resistance
increases only slowly, and then in the saturation region the resistance increases more
quickly.
It is important to notice that the drain current of the JFET is independent of the drain-
source voltage in the saturation region. As we will see shortly, in this region the drain
current remains very sensitive to the drain-gate potential.
So, if we want to obtain control via the gate then typically we will design the device to
operate in the saturation region. If however we are looking for control based on the drain
voltage, then the device will be positioned in the ohmic region.
Slide 9

Gate Control of FET

• The size of the depletion zone can be increased by reverse biasing
the PN junction at the gate, therefore the gate bias controls ID, and
since the gate is reverse biased there is essentially no gate current.
ID

VDS IB
VGS=0
-1V
-2V N

VP VDS
P
-VGS

VGS
N
P ≡ VGS

6.071 Field Effect Transistors 9

Here we show the variation of the IV curve as a function of the gate voltage. Recall that
at pinch-off the depletion zones of the two gates have met, and so as the gate voltage is
changed this operating point is moved. It is most common to reverse bias the gate (as
shown in the circuit) thus increasing the field over the PN junction and correspondingly
increasing the size of the depletion zone for a constant drain-source voltage.
Notice that as the gate is reverse biased the pin
Slide 10

JFET Specification

ohmic region - JFET acts as a

variable resistor.
ID saturation region - JFET is
independent of the drain
VGS = 0 source voltage, but strongly
IDSS VGS = -1V dependent on gate voltage.
VGS = -2V VOFF,GS ≡ cut-off voltage, gate-
to-source voltage where the
VDS JFET acts as an open circuit.
saturation
ohmic region BV ≡ drain-to-source voltage that
region breakdown DS
leads to current break
through of the JFET channel.
IDS ≡ drain current for zero gate bias.

6.071 Field Effect Transistors 10

Slide 11

JFET Performance
  2
VGS  VDS  V
I D = I DSS −21 −  −  DS
 ; ohmic
  V V
GS ,OFF  GS ,OFF  GS ,OFF   region
V
2
 VGS 
= I DSS  1 −  ; saturation region
 VGS ,OFF 

Some typical values:

IDSS ~ 1mA → 1A
VGS,OFF ~ -0.5V → -10V
BVDS ~ 6V → 50V

6.071 Field Effect Transistors 11

The design of FET circuits is usually performed with relatively simple equations for the
drain current in terms of device parameters and the operating conditions. These of course
depend on if the operating point is in the ohmic or saturation region.

Since the device performance should not depend critically on the circuit parameters, a
few simplifying shortcuts are often taken and at the end the circuit is evaluated with a
simulation package (like spice). It helps greatly to be able to break a design down into its
functional parts and then to roughly see how each should operate. This of course takes
practice and here we will lead you through the process.
Slide 12

Transconductance

∂I D : the rate of change of the drain current

gm =
∂VGS VDS
with a change of the gate bias

The transconductance is useful for the mode of a JFET as a

voltage controlled resistor, and has units of (1/resistance), mhos.

1 ID
gm = = gm
RDS VDS
0
I DSS VDS

2 I DSS
gm = − ≡ transconductance of a
0
VGS,OFF shorted gate.

6.071 Field Effect Transistors 12

An important, but not easy to understand, characteristic of a three parameter device is the
transconductance, gm. Recall the we are modeling the FET as a voltage controlled
resistor, therefore, the drain current is a function of the gate to source voltage. This of
course is seen in the IV plots of the FET for the saturation region. The transconductance
is the rate of change of the drain current with a change in the voltage at constant drain-
source voltage.
The units of transconductance are inverse ohms (mhos).
Generally the data sheets report both the transconductance for a shorted gate.
Often in the analysis of FET circuits the circuit properties can be reduced to a function of
the transconductance.
Slide 13

JFET Example
18V
ID Find ID
IDSS = 8mA, VGS,OFF = -4V

Since VDS appears to be greater than a few volts

and less than the breakthrough voltage,we will
assume that the JFET is in the saturation region.
1kΩ  2
VGS   V 
2

∴ I D = I DSS 1 −  = 8mA 1 − GS 
 VGS ,OFF   −4V 
Note that the gate voltage is zero, and therefore the gate to source
Voltage is minus the source voltage.
VGS = VG - VS = -VS = -ID 1kΩ
∴ ID = -VGS/1kΩ

6.071 Field Effect Transistors 13

Here we explore a simple example of a JFET derived current source. The gate is shorted
to ground (note it is not shorted to the source). The source resistor introduces a source
voltage and thus there is a negative gate-source voltage.
Let’s find the drain current as a function of the source resistor.
The drain voltage is large enough that we can assume that the device is working in the
saturation region. Therefore we can immediately write down the drain current as a
function of the gate-source voltage.
The gate source voltage is just minus the source voltage, and the source voltage is the
voltage drop of the drain current through the source resistor.
Slide 14

JFET Example (continued)

So substituting into the above equation:

2
−VGS  V 
∴ ID = = 8mA 1 − GS 
1kΩ  −4V 

This has solutions of VGS = -2V and -8V.

Note VGS,OFF = -4V ∴ the only valid range of VGS is 0 → -4V
If VGS = -2V, then ID = 2mA
VS = 2V, RJFET = 16V/2mA = 8kΩ
VDS = 16V

6.071 Field Effect Transistors 14

We set the two equations equal to each other and end up with a quadratic equation for the
drain current.
Since the FET turns off at -4V the -8V solution is not physical and we choose the -2V
solution giving a drain current of 2 mA.
From this we can also calculate the drain-source resistance of the device and the voltage
drop across the FET.
Slide 15

Light Dimmer
VDD

VGS,OFF = -4V, IDSS = 12mA

2
 VGS   V 
2

∴ I D = I DSS 1 −  = 12mA 1 − GS 
 VGS ,OFF   −4V 

lamp off
12mA lamp on
dimmer
ID

VGS
-4 -3 -2 -1 0
6.071 Field Effect Transistors 15

A second example of a FET application is as a voltage controlled resistor. Here we look

at the variation of the voltage drop across the FET to control the brightness of the lamp
(the brightness is a non-linear function of the current through the lamp). When the gate is
shorted to the source the drain current is high and the lamp is on. As the gate is
negatively biased, then the drain current is reduced and the lamp dims. This continues
until it is essentially off.
You could combine this circuit with the pervious one to make a lamp dimmer that
functions via a variable resistor, but it is often convenient to have a device that is voltage
controlled.
Slide 16

Source Follower

VDD
Analogous to the bipolar emitter follower
Vin amplifier. Provides no voltage gain, but
Vout does give a change in impedance, therefore
RS provides a current gain.

Where RS < Rload, then VS ≈ RSID

ID = gMVGS = gM(Vin - VS)
VS g RV
∴ = gM (Vin − VS ) or VS = M S in
RS ( + g M RS )
1
gM RS
Note Vout = VS, the gain is
( gM RS )
1 +

6.071 Field Effect Transistors 16

The JFET source follower is functionally similar to the BJT emitter follower. It also
provides no voltage gain but does provide a change in impedance and thus a current (and
power) gain.
Now we still use good design practices, so thinking of the source follower as a voltage
source, we arrange that the source resistor is much smaller than the load resistor and thus
we can ignore the load in our analysis.
The voltage drop over the source resistor is thus the source resistance times the drain
current. We can relate the drain current to the gate-source voltage via the
transconductance. And we see that the source voltage is also the output voltage.
Notice, that the typically the transconductance corresponds to a smaller resistor (about
200 ohms) than the source resistor and thus the gain is about 1.
Slide 17

Source Follower Amplifier

VDD

Vin
Vout
RB RS Rload

Vout RS
gain = = ; RB sets the bias of the
Vin RS + 1 JFET
gM

The capacitors are for filtering.

6.071 Field Effect Transistors 17

A common amplifier configuration of the source follower. If we strip it down to the

essentials, the capacitors are for removing DC, the gate resistor is for biasing, and the
load resistor can be ignored given the source resistance. Therefore, we see the same gain.
Slide 18

Common Source Amplifier

VDD

RD
Vout
Vin Rload

RB RS

Vout RD R B
gain = = −gM
Vin RD + RB

6.071 Field Effect Transistors 18

An amplifier with gain is the common source configuration, here the voltage is split over
a drain resistor, the FET and a source resistor. The source resistor only sets the DC
operating point, notice that it is bypassed by a capacitor and so for high frequencies the
source resistor is not in the circuit.
Slide 19

When to use JFETs

• JFET have much higher input impedances and much lower input
currents than BJTs.

• BJTs are more linear than JFETs.

• The gain of a BJT is much higher than that of a JFET.

6.071 Field Effect Transistors 19

In general JFETs are only used when a BJT would not conveniently work, such as when
the leakage current into the base of a BJT is too high.

For digital logic applications it has been important to use FETs, since they can be much
faster and they can dissipate less power. Most of these applications however use
MOSFETs which have even higher input impedances than JFETs.
Slide 20

JFET, Voltage Controlled Resistor

VDD
Operate in the linear ohmic region
R1 ID
Vout
Vcontrol

VDS
  
2
VGS  VDS  V
I D = I DSS −21 −  −  DS  
  VGS ,OFF  VGS ,OFF  VGS ,OFF  

VDS = VDD - R1ID; VGS = Vcontrol

   (V − R1I D )  (VDD − R1I D ) 
2
V
I D = I DSS −21 − control  DD −  
  VGS ,OFF  VGS ,OFF  VGS ,OFF  

6.071 Field Effect Transistors 20

Occasionally it is more convenient to operate in the ohmic region than in the saturation
region. The analysis does not in any way change, but the equations are bit messier. Here
we calculate the behavior of a JFET used as a voltage controlled resistor. As expected
you end up with a quadratic function again.
Slide 21

JFET, Voltage Controlled Resistor (continued)

 R 2I   2R I  (V − VDD )
∴  12 DSS  I D2 + 1 − 1 DSS 1 − control I D
 VGS ,OFF   VGS ,OFF  VGS ,OFF 
 2V  V  V2 
= −I DSS  DD 1 − control  + 2 DD 
VGS ,OFF  VGS ,OFF  VGS ,OFF 

For IDSS = 12mA, VGS,OFF = -5V,

ID (mA)
VDD = 10V, R1 = 2kΩ:

Vcontrol (V)
6.071 Field Effect Transistors 21
Graphs produced with Mathematica™

The curve was drawn with Mathematica to show the variation in the drain current with
the input voltage. This can be a useful means of providing a precise and controllable
offset.
Slide 22

The Effective Resistance of the JFET

VDS VDD
RJFET = = − R1
ID ID

RJFET (Ω)

Vcontrol (V)
Graphs produced with Mathematica™

6.071 Field Effect Transistors 22

Given the variation in current it is a simple enough process to report it as a resistance,

again via mathematica. Notice that in the ohmic region we can permit the gate - source
voltage to be positive.
It usually is wise in any application to also calculate the power dissipated in the FET,
which of course will be a function of the control voltage. Here of course the maximum
power is dissipated when the FET resistance is equal to the drain resistor.
Slide 23

Electronic Gain Control

Vin Vout
RC + RF
gain =
RC RC
RF

∴We can achieve an electronic control by replacing the control

resistor by a JFET:

Vin Vout

Vcontrol
RF

6.071 Field Effect Transistors 23

We will see next lecture that op-amps provide convenient differential amplifiers and that
their gain is controlled by the feedback resistors. A JFET makes a very convenient
voltage controlled resistor and thus a voltage controlled gain.
Slide 24

Frequency Dependence of yfs

VDD
bypass
RL Vout

VDS
Vin 1MΩ
∆I
recall yfs =
∆VGS VDS

Vin = VGS ; Id = yfs·Vin

VDS = VDD - Id · RL; VDS = VDD - yfs·Vin · RL

Vout ≡ AC part of VDS = yfs·Vin · RL

6.071 Field Effect Transistors 24

Here is a test circuit for measuring the frequency dependence of the transconductance
(here yfs as it is often reported for high frequencies). The large gate resistor is only for
stability.
Slide 25

JFET Symbols

drain drain

gate gate
source source
NPN PNP

• Often the gate areas are doped to different extents leading to the
specifications of drain/source.
• For some devices the drain and source are interchangeable.
• Occasionally, the two gates are not interconnected leading to a
four-terminal device.

6.071 Field Effect Transistors 25

As with BJTs there are both npn and pnp type JFETs, the NPN are often called n-channel
to avoid any confusion with the gate configuration.

The drain and source may be interchangeable, or not depending on their relative dopant
levels.
17 26-28

Go to the manufacturer’s web site to obtain a datasheet of their product. Please follow
these steps:

1. Go to the web site for Fairchild Semiconductor: http://www.fairchildsemi.com/

2. View the conditions of use for the web site by following the link on the home
page called Site Terms & Conditions, or by following this link:
http://www.fairchildsemi.com/legal/index.html
3. Return to the home page.
4. In the search box, enter the product number 2N5457 into the search box, select
“Product Folders and Datasheets” and click “go”. You want the datasheet for N-
Channel General Purpose Adapter.
5. You will be presented with several options (download PDF, email for example).
Select how you would like to receive this datasheet.
Slide 29

MOSFET #1
Metal-oxide-semiconductor-field-effect-transistors are quite
different than JFETs and come in a potentially confusing set of
varieties.
The defining feature is that the gate is capacitively coupled.
gate
source drain
metal
insulator
N N
P

enhancement-mode, npn MOSFET

source drain
absence of gate field ≡
∴ very low leakage current
6.071 Field Effect Transistors 29

MOSFETs are today more common than JFETs, but there are also a confusing array of
them and it is too much to cover in detail. The basic clever step was to realize that if you
only cared about the electric field from the gate to drain, then there was no need for a
galvanic connection and a capacitive connection would work as well. So in the MOSFET
there is a layer of insulator (glass) between the gate connector and the p-doped
semiconductor.
Notice that in the absence of a gate voltage the semiconductor is arranged such that there
is a NPN junction between the drain and source, and so this looks like two back to back
diodes and thus there is a very low drain to source current. Contrast this with the BJT
(where the gate region is small), and the JFET (where the drain and source form a
conducting channel).
Slide 30

Enhancement Mode MOSFET

A positive gate substrate

voltage induces negative
charge between the
source and the drain and VG
creates a n-type channel.
Current can now flow.
N N

substrate connector

6.071 Field Effect Transistors 30

In exploring the action of a MOSFET we start by looking at the capacitive junction of the
gate and ask what the charge distribution in the semiconductor will be for various gate
potentials. Notice that we are now interested in a potential difference between the gate
electrode and the substrate (at this moment we have not invoked the source or drain).
If the gate to substrate is positively charged, then we will concentrate electrons between
the n-type channels of the source and drain and current can flow. This is of course
majority carriers in the source and drain regions and minority carriers in the gate region
(but we have concentrated them).
This is the normal conduction mechanism for so called enhancement mode MOSFETs.
Slide 31

MOSFET Symbols

drain drain
substrate substrate
gate gate
source source
N-channel P-channel

Depletion Mode

drain drain
substrate substrate
gate gate
source source
N-channel P-channel
Enhancement Mode
6.071 Field Effect Transistors 31

In addition to enhancement mode MOSFETs there are also depletion mode devices. The
various symbols are shown above. In using these devices it is important to pay attention
to the substrate connection since this forms the second terminal of the gate capacitor.
Slide 32

Depletion Mode MOSFET

gate
source drain

insulator
N+ N N+
P

The source and drain regions are more heavily doped than the
channel, but at zero gate bias there is a current.

6.071 Field Effect Transistors 32

In depletion mode devices the second side of the gate capacitor is a small region of n-type
material. Now with no gate bias there is an n-type channel from the drain to the gate and
current flows. This gate region is lightly doped and the electric field in the gate capacitor
is used to manipulate the carrier concentrations in this region and obtain control of the
drain-source current.
Slide 33

Depletion Mode MOSFET #2

A negative voltage
between the gate and
substrate induces a
p-type channel into the
n-doped gate region and N N
turns off the source-drain
current. P

6.071 Field Effect Transistors 33

A negative bias across the gate substrate capacitor pulls holes from the p-type material
into the conduction channel and reduces the drain source current. In this operation the
device looks like a JFET, where a negative gate potential retards the drain current.
Slide 34

N-channel Depletion-mode MOSFET

Cutoff voltage, VGS,OFF - gate/source

voltage where ID≈0.
Breakdown voltage, BVDS - drain/source
voltage for current break-through
of the channel.
Drain current for zero bias, IDSS -
Transconductance, gm - rate of change of
drain current with with the change
of the gate/source voltage at a
particular drain/source voltage.

Graphs produced with Mathematica™

6.071 Field Effect Transistors 34

The IV plot for a depletion mode MOSFET data sheet, the other parameters are always
given somewhere in the data sheet.
Slide 35

Formulas: Depletion-Mode MOSFET

   V  V 
2
V
I D = I DSS −21 − GS
 DS
− DS

  VGS ,OFF  VGS ,OFF  VGS ,OFF  
In ohmic
2
 VGS 
I D = I DSS 1 − 
 VGS ,OFF 
In active
1
RDS = ; Drain-source resistance
gm
ID 2I DSS
gm = gm o ;gm o =
I DSS VGS ,OFF

6.071 Field Effect Transistors 35

As with the JFET there are a series of formula relating the drain current to the device and
circuit parameters. These are used just like those of the JFET.
Slide 36

Formulas: Enhancement-Mode MOSFET

VGS = 14V VGS,th - Threshold voltage for start

VGS = 12V of conduction.
VGS = 10V k - construction paramater.
I D,ON
=
VGS = 8V

(VGS ,ON − VGS ,th )

VGS = 6V 2
VGS = 4V

Ohmic: I D [
= k 2(VGS − VGS ,th )VDS − 1 2 VDS
2
]
I D = k (VGS − VGS ,th )
2
Active:
Graphs produced with Mathematica™
ID 1
gm = gm o ;RDS =
I D ,ON gm
6.071 Field Effect Transistors 36

The formulas for enhancement mode are quite similar, but include the so-called
construction parameter that describes the channel capacity. This is often explicitly listed
on the data sheet, so it is not necessary to calculate.
Slide 37

Transfer Characteristics of Three FET Types

Graphs produced with Mathematica™

6.071 Field Effect Transistors 37

Here we show the transfer characteristics of the three types of MOSFETs, (1) depletion,
(2) enhancement, and (3) both. The IV plots at right show the drain current vs drain
source voltage for various gate potentials. This is what is normally found in the data
sheets. The curves at left show how the drain current varies as a function of the gate
potential in the active region. This is not often shown, but it is a good way of viewing the
differences between the three types of devices. It also helps to see where the operating
points should be set.
Slide 38

Example: N-channel , depletion-mode MOSFET

Amplifier
VDD
RD MOSFET characteristics:
Vout IDSS = 10mA
Vin VGS,OFF = -4V
VDD = 4V
RD = 200Ω
1MΩ
The problem is to find the gain.

The action of the MOSFET is to be a voltage divider and to share

VDD over RD and RDS. Vin will control the value of RDS. The
1MΩ resistor is only included for stability and to correct for leak
Currents into the gates; so, let’s ignore it.
6.071 Field Effect Transistors 38

As an example we look at the operating point of a depletion-mode MOSFET amplifier.

The FET and drain resistor share the voltage and as the gate is reverse biased the the FET
shuts down and the voltage grows across the FET (the output voltage increases).
Slide 39

Example (continued)

Calculate the gain in the neighborhood of Vin=0, then

ID = IDSS = 10mA
and Vout = VDD - IDRD = 4V - (10mA)(200Ω) = 2V
To see how this changes with Vin, let’s calculate the
Transconductance at Vin = 0.
2I DSS 20mA 1
gm o = = = 5 × 10 −3
VGS ,OFF −4V Ω
Recall that the transconductance gm=1/RDS.
 RDS 
and Vout =  VDD
 RDS + RD 

6.071 Field Effect Transistors 39

Since we are looking for a change in current (resistance) with the control voltage, we nee
to think about the transconductance, but first we need to decide about which point to
calculate the gain. Let’s look in the neighborhood of zero input voltage. Now the drain
current can be taken from the data sheet and the output voltage is found to be 2 V
(conveniently in the middle). We can also directly calculate the transcoductance which is
200 mohs. Since this gives us the drain source resistance we can calculate the gain.
Slide 40

Example (continued)

From our formulas,

 VGS  5 × 10 −3  Vin 
gm = gm 0 1 − = 1 + 
 VGS ,OFF  Ω  4V 
This gives the change in RDS with a change in Vin.
Now assume that RDS varies slowly so that
∆RDS << RDS ≈ RD. Under this case,
 ∆RDS 
Vout ≈ 2V +   ⋅ 4V
 400Ω 
and the change in Vout with ∆RDS is
∆RDS
∆Vout ≈
100
From gm = 1/RDS, we find RDS = 200Ω(1+Vin/4)-1

6.071 Field Effect Transistors 40

In this case lets assume a small signal and look for a linear solution around zero input
voltage. We will make a few assumptions and throw away a few terms to keep from have
a quadratic problem. Either way works and of course will give essentially the same
answer. Recall that all of the circuit parameters vary.
We rewrite the output voltage for small changes in the drain source resistance, and find
that the output voltage varies slowly with this.
Slide 41

Example (continued)
200Ω 200Ω ⋅ Vin
∆RDS = 200Ω − =
Vin 4 + Vin
1+ 4
Again we look around Vin ≈ 0, so Vin << 4 and
∆RDS ≈ 50W⋅Vin.Pulling this together then,
50Ω  1
∆Vout ≈ Vin =  Vin
100  2
So the gian is -1/2.

6.071 Field Effect Transistors 41

Expand the drain-source resistance in terms of the input voltage and then use the fact that
the input voltage is small to simplify this. The result is that the device is an attenuator
(has a gain of one half) rather than an amplifier. You should recognize that if we
increased the voltage (or reduce the drain resistor) we could increase the gain.
Slide 42

MOSFET

6.071 Field Effect Transistors 42

One of the most important uses of MOSFETs is to build logic circuits that dissipate very
little power. If we build the above MOSFET configuration we see that in one
configuration there is a current into the load, and not in the other.
Notice that the substrate is grounded to the source.
Slide 43

MOSFET

6.071 Field Effect Transistors 43

In a p-channel device the current is associated with the on state.

Here notice that the substrate is still grounded to the source (which is now at a positive
voltage).
Slide 44

MOSFET inverter

6.071 Field Effect Transistors 44

In complementary MOSFET logic (CMOS) the same gate is built from a combination of
p and n channel devices in such a fashion that there is no current flow in either logical
state. Of course no current means no power is dissipated.