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BER Instrumentation
Ö Design of Ex p eriment
OBJECTIVES:
1. To be able to describe BER Instrumentation
2. Determine the probability of error to occur upon setting up a noisy
communication channel
3. Demonstrate how the BER works
Moscare, Ace
Approach
Most of the time communications theories are hardly visualize
and its system are presented in block diagrams which can be
represented by mathematical equations. Within the TIMS module
most of this mathematical equations and communication
systems are compacted in a single module for students and
others to visualize the communication system, and thus the
proponents successfully conducted and finish a design of
experiment
Design
BER or bit error rate is a key parameter that is used in assessing systems
that transmit digital data from one location to another. Systems for
which bit error rate, BER is applicable include radio data links as well
as fiber optic data systems, Ethernet, or any system that transmits
data over a network of some form where noise, interference, and phase
jitter may cause degradation of the digital signal. Although there are
some differences in the way these systems work and the way in which bit
error rate is affected, the basics of bit error rate itself are still the
same. When data is transmitted over a data link, there is a possibility
of errors being introduced into the system. If errors are introduced into
the data, then the integrity of the system may be compromised. As a
result, it is necessary to assess the performance of the system, and bit
error rate, BER, provides an ideal way in which this can be achieved.
Unlike many other forms of assessment, bit error rate, BER assesses the
full end to end performance of a system including the transmitter,
receiver and the medium between the two. In this way, bit error rate, BER
enables the actual performance of a system in operation to be tested,
rather than testing the component parts and hoping that they will
operate satisfactorily when in place.
Fig.1 TIMs Model for BER instrumentation
(i) In normal mode, no clock signal should be connected to the logic gate’s CLK
input. The output will be an uninterrupted result of the X-OR gate.
(ii) In pulse mode, a clock signal must be connected to the logic gate’s CLK input.
The logic gate’s result will only be passed to the output during the clock’s HI
period. Therefore, if the logic gate’s result is HI (logic 1) the output will
appear as one pulse or as a sequence of pulses if the result is HI for more
than one clock cycle.
Experiment Procedure
1. First Step is to get all the necessary blocks of Tim’s model
that were going to use. The error counting utilities,
sequence generator, and a wideband true RMS.
2. Then connect the models based on the given model
diagram of the experiment.
3. The decoded sequence is also came from the sequence
generator so a second one is needed to conduct this
4. After connecting all blocks with each other and setting the
sequence generator next part is to the frequency counter
5. After setting up all the system
6. Remove the noise from the channel
7. Align the two sequence, to do this momentarily connect the
reset of the instrumentation sequence generator to the
output of the XOR gate of the error counting utilities.
8. Press the reset of the counter, were no digits should be
displaying
9. Press the TRIG button of the ERROR COUNTING UTILITIES
module.
10. Always remember to remove the noise before attempting
to align the two sequence.
Data and Results:
measurement of the bit error rate or BER is done with the modules of the
generators were then used and was then fed to the error counting and the
number of error bits count would be displayed on the frequency counter. The
counts or the outputs seen in the frequency counter is the result of the XOR in
the error counting utilities, wherein the output is from the comparison of
would be counted when the error generator would be fed along in either of