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Multiple Closed Loop System Control with Digital

PID Controller Using FPGA

Şirin AKKAYA Onur Akbatı and Haluk Görgün


Control Engineering Department Control and Automation Engineering Department
Istanbul Technical University Yildiz Technical University
Istanbul, Turkey Istanbul, Turkey
sakkaya@itu.edu.tr oakbati@yildiz.edu.tr, gorgun@yildiz.edu.tr

Abstract— PID (Proportional – Integral - Derivative) particularly PID [1]. And some works about how to
controllers are the most widely used closed loop controllers implement PID controller using FPGA has begun to be
due to their simplicity, robustness, effectiveness and published. In [2], the basic discrete PID equation and
applicability for much kind of systems. With the rapid algorithm is given, and in addition to PID algorithm in [3],
development of technology, implementation of PID controller some peripheral interfaces (analog to digital converter and
has gone several steps from using analog components in digital to Analog converter) are introduced, in [4], to verify
hardware to using some software-based program to execute the design performance a sine micro stepping driver system
PID instructions digitally in some processor-based systems. model of stepper motor is introduced. Different types of
And also, these developments have brought an alternative
digital PID algorithm based on parallel, serial and mixed
solution to implement PID instructions in Programmable
Logic Devices (PLD). Field Programmable Logic Array
architecture is implemented and simulated in [5]. The
(FPGA) is the most advanced members of PLDs. This paper structure proposed in [6] is based on a distributed arithmetic
presents the digital PID algorithm on FPGA. The controller algorithm where, a Look-Up-Table mechanism inside the
algorithm is developed using VHDL and implemented using FPGA is utilized and in [7] System on a Programmable
Altera DE0 Nano Board. As the controlled system, five axis Chip (SOPC)-based PID controller Intellectual Property
robot arm is selected, which have five dc motor and four (IP) core is implemented on FPGA using hardware
potentiometer to determine the positions of motors. The description language.
results show that digital PID controller and also multi-
For a low voltage synchronous buck converter, FPGA
feedback control systems can be implemented successively
using FPGA devices.
based PID controller is designed and implemented in [8].
And also, FPGA has been used in motion control systems
Keywords—fpga, digital pid, pwm, vhdl, robot arm which are employed all sort of robotic applications, such as
in [9] and [10], a technique has been adopted for the
I. INTRODUCTION generation of the control input for controlling the DC motor
driver circuit and decoding the optical encoder data for
The new and effective theories and design using it for speed feedback in the PID control loop. In [11],
methodologies are being continually developed in the an FPGA controller is designed and programmed to control
automatic control field, however, Proportional – Integral – the speed of the permanent magnet DC motor of a portable
Derivative (PID) controllers are still the most widely dough mixing machine, using digital PID algorithm with
adopted controllers in industry. Owing to the advantage of PWM signals. In [12], a simple approach for designing a
simple structure, good stability, reliable operation, fractional order FPGA based PI controller for controlling
robustness and effectiveness, the PID controllers are the speed of a DC motor is presented and in [13], for multi-
properly used in different areas such as aerospace, process axis systems a high performance PID IP core controller is
control, manufacturing, robotic, automation, transportation described. In [14] the design and implementation of a fuzzy-
systems and real time multi tasking applications. control based speed control IC for permanent magnet
The implementation of PID control has same synchronous motor is presented, with Simulink/Modelsim
evolutionary stages from the early mechanical and co-simulation and FPGA realization. And also robotic
pneumatic designs to software based microcontroller control applications are one of the most recent targeted
systems. But these systems encounter some difficulties such fields covered by FPGA. For a three degree-of-freedom
as overloading or computing speed limits to implement the (DOF) wafer-handling robot, three current vector
requirements of modern control systems. Recently, Field controllers, three position/speed controllers and one
Programmable Gate Arrays (FPGA) has become alternative trajectory planning are implemented in a single FPGA chip
solution for the realization of digital control systems, [15]. For a modular reconfigurable robot controller is
proposed which based on the Advanced RISC Machine
This project is supported by Yildiz Technical University Scientific (ARM) processor and FPGA [16]. A hexapod robot which
Research Projects Coordination Unit under rule 2012-04-04-YL02. has eighteen continuous servomotors, PWM controllers is
designed and implemented in [17] and for a humanoid robot algorithm given (3) is known as the absolute form or position
the FPGA implementation of nonlinear PID controllers is form of PID algorithm [19].
presented in [18].
In this paper, the design and implementation of a FPGA- B. The Controlled System
based digital PID controller for a five axis robot arm is To show the applicability of the algorithm in multi-
presented. The organization of this paper is as follows: In feedback control systems, a basic five axis robot arm
section II, digital PID controller algorithm, five axis robot selected as a controlled system is shown in Fig. 2.
arm and FPGA development board are described, in section
III, the implementation of analog input interface, digital
PWM block and digital PID block implemented in FPGA
and the results are discussed. In section IV, the conclusion
of the work is given.

II.STRUCTURE OF CLOSED LOOP CONTROL SYSTEM


The overall block diagram of the system is shown in Fig.
1.

r[ k ] e[k ] PID u[k ] Motor Robot y (t )


Ref PWM
+ Controller Driver Arm
Fig. 2. Five axes robot arm
-
b[k ]

The robot arm has a five axes pick-and-place manipulator


ADC which consists of mechanical parts forming a rotating base,
FPGA DE0
Nano Board
three links and a gripper with dc motors and rotary
potentiometers and motor driver units. Each of these axes is
Fig. 1. The block diagram of the system driven by a small DC electric motor. These five axes consist
of a shoulder, elbow and wrist having 180, 270 and 90
Where r[k] is the discrete reference signal, e[k] is the degree rotational limits respectively for vertical movement,
discrete error signal, b[k] is the discrete feedback signal, and the axes at base has 270 degree rotational limit for
u[k] is the controller output and y(t) is the output of the horizontal movement. The potentiometer is an electro
controlled system. In FPGA, there are three block; digital mechanic device used for measuring the angular position of
PID controller block, analog input interface and digital PWM the motor in terms of voltage levels. The motor driver unit is
block. an electronic circuit which links the controller and the
robotic arm; adjust the voltage level to control motor
A. Digital PID Controller direction and speed according to controller’s output. The
The PID algorithm consists of three basic modes as basic driver unit generally consists of H-bridge as an
Proportional mode, Integral mode and Derivative mode. The integrated circuit in a chip or can be built from discrete
general form of PID controller given in (1); components. L298 chip is well known H-bridge which
allows driving DC motor in both directions and adjusts the
1 t de(t )  speed with PWM inputs. A driver unit can drive two motors
u (t )  K p (e(t ) 
Ti  e(t )dt  T
0
d
dt
)  simultaneously, so three units are used to control five DC
motors.

Where Kp is a proportional gain, Ti is integral time The robotic arm is designed for training purpose, but
constant and Td is derivative time constant. For a small there is not enough information about the parameters of the
sample time Ts, (1) can be turned into a difference equation dc motor and the material, to obtain the mathematical model
with approximating the derivative mode by backward of the robotic arm, each of the joint is considered as a
difference approximation and the integral mode by backward separated system and the linear model of each axis (motor
integration rule. and mechanical load) are created by using model based
system identification technique. The basic idea of this
technique depends on applying a sinusoidal signal to a linear
Ts k T
u[k ]  K p (e[k ]  
Ti n  0
e[n]  d (e[k ]  e[k  1])) 
Ts
 system as an input; and measuring the sinusoidal output with
the same frequency but different amplitude and phase. The
model of the each joint is thought as motor and mechanical
Equation (2) can be written as below; load and the schematic diagram is shown in Fig. 3 and the
estimated transfer function is shown in (4) and (5) for each
joint of the robotic arm [20].
u[k ]  K p e[k ]  ui [k  1]  Ki e[k ]  K d (e[k ]  e[k  1])  

Where Ki is the integral gain, Kd is the derivative gain,


e[k] is the current error signal, e[k-1] is the previous error
signal and u[k] is the control signal. The discrete PID
Ra La
Channel 1 Channel 1
Channel 2
Rotor Channel 2
e (t) Tm(t)
a vb(t)  m (t)
Armatur
current Jm
i a(t)
Dm

Fig. 3. The diagram of the motor and the mechanical load [20]
Axis 3 Axis 4

Fig. 6. The graphics for axis 3 and axis 4 (Channel 1: 5.00 V/Div, 50.0

 m ( s) 1 /( Ra J m )   ms/Div - Channel 2: 50.0 mV/Div Time/Div - 50.0 ms/Div)

Ea ( s) ss  (1 J m )( Dm  ( K t K b Ra ))
To compare these signal values the mathematical model of
each joint is obtained for base, shoulder, elbow, and wrist

 m ( s) A  
respectively and the results are shown in Fig. 7.

Ea ( s ) ss  B 
 4 (s) 0.492

wrist E4 (s) s (s  30.9)
Where θm is the position of motor, Ea is the armature axis 4

voltage, Ra is the armature resistance, Kt and Kb the motor


3 (s) 0.8232
constants, Jm is the equivalent inertia of the motor and the elbow

E3 (s) s (s  28.10)
load and Dm is the equivalent constant of friction of the axis 3
motor and the load. To obtain the linear model of each joint  2 (s) 0.7374
of robotic arm the testing system is created as in Fig. 4. shoulder E2 (s)

s (s  24.55)
axis 2
Channel 1 Channel 2
Oscilloscope
15V pp x2 30Vpp
axis 1 1 (s) 0.58
+30 V

Power base E1 (s) s (s  19.44)
Opamp

Signal
M
Generator

Fig. 7. The mathematical model for each joint of robotic arm

Fig. 4. The testing system for system identification


C. FPGA Development Board
As seen in Fig. 4, the input signal (AC 30Vpp) which is given FPGA, a PLD is a semicustom component, which
the motor is shown in Channel 1 and the output signal which includes configurable logic blocks, input-output blocks and
is taken from potentiometer is shown in Channel 2 of interconnects. It has some important characteristics; highly
oscilloscope. The graphics for axes of robots is given in Fig integrated, fast computer speed, could be parallel
5 and Fig 6. programmed and online programmed. The proposed PID
controller algorithm is implemented with VHDL using the
Channel 1 Channel 1
Altera Corp. DE0Nano (Cyclone® IV EP4CE22F17C6N
Channel 2 Channel 2
FPGA) device. The components of this board are shown in
Fig. 8. This board introduces a compact-sized FPGA
development platform suited for to a wide range of portable
design projects, such as robots and mobile projects. It
features Cyclone FPGA with 22,230 logic elements, 32MB
of SDRAM, 2 Kb EEPROM and 64 MB serial configuration
memory device. For connecting to real-world sensors, it
Axis 1 Axis 2 includes a National Semiconductor 8-channel, 12 bit ADC
device, 13-bit, 3 axis accelerometer device, two pushbuttons,
Fig. 5. The graphics for axis 1 and axis 2 (Channel 1: 5.00 V/Div, 50.0 8 use LEDs, a set of four dipswitch, three expansion headers
ms/Div - Channel 2: 100.0 mV/Div Time/Div - 50.0 ms/Div)
[21].
IN0
IN1 SCLK ADC_SCLK
IN2
2x13 . CS ADC_CS
FPGA
Header . ADC DIN ADC_SADDR
. DOUT ADC_SDAT

IN7

Fig. 9. Signals to and from the ADC

The timing diagram of ADC is shown in Fig. 10;

Fig. 8. DE0 Nano FPGA Education and development board

The components which is used in the study; Cyclone IV


EP4CE22F17C6N FPGA, USB type-mini AB port to
connect the board to computer to power the board and
download the VHDL program to FPGA, 50 MHz clock Fig. 10. The Timing diagram of ADC[22]
oscillator which can use as a source clock, ADC and 26-pin
header to take the motors position values as a voltage level B. Digital PWM Block
and transmit these to FPGA as s digital value, push button
for reset the system and LEDs to see the same values about Pulse width modulation is a simple method of using
the program values. rectangular digital waveform to control an analog variable by
changing ON and OFF ratio or the output pulse in discrete
time domain. It is used in a variety of applications ranging
III.IMPLEMENTATION
from communications to automatic control. In this
In FPGA, three basic blocks are executed, which are application, pulse width modulation (PWM) block
Analog Input Interface Block, Digital PWM Block and, implemented within FPGA and adjusts on and off period of
Digital PID Block. In this section, implementation of these each terminal of the full H-bridges to control five DC motors
blocks is introduced. The FPGA design is generally at the robot axes.
synchronous, that means that the design is clock based and The total PWM period T can be stated as (6) and where
each rising edge allows all the D-flip flops to simultaneously Ton= ON time and Toff = OFF time.
take a new state. But, most of the designs need one more
clock which works in a different frequency. To solve this
problem, there are some techniques about clock domain  T  Ton  Toff  
crossing (CDC). In this design, a binary counter is created
(33 bits) triggered by 50 MHz main oscillator clock and The output voltage is calculated as (7), where Vout is the
suitable divided bits are chosen for ADC, digital PID and average output voltage, Vin is the input voltage and D is the
digital PWM blocks. duty cycle.
A. Analog Input Interface
The ADC performs the function of converting a  Ton 
 Vout   Vin , Vout  DVin ,  
continuous-valued analog signal into a discrete-valued digital T T 
signal. FPGAs are well suited for serial analog to digital  on off 
converters owing to serial interface consuming less
communication lines while the FPGA is fast enough to The simplest digital PWM architecture, counter-based
accommodate to high speed serial data. The DE0Nano board PWM, and can be easily implemented only by an n-bit
contains ADC120S02 analog to digital converter provides up counter and n-bit comparator shown in Fig. 11. The counter
to 8 channels of analog input and converts them into a 12-bit counts each positive transit of reference clock and when the
digital signal [22]. ADC receives analog signals via the eight value of counter is less than the digital settling code K (the
analog inputs from IN0 to IN7. When performing a output of PID controller or duty cycle), the output (A<B) of
conversation, the ADC reads the signal on one of these eight the comparator remains high level state until the content of
input channels and converts it to a digital output. These eight the counter is large then K [23]. Therefore, this output will
pins are part of 2x13 GPIO header. The ADC also has four generate a pulse width corresponding to duty cycle and a
wires connected to the FPGA and these wires are used to frequency.
control the ADC and allow communication between ADC
and the FPGA. ADC120S02 is a high speed, low power 12 f clk
n-bit
A
Counter
bit converter. In this study the first four channels of ADC is A<B
PWM
Output
used actively. The A/D is connected both the FPGA and the B
2x13 GPIO header as shown in Fig 9. K
n-bit

Fig. 11. Basic structure of counter based digital PWM[23]
The modulating signal is 12 bit digital value. The source There are various methods to determine PID
(reference) clock signal of FPGA is 50 MHz and the period parameters and in this paper, the proportional (Kp), integral
is 20ns. To represent 212  4096 level of modulation signal, (Ki) and derivative (Kd) gains are obtained from Matlab
20 4096 = 81920 ns period is necessary. This allows a Sisotool with the help of linear system model which
maximum PWM frequency of about 12.2 KHz. This obtained in Section II, based on step response. The basic
frequency is experimented on motors and found to be criteria to find these parameters, the overshoot for all robot
sufficient. axes are assumed to be zero. However, as far as theoretical
studies show proportional control satisfy, but in the real
C. Digital PID Block system owing to unmodelled nonlinear disturbance and
In FPGA, the digital PID control algorithm is dead-zones requires integral control. In this method at first
implemented and synthesized using Altera Quartus II, the Ki and Kd parameters are set to zero and the proportional
RTL level implementation of controller is described using gain is increased until the step response reaches the
VHDL language. Finally, the generated implementation file overshoot boundary. After that, Kp and Ki have been set to
is downloaded to the FPGA development board for testing. get desired fast control system with minimal steady state
The four closed loop digital PID algorithm is executed error and the result show that there is no need derivative
simultaneously in FPGA to control base, shoulder, elbow term so Kd is set to zero. The parameters for each axes is
and wrist motors. given in Table I.
In the loop, the first calculation is that the previous error
TABLE I. PID PARAMETERS
signal e[k-1] and the total previous integral signal ui[k-1] is
updated. Then the present error e[k] is obtained to subtract Axis 1 Axis 2 Axis 3 Axis 4
reference point from the output of the system. The reference Kp 40 50 60 130
and the output of the system are both 12 bits wide and the
sign of the result is checked to see if the error is positive or Ki 4 5 6 13
negative. If the error sign is positive or zero the sign bit is Below, the application results for a pick and place
set to ‘0’, otherwise is set to ‘1’. Then e[k], e[k-1] are experiment are given for each axis of robot. The reference
multiplied by the PID parameters. The sign bits of the position is calculated by using Matlab and the real time
multiplicands are found with XOR to get the sign bit of the motor position is obtained by using Quanser Q2 data
products. With the multiple 12 bit two signals, the result is acqusation board.
found as 24 bits. After two additions, the output of PID
2.2
controller is found 26 bits. As a result, 26 bits value is reference position
reduced to 12 bits duty cycle value. All of the values in PID real time motor position for axis 1
2
control algorithm are binary. In the algorithm there are no
decimal points. The block diagram of the digital PID
position (volt)

1.8
controller in FPGA is shown in Fig 12.

Sign Sign 1.6


1 Reg 1 Reg
12 Sign 12 12
Ref Check
Reg
r[k] e[k] e[k-1] 1.4

12
12
y[k] Sign Sign Sign
1 Reg Reg Reg
1 0 10 20 30 40 50 60 70
12 1 12
Kp
12
1 1 Kd
1
Ki 1 1 time (seconds)
Kd 24 Sign
24
Sign
24
Sign
Fig. 13. Reference and real time motor position for axis1
Reg Reg Reg
1 1

1 1.9 reference position


real time motor position for axis 2
Addition/Subtriction Addition/Subtriction 1.8

25
1.7
position(Volt)

Sign Limit
Sign 1 Reg Check
1.6
Reg 1 25

ui[k] Sign 1.5


1 Reg

Addition/Subtriction Reg 1.4


ui[k-1]

26
1.3

12 u[k]
Round
0 10 20 30 40 50 60 70
time (second)

Fig. 12. Digital PID implementation in FPGA


Fig. 14. Reference and real time motor position for axis 2
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