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Abstract—The following paper describes the design and parameters. Likewise, its accuracy influences the performance
implementation of an analog-to-digital converter (ADC) using an of the overall power supply. The implementation of the ADC
FPGA circuit – Artix 7, manufactured by Xilinx inc. The ADC on the FPGA leads to a more compact design, lower
implemented is intended to be part of a digital control circuit for component count and lower costs. Also, it can be reproduced
a DC-DC inverter. All blocks of the control circuit will be part of on the FPGA if more ADCs are required. Designing a custom
the FPGA circuit. The method described requires two successive made ADC leads to flexibility in choosing the sampling rate
conversions, namely voltage-to-time and time-to-digital. Both and resolution, as opposed to using a separate ADC (already
conversions will be presented in terms of design, physical available on the FPGA or as an ASIC), which features a
implementation and experimental results. Various ways to
predefined sampling rate. Custom made ADCs can be designed
improve the accuracy of the resulting conversion will be
discussed.
as strings of diode connected mosfets and D flip-flops. Such a
method was proposed in [1].
Keywords— analog to digital converter, digital control, FPGA, The analog to digital conversion proposed in this paper is
dc-dc converter. divided into two processes: a voltage to time conversion and a
I. INTRODUCTION time to digital conversion. In order to complete the voltage to
time conversion, a test signal is required. This test signal must
The digital control of power supplies provides several be periodical and must follow monotonic variations both
benefits over its analog counterpart such as increased accuracy during its increase and during its decrease. Such solutions have
of the control transfer function, self-calibration capability, the been proposed in [2], [3]. The resulting test signal is compared
ability to communicate with other devices, the reduction in the to the input voltage in order to generate a periodic logic signal
overall component count. The benefits do, however, come at a whose duty factor varies with the input voltage. This is the
price: an analog-to-digital conversion is required; the voltage to time conversion
computation of the duty factor takes a longer amount of time;
generating the duty factor requires a higher frequency counter. The time to digital conversion can be accomplished by
These drawbacks may restrict some of the design parameters of using a counter circuit. The result of the count during a defined
the dc-dc converter, such as the switching frequency, which period of time produces a time to digital conversion, but in
may hinder the miniaturization of the overall system. For this order to increase the accuracy of this conversion the counter
reason a careful design of the control block is required. clock frequency must be high. If the available clock frequency
is not high enough for the desired conversion accuracy, an
One way to implement the digital control of a power supply alternative method which relies on propagation time delays can
is to use FPGA circuits. They work at high frequencies be employed. A constant logic level is propagated through a
(hundreds of MHz) and offer the possibility to synthesize a string of delay cells for a defined duration, the duration being
broad range of circuits. Some of the resources available on an the input signal. At the end of the duration the number of delay
FPGA circuit are logic blocks, such as look-up tables (LUT), cells through which the constant logic level propagated is the
flip-flops, multiplexers or summers featuring carry look-ahead output of the time to digital conversion. Such converters have
capability, interconnection blocks and phase-locked loops for been proposed in [4-10].
frequency synthesis. The circuits implemented on an FPGA
function simultaneously, which leads to a decrease in II. METHODS
processing delays. Also, after the thorough validation of the The block diagram of the ADC is given in Fig. 1. It consists
design, it can be translated into an ASIC digital controller for of two cascaded stages: a voltage-to-time converter (VTC) and
power supplies. a time-to-digital (TDC) converter.
The analog-to-digital converter (ADC) is used primarily in
the feedback loop. It can, however, be part of the self-
calibration process as the front-end of the data acquisition Vin time digital
system. Its sampling rate and resolution are both important
VTC TDC
Fig. 1. The two stages of the described ADC.
t
E
°
UH
E u c t RC °
(E U L ) e ° T
ic (t ) §
¨ T ·
¸
°
R R ¨ ¸
°
° 1 e 2 RC
¨
U H ¨1 e 2 RC
¸
¸ E °
® T
The discharge equations are ¨
¨
¸
¸
°
° E
¨ ¸ °U e 2 RC
© ¹ ° L T
°
°
t ° 1 e 2 RC
¯
u c (t ) UH e RC
Fixed values for the E, R, C and the rectangular signal
t period T can control the high and low thresholds, UL, UH.
u R (t ) u c (t ) U H e RC The input voltage and the test signal are applied at the
ic (t )
R R R inputs of a comparator. Assuming the frequency of the test
The average capacitor current is 0A in steady state. signal to be constant, the output signal of the comparator will
be a rectangular signal whose duty factor will vary as the input
I
avg
0 A 'i
charge
'i
discharge voltage varies. The resulting high or low times at the output of
the comparator can be correlated with the input voltage. The
1 T test signal can be expressed as
³ i (t )dt 0A
T 0c u s (t ) U L ¦U i sin Zi t Mi
Vin and this leads to the fact that the threshold voltage at the
comparator input is located at a unique and well defined
time moment during each test signal period, the threshold voltage
Vtest being the test signal value for which the output of the
Fig. 2. The VTC.
comparator changes state. As a consequence, if the high time