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Timing, Clocking
Lecture 10: 1
Announcements
• Prelim 1 graded
– High: 60 (out of 60); Mean: 46.2; Median 46.8
– You can view your exam during instructor OH today,
TA OH tomorrow, or lab sections next week
Lecture 10: 2
FSM for Toggle Flip-Flop
• Input: T T Q
• Output: Q CLK
• Current state: S
• Next state: S* S* = T’S + TS’
Q=S
T=1
S* Q
S0
S1
S T=0 T=1
Q=0 Q=1
[0] [1] 0 0 1 0
T=0 T=1 T=0 1 1 0 1
Lecture 10: 3
Review: Pattern Detector Moore FSM
Reset
In = 1 In = 1 In = 1
In = 0 In = 0 In = 1
In = 0
0 0 0 0 0 0 0 0 0 0
1 0 1 1 1 1 1 0 1 1
S1*=S0•In+S1•In S0*=S0’•In+S1•In
Lecture 10: 5
Review: Pattern Detector Mealy FSM
In = 1
In = 1
Reset Out = 0 Out = 0
0 0 0 d 0 0 0 0 d 0 0 0 0 d 0
1 0 1 d 1 1 1 0 d 0 1 0 0 d 1
Lecture 10: 7
Traffic Light Controller
• 4-way intersection with traffic lights
• Opposing lanes sequence together
– 20 seconds dwell on green
– 5 seconds dwell on yellow
– 25 seconds dwell on red North
N
E
W
S
Lecture 10: 8
Four Scenarios
• E & W Green / N & S Red for 20 seconds
• E & W Yellow / N & S Red for 5 seconds
• E & W Red / N & S Green for 20 seconds
• E & W Red / N & S Yellow for 5 seconds
North
N
E
W
S
Lecture 10: 9
Traffic Light Controller States
• 10 states
– E & W Green / N & S Red1 for 5 seconds
– E & W Green / N & S Red2 for 5 seconds
– E & W Green / N & S Red3 for 5 seconds
– E & W Green / N & S Red4 for 5 seconds
– E & W Yellow / N & S Red for 5 seconds
– E & W Red / N & S Green1 for 5 seconds
– E & W Red / N & S Green2 for 5 seconds
– E & W Red / N & S Green3 for 5 seconds
– E & W Red / N & S Green4 for 5 seconds
– E & W Red / N & S Yellow for 5 seconds
R/Y G/R2
R/G4 G/R3
R/G3 G/R4
R/G2 Y/R
R/G1
Lecture 10: 11
Factoring FSMs
• Break FSM into multiple communicating FSMs
• Simplifies large FSMs
• May result in fewer states
Lecture 10: 12
Traffic Light Controller Using 2 FSMs
• Light Controller (LC) FSM has 4 states
– G/R, Y/R, R/G, R/Y
• Timer FSM controls when the LC FSM EW
advances to the next state
– Keeps LC in Green states for 4 clock cycles
Next
CLK
G/R
Green = 1
Next = 1
Next = 0
R/Y Y/R
Green = 0 Green = 0
Next = 0
Next = 1
R/G
Green = 1
Next
Timer LC
Green Lecture 10: 14
State Timer FSM
Next
G NG2
Next = 1 Next = 0
Green = 1
NG3
Next = 0
Next
Timer LC
Green Lecture 10: 15
Traffic Light Controller Operation
0s 5s 10s 15s 20s 25s 30s 35s 40s 45s 50s 55s 60s 65s
Clk
Next
Green
LC state
Timer state
East
West
Lights
North
South
Lights
Lecture 10: 16
Moore vs. Mealy
• States
– Mealy machines tend to have fewer states
• Different outputs on arcs (up to n2) rather than states (n)
• Timing
– Mealy machines react faster to inputs
• Combinational path between input & output may potentially
lower clock frequency
• Need to avoid combinational loop (asynchronous feedback)
when two FSMs are communicating
– Moore machines are safer to use
• Outputs change at clock edge (always one cycle later)
• Potentially higher clock frequency
Lecture 10: 17
FSM Discussions: True or False?
• The next state logic in Moore FSM only depends
on current state?
Lecture 10: 18
Propagation Delay (tpd)
• Time for change in input to change the output
• Typically specified between 50% points
IN
OUT
tpHL tpLH
X
Y
S
S•Y
S’•X
F
tp of AND gate
Lecture 10: 20
Glitch (Hazard)
• Unplanned momentary switching of an output
• Types of glitches
– Static 1-hazard: Input change 1 1
causes output to go from 1 to 0 to 0
1 (should have stayed 1)
1 1
– Dynamic hazards: Input change 0 0
causes a change from 0 to 1 to 0
to 1 or from 1 to 0 to 1 to 0 (there
1 1
should be just one change)
0 0
Lecture 10: 21
Glitch Example
• Glitches are typically caused by unequal signal
propagation delays through the circuit
Assume X and Y are 1
S changes from 1 to 0
X 1 S’•X
0→1 0 →1
S 1→0 F 1→0→1
1→0 1→0
Y 1 S•Y
Lecture 10: 22
Timing Diagram
X S’•X
Showing Glitch S F
Y S•Y
X
Y
S
S’
S•Y
S’•X
F
glitch
Lecture 10: 23
Do Glitches Matter?
X S’•X
S F
S•Y
Y
CLOCK
must be glitch-free
Lecture 10: 24
Sequential Circuit Timing
X
Y
S
S’
S•Y
S’•X
F
CLOCK
X S’•X
S F
S•Y
Y
CLOCK
Lecture 10: 25
Glitch on F: No Problem
X
Y
S
S’
S•Y
S’•X
F
CLOCK
X S’•X
S F
S•Y
Y
CLOCK
Lecture 10: 26
Synchronous Circuits
combinational
logic
CLOCK
Lecture 10: 27
Before Next Class
• H&H 1.4, 3.4-3.5.5
Next Time
Timing Analysis
Binary Arithmetic
Lecture 10: 28