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1. PAL refers to
a) Programmable Array Loaded b) Programmable Logic Array
c) Programmable Array Logic d) None of the Mentioned
9. Which of the following logic families has the shortest propagation delay?
a) CMOS b) BICMOS c)ECL d) TTL
23. TTL devices consume substantially ______ power than equivalent CMOS devices at rest.
a) Less b) More c) Equal d) None of the Mentioned
25. A major advantage of DTL over the earlier resistor–transistor logic is the
a) Increased fan out b) Increased fan in
c) Decreased fan out d) Decreased fan in
Unit V
2. Which type of simulation mode is used to check the timing performance of a design?
a) Behavioural b) Switch-level
c) Transistor-level d) Gate-level
3. Which among the following is a process of transforming design entry information of the circuit into a
set of logic equations?
a) Simulation b) Optimization
c) Synthesis d) Verification
4. Which type of simulation mode is used to check the timing performance of a design?
a) Behavioural b) Switch-level
c) Transistor-level d) Gate-level
5. In VHDL, the mode of port does not define
a) An input b) An Output
c) Both input and output d) the type of bit
6. What do VHDL stand for?
a) Verilog hardware description language
b) VHSIC hardware description language
c) very hardware description language
d) VMEbus description language
7. Each unit to be modelled in a VHDL design is known as
a) behavioural model b) design architecture
c) design entity d) structural model
8. Which of the following describes the connections between the entity port and the local component?
a) port map b) one-to-one map
c) many-to-one map d) one-to-many maps
9. Among the VHDL features, which language statements are executed at the same time in parallel flow?
a. Concurrent b. Sequential c. Net-list d. Test-bench
10. In VHDL, which object/s is/are used to connect entities together for the model formation?
a. Constant b. Variable c. Signal d. All of the above
11.Which of the following are capable of displaying output signal waveforms resulting from
stimuli
applied to the inputs?
a) VHDL simulator b) VHDL emulator c) VHDL debugger d) VHDL locater
12. Which wait statement does follow a condition?
a) wait for b) wait until c) wait d) wait on
13. Which among the following is pre-defined in the standard package as one-dimensional
array type comprising each element of BIT type?
a. Bit type b. Bit_vector type c. Boolean type d. All of the above
14. Which among the following does not belong to the category of sequential statements?
a. If statements b. Process statements c. Loop statements d. Node statements
15. How are the design specifications represented in the behavioral modeling style of VHDL?
a. Boolean equation b. Truth table c. Logical diagram d. State diagram
Question Bank
Gate
6. Draw the circuit of two input NOR gate using CMOS.
7. Define TTL.
8. Explain the relational operator in Verilog HDL.
Part C
3. Explain the operation of totem pole TTL logic and Draw and explain CMOS NAND gate
4. Discuss about CMOS NAND and CMOS NOR gate with a suitable diagram
5. Discuss the various styles of modelling architecture in VHDL program with an example
7. . Write the VHDL code for 16:1 multiplexer,4:1 Mux,JK flip flop,D FF,Full and half adder