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Unit IV

1. PAL refers to
a) Programmable Array Loaded b) Programmable Logic Array
c) Programmable Array Logic d) None of the Mentioned

2. The inputs in the PLD is given through


a) NAND gates b) OR gates c) NOR gates d) AND gates

3. For programmable logic functions, which type of PLD should be used?


a) PLA b) CPLD c) PAL d) SLD

4. Which type of device FPGA are?


a) SLD b) SROM c) EPROM d) PLD

5. The difference between a PAL & a PLA is


a) PALs and PLAs are the same thing
b) The PAL has a programmable OR plane and a programmable AND plane,while the PLA
only has a programmable AND plane
c) The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a
programmable AND plane
d) The PAL has more possible product terms than the PLA

6. In an ECL the output is taken from


a) Emitter b) Base c) Collector d) None of the Mentioned
7. Transistor–transistor logic (TTL) is a class of digital circuits built from
a) Transistors only b) Bipolar junction transistors (BJT)
c) Resistors d) Bipolar junction transistors (BJT) and resistors.
8. . Standard TTL circuits operate with a __ volt power supply.
a) 2 b) 4 c) 5 d) 3

9. Which of the following logic families has the shortest propagation delay?
a) CMOS b) BICMOS c)ECL d) TTL

10. The disadvantage of RTL is that


a) It uses a maximum number of resistors
b) It results in high power dissipation
c) High noise creation
d) None of the Mentioned
11.Logic circuits can also be designed using
a) RAM b) ROM c) PLD d) PLA
12. PLA refers to
a ) Programmable Loaded Array b) Programmable Logic Array
c) Programmable Array Logic d) None of the Mentioned
13. 13.The memory which is used for storing programs and data currently being processed by the
14. CPU is called
a) PROM b) Main Memory
c) Non-volatile memory d) Mass memory
14. PLA contains
a) AND and OR arrays b) NAND and OR arrays
c) NOT and AND arrays d) NOR and OR arrays
15.In FPGA, vertical and horizontal directions are separated by
a) A line b) A channel c) A strobe d) A flip-flop
16. Which logic is the fastest of all the logic families?
a) TTL b) ECL c) HTL d) DTL
17. TTL is a
a) Current sinking b) Current sourcing
c) Voltage sinking d) Voltage sourcing
18. Special handling precautions should be taken when working with MOS devices. Which of the

following statements is not one of these precautions?


a) All test equipment should be grounded.
b) MOS devices should have their leads shorted together for
shipment and storage.
c) Never remove or insert MOS devices with the power on.
d) Workers handling MOS devices should not have grounding straps attached to their wrists.

19. What is the major advantage of ECL logic?


a).very high speed b) wide range of operating voltage
c).very low cost d) very high power

20. The primary advantage of RTL technology was that


a) It results as low power dissipation
b) It uses a minimum number of resistors
c) It uses a minimum number of transistors
d) None of the Mentioned

21. The ECL behaves as


a) NOT gate b) NOR gate c) NAND gate d) AND gate

22. TTL inputs are the emitters of a


a) Transistor-transistor logic b) Multiple-emitter transistor
c) Resistor-transistor logic d) Diode-transistor logic

23. TTL devices consume substantially ______ power than equivalent CMOS devices at rest.
a) Less b) More c) Equal d) None of the Mentioned

24. In DTL logic gating function is performed by


a) Diode b) Transistor c) Register d) Capacitor

25. A major advantage of DTL over the earlier resistor–transistor logic is the
a) Increased fan out b) Increased fan in
c) Decreased fan out d) Decreased fan in
Unit V

1. What do VHSIC stand for?


a) very high speed integrated chip
b) very high sensor integrated chip
c) Verilog system integrated chip
d) Verilog speed integrated chip

2. Which type of simulation mode is used to check the timing performance of a design?
a) Behavioural b) Switch-level
c) Transistor-level d) Gate-level
3. Which among the following is a process of transforming design entry information of the circuit into a
set of logic equations?
a) Simulation b) Optimization
c) Synthesis d) Verification
4. Which type of simulation mode is used to check the timing performance of a design?
a) Behavioural b) Switch-level
c) Transistor-level d) Gate-level
5. In VHDL, the mode of port does not define
a) An input b) An Output
c) Both input and output d) the type of bit
6. What do VHDL stand for?
a) Verilog hardware description language
b) VHSIC hardware description language
c) very hardware description language
d) VMEbus description language
7. Each unit to be modelled in a VHDL design is known as
a) behavioural model b) design architecture
c) design entity d) structural model
8. Which of the following describes the connections between the entity port and the local component?
a) port map b) one-to-one map
c) many-to-one map d) one-to-many maps
9. Among the VHDL features, which language statements are executed at the same time in parallel flow?
a. Concurrent b. Sequential c. Net-list d. Test-bench
10. In VHDL, which object/s is/are used to connect entities together for the model formation?
a. Constant b. Variable c. Signal d. All of the above
11.Which of the following are capable of displaying output signal waveforms resulting from
stimuli
applied to the inputs?
a) VHDL simulator b) VHDL emulator c) VHDL debugger d) VHDL locater
12. Which wait statement does follow a condition?
a) wait for b) wait until c) wait d) wait on
13. Which among the following is pre-defined in the standard package as one-dimensional
array type comprising each element of BIT type?
a. Bit type b. Bit_vector type c. Boolean type d. All of the above
14. Which among the following does not belong to the category of sequential statements?
a. If statements b. Process statements c. Loop statements d. Node statements
15. How are the design specifications represented in the behavioral modeling style of VHDL?
a. Boolean equation b. Truth table c. Logical diagram d. State diagram
Question Bank

1. Write down the comparison between PROM,PLA & PAl.


2. Give the difference between TTL & RTL
3.Explain the features of transfer logic

4. Draw and explain three input TTL NAND gate


5. With a neat diagram, explain the working of CMOS NAND

Gate
6. Draw the circuit of two input NOR gate using CMOS.
7. Define TTL.
8. Explain the relational operator in Verilog HDL.

9. Write the VHDL program for full adder

10. Write the VHDL code for half adder circuit


11. Write short notes on test bench.

12. Explain any two VHDL operators with example

13.Explain process in VHDL with syntax.

Part C

1.Problem in PAL & PLA


2. Write the working of two input TTL NAND GATE and Write short notes on noise margin and

propagation delay of logic families

3. Explain the operation of totem pole TTL logic and Draw and explain CMOS NAND gate

4. Discuss about CMOS NAND and CMOS NOR gate with a suitable diagram

5. Discuss the various styles of modelling architecture in VHDL program with an example

6. Explain in detail the the structure of HDL behavioral Descriptions

7. . Write the VHDL code for 16:1 multiplexer,4:1 Mux,JK flip flop,D FF,Full and half adder