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EE 582-001

Hardware Description Languages and Programmable Logic


Course Syllabus
Fall, 2004

Instructor: Dr. J. Robert (Bob) Heath

Office: 475 F. Paul Anderson Tower ((859) 257-3124)


Email: heath@engr.uky.edu
Web Page: http://www.engr.uky.edu/~heath

Office Hours: M (1:30 p.m. - 3:00 p.m.)


W (11:00 a.m. - 11:45 a.m. and 1:30 p.m. – 2:30 p.m.)

Text: 1. Sudhakar Yalamanchili, Introductory VHDL From Simulation to


Synthesis, Prentice Hall, 2001.
2. Xilinx Inc. Integrated Software Environment (ISE) Version 6.2i Series
Simulation, Synthesis and Implementation CAD Software Tools/Mentor
Graphics Modelsim HDL Simulator, 2004 (Available in CE Microlab
(CE228) and ME Microlab (Rms. 111 and 114 in Ralph Anderson
Bldg.)).

Meeting Schedule: MWF (12:00 p.m. - 12:50 p.m.) FPAT 255

Course Objectives: The objectives of this course are to provide students with a working
knowledge required to describe student developed digital logic system
designs in Hardware Description Languages (HDLs) at behavioral, register-
transfer, and structural (gate) levels; to verify their logic system designs via
exhaustive automated pre/post-synthesis HDL simulation test-benches; and
to then implement their final digital logic system designs to Complex
Programmable Logic Devices (PLDs) and/or Field Programmable Gate
Arrays (FPGAs) for final post-implementation (place and route) functional
and performance simulation testing and final design and operational
verification/validation. To meet these objectives, the following competencies
(Learning Outcomes!) should be imparted to the students:
1. An understanding of behavioral, register-transfer, and structural/gate
level HDL based digital system design capture, modeling, simulation, and
synthesis/implementation processes and their impact on digital system design
and manufacturing processes.
2. An understanding of programmable logic implementation media,
programming techniques, and architectures and their impact on digital
system design, synthesis, implementation, testing, and manufacturing
processes.

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3. The ability to develop behavioral, register-transfer, and structural/gate
level HDL models of digital circuits/systems and verify/debug those models
through HDL simulations.
4. The ability to synthesize behavioral, register-transfer, and
structural/gate level HDL models and to implement and experimentally test
the resultant design in programmable logic devices.
5. Hands-on experience with Computer-Aided Design (CAD) tools for
HDL design capture, design functional and performance
validation/verification via HDL simulation testing, and
synthesis/implementation of HDL models as well as tools for generating
configuration data, programming, and testing the target programmable logic
devices.

Course Outline:I. Digital System Design Flow and Hardware Description Languages
(HDLs).
II. Very High Speed Integrated Circuit Hardware Description Language
(VHDL).
III. Verilog and Other HDLs.
IV IV. HDL Modeling of Digital Systems.
V. Simulation vs. Synthesis/Implementation of HDL Models of Digital
Systems.
VI. VHDL Identifiers, Data Types, and Operators.
VII. Basic VHDL Language Concepts for Pre/Post-Synthesis Simulation
and Design Verification/Validation.
VIII. Introduction to Pre/Post-Synthesis Simulation, Testbenches, and
Design Verification/Validation Using Xilinx ISE/Mentor Graphics
Modelsim Series CAD Software.
IX. Programmable Logic Architectures Including PLA, PAL, CPLD, and
FPGA Architectures.
X. Basic VHDL Language Concepts for Synthesis to Programmable
Logic.
XI. Introduction to Synthesis to Programmable Logic Using Xilinx ISE
Series CAD Software.
XII. Behavioral and Register-Transfer Level VHDL Modeling for
Simulation and Synthesis.
XIII. Structural Level VHDL Modeling for Simulation and Synthesis.
XIV. Sub-Programs, Packages, and Libraries.
XV. Basic VHDL I/O.
XVI. Detailed Xilinx ISE/Mentor Graphics Modelsim Series Software
Simulation, Synthesis, and Implementation Steps and Processes.
XVII. Examples of Complete Digital System Design Flow Process(es)
Using Xilinx ISE Series Software (Digital System Design, VHDL
Design Capture, Pre-Synthesis Simulation of Design for Design
Verification/Validation, Synthesis, and Implementation to FPGA
Technology Chips Including the Mapping, Place, Route, Bit

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Generation, and Programming Steps, Post-Synthesis and Post-
Implementation Functional and Performance HDL Simulation
Testing, and Final Experimental Testing of Hardware Prototype for
Validation/Verification of Correct Functional and Performance
Operation of Synthesized System.)

Homework: Homework problems from the text and instructor will be periodically
assigned. You will be provided solutions to all assigned homework problems.
You must work “all” assigned homework problems to do well in this course.

Design, HDL Design Capture, Synthesis, Implementation, And


Design Verification/Validation via HDL Simulation Testing
Projects: During the semester you will design several digital systems, capture
each design using VHDL and/or Verilog, verify correct design and
functional/timing operation of each logic system via pre-synthesis HDL
simulation, synthesize and implement your design to a Xilinx FPGA chip and
perform post-synthesis and post-implementation (place and route) HDL
simulation testing of your synthesized design as a final level of correct
design and functional and performance verification/validation. A brief
computer generated project report will be prepared for each design and
design verification project.

Example design, HDL design capture, synthesis, implementation, and HDL


simulation testing projects would include initially combinational logic
circuits/systems, sequential logic circuits/systems, followed by more
complex digital systems such as small general purpose and/or special
purpose computational systems or their functional units.

Grading: Our accreditation association and policy of the Graduate School require that there be
different assignments and grading criteria for undergraduate students and graduate
students in 400G and 500-level courses. For that reason, you will find differences in
course requirements and/or grading criteria in this class as follows:
1. Grades will be determined and assigned for each peer group separately; that is,
grades will be assigned to all undergraduates as a group and all graduate students
as a separate group.
2. All graduate students will perform one additional more significant digital
design, HDL design capture, synthesis, implementation, and HDL simulation
testing project as compared to the undergraduates. The graduate students will
prepare and give a classroom presentation of the additional project and results.

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Grade: 1. Three (3) Tests: (Sept. 20, 2004, Oct. 22, 2004, and Dec. 1, 2004) - 60%
2. Homework Problems from Text and Instructor Generated - 10%
3. Digital System Design, HDL Design Capture, Synthesis,
Implementation, and HDL Simulation Testing Projects - 30%

Your final grade will be determined by the number of points you


have earned from 100 possible as follows:
A: 90 - 100 pts.
B: 80 - 89 pts.
C: 70 - 79 pts.
D: 60 - 69 pts. (Undergraduates Only)
E: < - 60 pts. For Undergraduates and < 70 pts. For Graduate Students.

Make-up
Examinations: Make-up examinations will only be given to students who miss
examinations as a result of excused absences according to applicable
current university policy. Make-up examinations may be in a different
format from the missed examination, such as an oral exam, etc.

Class Attendance: Attendance of all class lectures is required to assure maximum course
performance. You are responsible for all business conducted within a class.

Cheating: Cheating will not be allowed or tolerated. Anyone caught cheating will be dealt with
according to applicable University policy. (Assignment of a grade of E for the
course).