Implementation of a DSP-based 20-bit
High Resolution Quasi-Absolute Encoder for
Low-Speed Feedback Control Applications
By Lee Wei Yan
White Paper
Abstract
Absolute encoders using optical technology often face
limitations in resolution and size. For example, to achieve
a higher resolution of up to 16-bits, the absolute encoder
has to be combined with an incremental pattern that is
strongly interpolated with external hardware and signal
conditioning circuits. Alternatively, design engineers may
use high-speed DSPs (digital signal processors) to imple-
ment signal processing algorithms and calibration coeffi-
cients that can be stored in non-volatile memory. The lat-
ter method enables the development of a fully integrated
solution that is small in size, coupled with an increase in ac-
curacy and resolution, which is not possible with conven-
tional encoders. However, the software overhead means a
limited read-out rate is available. These types of encoders
are only suitable for low-speed feedback control applica-
tions that require high accuracy. In this paper, we present
the DSP design approach, and the hardware and software
implementation of a quasi-absolute encoder solution.
Introduction
Avago Technologies has introduced a high accuracy 20-bit
resolution quasi-absolute encoder with DSP-based signal
processing. This encoder is built into a housed PCBA with
DC (direct current) stepper motor assembly and is able to
operate in a wide operating temperature range between
0°C to 90°C. It provides an ideal solution for closed-loop
control systems that demand high precision and repeat-
ability, as well as reliable performance, even in a high tem-
perature environment.
The encoding signals are provided by a 3-channel analog
optical encoder and a 1024 line codedisk with an index
track. The index marks are located at different intervals.
The encoder finds its absolute position by scanning two
consecutive indexes.
The high speed DSP chip implements real-time signal
conditioning, 1000 times software interpolation, and fac-
tory programmed error calibration. The encoder output
has a final resolution of 1,024,000 counts and an angular
position accuracy of +/-0.05° (mechanical degree). Abso-
lute position is available as 20-bit binary data through a
serial peripheral interface (SPI).
Hardware Implementation
Supply and Interface
The encoder module operates on a single 5V supply which
powers the encoder device. An on-board 3.3V voltage reg-
ulator supplies current to the DSP and amplifier blocks. A
10-pin connector provides the interface to connect to the
end application system for controlling the SPI communi-
cation and stepper motor drive.
Encoder Block
The encoder’s sine and cosine analog current outputs are
amplified by a pair of trans-impedance amplifier circuits
for interpolation by the DSP. The amplified signals are
then sampled by two built-in high-speed ADC (analog to
digital converter) channels. Here, the amplifiers’ gain and
offset voltage are set to match the ADC’s 3.3V range. The
rail-to-rail op-amp (operational amplifier) enables single-
supply operation, while providing high bandwidth and
dynamic range for the input signal from ground to the
supply voltage.
The amplified analog signals are also directed through
a pair of threshold circuits in order to generate digitized
versions of the signals that are 90 electrical degrees
(e.degrees) out of phase. These digitized signals then are
further directed into the DSP’s quadrature decoder hard-
ware circuit which drives an internal counter. This allows
the DSP to use the incremental signals to track the encod-
er’s rotation angle and direction, and synchronize it with
the index pulse triggering.
Figure 1. Functional block diagram
2
DSP Block
The DSP controller is a 16-bit fixed-point DSP core with
special hardware and peripherals, optimized for motor
control applications. The 50ns instruction cycle time offers
10 to 20 times the speed of traditional 16-bit microcon-
trollers and microprocessors, thus allowing for high speed
real-time algorithms.
Software Implementation
SPI
The SPI is configured to operate in Slave mode to interface
with the user application (Master). A read-out cycle is initi-
ated by the Master, by pulling the Encoder Select (CS) line
low, generating an external interrupt (Figure 2). The DSP
branches to an ISR (interrupt service routine), where the
entire encoder algorithm and SPI routine is handled. The
transmission length is always 16-bits. It takes two consec-
utive transmissions to read the encoder’s 20-bit position
data (high-byte comes first, then low-byte).
The maximum read-out rate available from the encoder is
20 kHz. This is due to the 50µs latency required by the DSP
to process the position data. The serial transmission is syn-
chronized by the clock pulse (CLK) at a maximum frequen-
cy of 1MHz. A parity bit is included for each transmitted
byte. The status bits indicate absolute mode/incremental
mode and high-byte/low-byte (Figure 2).
Figure 2. SPI interface timing waveforms

Interpolation Algorithm Offset and Gain Compensation

For resolution higher than the grating lines of the code- Offset, gain, and phase errors occur in the encoder signals
disk, the encoder position within a grating line is deter- due to misalignment and other non-idealities. These af-
mined by software interpolation. The electrical angle fect the overall accuracy of the encoder when the analog
between 0 to 360 e.degrees around the Lissajous circle is signals are interpolated. The offset and gain corrections
given by, are done in real-time by sampling the analog signals and
tracking the errors. Phase error is not compensated in real-
−1 H0 time, but corrected by a constant calibration factor pro-
θ = tan
H1 grammed at the factory.
Eccentricity Correction
Where,
Rotary encoders are affected by eccentricity issues due to
H0 = Sin value sampled by the ADC concentricity and assembly tolerances. The angular error
resulting from eccentricity is given by,
H1 = Cos value sampled by the ADC
−1 ε ε
θ = tan ≅ rad. (for small angles)
Rop Rop

Where,
ε = Eccentricity error
Rop = Optical radius

Figure 3. Lissajous circle formed by the ADC sampling data

For fast computational speed, the interpolation algorithm

uses a lookup table to implement the arc-tan function.

Figure 4. Eccentricity and angular error


Figure 5. Accuracy plot
Over one revolution of the codedisk, the eccentricity is pe-
riodic, and is a sinusoidal function of the shaft angle (Fig-
ure 5). The position error as a function of angle of rotation
is given by,
Δ P = (ε/Rop)×Sin(A) × (180/ π) mech.deg. Fast processing is possible with high performance DSP
Where,
ε = Total eccentricity
A = angle of rotation (relative to position error of zero)
To achieve +/-0.05° (mech.degree) accuracy, the allowed
eccentricity is,
ε (allowable) = θ × Rop = 0.05 × (π/180) × 11.5mm
= 10µm
This places a high constraint on assembly tolerance, and
since eccentricity translates directly into mechanical posi-
tion error (rather than error in the signals), it cannot be
compensated for with signal conditioning. However, this
problem is corrected by software calibration at the factory
during assembly.
Indexing Algorithm
At power-up, the encoder starts up in incremental mode.
Absolute mode is achieved by recognizing the unique
distances between the index marks on the codedisk. The
indexing algorithm needs to find two consecutive indexes
and compares against a lookup table stored in the flash
memory to determine the absolute position.
For product information and a complete list of distributors, please go to our web site:
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2007-2010 Avago Technologies Limited. All rights reserved.
AV02-0865EN - March 8, 2010
The indexing initialization can start from anywhere, and at
either direction. Absolute mode is found after a small rota-
tion, within a maximum initialization angle of 136° (mech.
degree).
Conclusion
The hardware and software implementation and opera-
tion of a high resolution quasi-absolute encoder were
presented. The DSP-based design combines high perfor-
mance within a small form factor, while providing a cost-
effective solution beyond what can be achieved with con-
ventional encoders.
The encoder is a Slave device, and requires an interrupt
stream from a Master (the application system) to run the
encoder routine in the ISR, in order to produce an out-
put. The encoder has a 1024 lines incremental track and
unique pattern index track codedisk for quasi-absolute
operation. It behaves like an absolute encoder after index-
ing initialization, which finds the absolute position within
a small turning angle upon power-up.
integrated with high speed ADC and hardware capture
inputs. The overall software overhead is optimized to give
a fast readout rate of 20 kHz by using algorithms based
on lookup tables (arc-tan interpolation and eccentricity
correction). The real-time offset and gain correction com-
pensate for signal imperfections to enable a high 1000x
interpolation factor for 20-bits total resolution. The soft-
ware error calibration (eccentricity correction) feature en-
sures +/-0.05° accuracy over the entire 360° rotation, and
eliminates the need for accurate mechanical alignment
during assembly.
This encoder application is best suited for closed-loop
control systems demanding high precision and repeat-
ability with operational speeds up to 240RPM (e.g., high
resolution surveillance cameras, robotics, semiconductor
handling systems, factory automation, etc.).
References
1. Avago Technologies' Super High Resolution 20-Bit
Quasi-Absolute Optical Encoder Datasheet, October
2007.
www.avagotech.com