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Microelectronic

Circuits
EEE F244
BITS Pilani
Pilani Campus ANU GUPTA
BITS Pilani
Pilani Campus

Current Mirror
Reference voltage/ current

BITS Pilani, Pilani Campus


Requirements

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


Characteristics

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


Sensitivity

gain

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


Sensitivity

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
References

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


Potential divider bias

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


Without Rs

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


With Rs

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


• With Rs

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


Passive reference voltage gen.
ckts.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


Passive reference voltage gen.
ckts.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


Active references—vgs
referenced
Vref V1 = 3 Vgs
S= 1

Not much gain

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


β = un cox (w/l )

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


How to generate bias current?

Generate stable Vref directly


Generate stable Iref, use it to generate voltage
Generate stable Iref, and mirror it.

Vref

BITS Pilani, Pilani Campus


Vgs referenced

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


Another approach to find
sensitivity
1
gm
v1 = vdd
1
v1
+R
gm
v1
iout = g m v1

Iout is not independent of variations in Vdd


BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Vbe referenced

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956


Non idealities
--Current transfer ratio (CTR) never 1

--Rout  less than infinite


λ effect Not flat

--Voltage range loss


At least Needs vdsat voltage
--Body effect
loss
Implementation—increasing Rout
• Cascode current source— use
source degeneration

For identical devices

CTR = 1
loss = 2 Vgs- Vt
Rout Rout = ro + ro + gm
Voltage loss
ro2
Double cascode
(1) Reducing voltage loss
3 Vgs- Vt
W/L =
2 Vgs- Vt
Vgs
Vgs

Vgs- Vt
Reducing voltage loss- contd.
(2) Reducing voltage loss

2 (Vgs- Vt)
2 Vgs- Vt

Vgs
MATCHING
Vgs- Vt PROBLEM

CTR ≠ 1
Wilson Current Source
Current sampling

Vout

Vgs Vgs

Use of current sensing


Ctr 1
Rout (gm ro)4 (1/gm)2 [ 1+ gmro]
Volt loss 2 Vgs- Vt
Loop gain=Gm β

BITS Pilani, Pilani Campus


Detailed derivation

• Rout of wilson mirror


Wilson Current Source- cont.
Gain boosting technique

2Vgs- Vt
2Vgs

Vgs Ctr = 1

Vgs Vgs
Vgs
BITS Pilani
Pilani Campus

End