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Application Spectrum CMOS taking over Bipolar/BICMOS

OC12 SAT TV/WLAN/OC48 OC192 OC768 RADAR
RKE IMT2000 Automotive Military
UWC136 Satellite Comm. 24 76...78 94
Terrestrial TV GSM Bluetooth HiperLAN home LAN
DECT/UMTS UWB MVDS
GPS BT WiMAX LMDS ITS

2020 12nm CMOS fT=790 fmax=1110

2017 16nm CMOS fT=630 fmax=890

Year of Introduction

2014 22nm CMOS fT=440 fmax=650

2011 32nm CMOS fT=320 fmax=480

2008 45nm CMOS fT=200 fmax=310

2006 65nm CMOS fT=140 fmax=220

2004 90nm CMOS fT=120 fmax=140

2002 130nm CMOS fT=132 fmax=160

2000 180nm CMOS

100MHz 1 GHz 10 GHz 100 GHz 1 THz

Frequency

Source: The International Technology Roadmap for Semiconductors: 2005 CMOS SiGe-BICMOS III-V (InP)

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SIA Roadmap : The law of Moore 500 to 45 nm CMOS technologies : 2007

10
L
µm
45
Analog/RF
40

35
1
30 Digital
25

20
0.1
15

10

5
0.01
0
1980 1985 1990 1995 2000 2005 2010
500 350 250 180 130 90 65 45 nm
Year
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1
500 to 45 nm CMOS technologies : 2008 500 to 32 nm CMOS technologies : 2009

30
Analog/RF Analog/RF
25

Digital 20

15

10
Digital
5

0
nm 500 350 250 180 130 90 65 45 32 nm

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Flash ADC towards 0.2 Volt Supply 0.125 pJ/conversion at 0.4 V supply

No biasing 1 pJ/conv
currents !
All clocked !

Calibrated with
off-chip ramp

Ref. Daly, .. ISSCC-2008, 30.8 Ref. Daly, .. ISSCC-2008, 30.8

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Table of contents Submicron MOST

1.  Nanometer CMOS IDS

vs
2.  Noise
3.  Distortion si IDS = Kʼn W (VGS-VT) 2
wi L
VGS
4.  Analog Signal Processing Kʼ ≈ µCox
gm VGSws VGSsv
5.  Efficient opamp design
vs IDS = Kʼʼn W (VGS-VT)
6.  Efficient Gm-C design
si
7.  Sub-1 Volt realizations wi VGS Kʼʼn ≈ vsatCox
Ref.: W. Sansen : Analog Design Essentials, Springer 2006 10 7 cm/s

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 Submicron & deep-submicron MOST Nanometer MOST : smaller gm
IDS IDS
vs
vs gmsat = WCoxvsat
si kT
VGSws- VT = 2n si 1
q wi W ~ L & Cox ~
wi VGS VGS L
VGSws VGSsv gmsat ≈ constant
IDS VGSws VGSsv gm
vsat
vs VGSvs- VT = 4nL
µ vs gmsat gmsat does not increase
si si with smaller L !!
wi VGS ~ L !! wi VGS
VGSw VGSsv VGSws VGSsv
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Maximum fT versus channel length L Table of contents

100
f (GHz) fm
fT µ 1.  Nanometer CMOS
fTsat fT = (VGS-VT)
2πL2 2.  Noise
0.2 … 1 V
vsat 3.  Distortion
fTsat =
10 2πL 4.  Analog Signal Processing

VCOʼs 5.  Efficient opamp design

VGS-VT = 0.2 0.5 1V fT
LNAʼs 6.  Efficient Gm-C design
5
1
7.  Sub-1 Volt realizations
.1 fT 1 L (micron) 10
Processors Ref.: W. Sansen : Analog Design Essentials, Springer 2006
100
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Noise and dynamic range Gate current

Increases with vsat For 0.1 mm CMOS :

Thermal noise :
tox ≈ 2 nm
2/3 L JG ≈ 4 10-2 A/cm2
dvieq2 = 4kT ( ) df ~
gm W
For 10 x 0.5 mm
1/f noise IG ≈ 2 nA
KFF df
dvieqf2 = JG (A/cm2)
WL Cox2 f pMOST KFF ≈ 10-32 C2/cm2 L
≈ 4.5 105 exp( - )
nMOST x40 6.5
L in nm
Dynamic range decreases for smaller W and L ! Ref. Koh, Tr ED 2001, 259-
Annema, JSSC Jan.05, 135.
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 Table of contents Mismatch and dynamic range

1.  Nanometer CMOS

2.  Noise AVT 2
σ 2(ΔVT) ≈
WL
3.  Distortion
4.  Analog Signal Processing AVT ~ tox ~ L

5.  Efficient opamp design

AVT ≈ 10 mVµm
6.  Efficient Gm-C design in 0.5 µm CMOS
7.  Sub-1 Volt realizations σ (ΔVT) ≈ 3.2 mV
for W = 10 & L = 1 µm

Ref.: W. Sansen : Analog Design Essentials, Springer 2006

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Threshold voltage mismatch AVT Limits because of device mismatch

4
mVµm 40 AVT ~ tox NB 1 ΔIDS 4 AVT 2
≈ σ 2 ( ) ≈
20 (Accuracy)2 IDS WL (VGS - VT )2
10
2 IDS VDD
1 mVµm /nm tox Speed ≈ fT =
5 2π WL 2/3 Cox (VGS - VT )
? 2
2.5

1.2
Speed x (Accuracy)2 1 1
= ~
1.25 2.5 5 10 20 40 nm tox Power Cox AVT2 tox
0.06 0.13 0.18 0.25 0.35 0.5 0.7 1.2 2.4 µm L = Technological constant
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Limits because of device noise Noise versus mismatch for high DR

Vpp2/ 2 Vpp2/ 8
S/N = S/N = Mismatch
4kT R BW kT / C
Noise
Vpp2
Pmin = Pmin = VDD BW Vpp C
R

Ref. P.Kinget, ...

“Analog VLSI ..”
Pmin ≈ 8kT BW S/N page 67,
Kluwer 1997;
JSSC June 2005
1212-1224

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The zero HD3 point for smaller L Derivatives of gm : zero HD3 point

gm vs
gmsat = WCoxvsat
wi
W = 60 µm
g m’ VT VGS L = 0.6 µm
VDS = 2 V

gm’’ HD3 = 0 at VGS = VT ???

IDS’’’ = gm’’
VGS Ref. Fager JSSC Jan. 2004, 24-33

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Table of contents Applications and problems

1.  Nanometer CMOS

•  Applications
2.  Noise •  Anti-aliasing filters
3.  Distortion •  Video and HF filters : hard-disk drives
4.  Analog Signal Processing
•  Channel select filters in communication systems
•  Very-low-power filters
5.  Efficient opamp design •  Problems:
6.  Efficient Gm-C design •  Tuning for high precision: mismatch < 5 %
7.  Sub-1 Volt realizations •  Distortion : THD < -60 dB
•  Low power supply voltages : 1 Volt
Ref.: W. Sansen : Analog Design Essentials, Springer 2006
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Channel select filters Signal to Noise + Distortion ratio

dB RC (GBW) + Disto - Tuning
BW IIP3 Power 100

MOST-C (GBW) + Tuning - Disto

•  GSM 115 kHz 10 dBVp 3.5 mW 80
SC (settling) + Tuning - HiFr
•  Bluetooth 650 kHz 18 dBVp 10 mW + Power, Disto
•  CDMA2000 700 kHz 15 dBVp 7 mW gmC (linearity) gmC + Tuning - Disto
60
•  W-CDMA 2.2 MHz 0 dBVp 10 mW + HiFr
SI (mismatch)
•  IEEE 802.11 a 10 MHz 0 dBVp 10 mW +HiFr - DR
40
•  IEEE 802.11 g 10 MHz 0 dBVp 10 mW
•  IEEE 802.11 b 12 MHz 0 dBVp 10 mW
•  IEEE 802.11 n 20 MHz 0 dBVp 15 mW 20
10 k 100 k 1M 10 M 100 M 1 GHz f
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 Table of contents Telescopic CMOS OTA

1.  Nanometer CMOS M9

2.  Noise
+ - More gain
M1 M2
3.  Distortion At low frequencies
M5 M6
4.  Analog Signal Processing
vOUT
5.  Efficient opamp design
CL
6.  Efficient Gm-C design gm1
M7 M8
GBW =
7.  Sub-1 Volt realizations 2π CL
M3 M4
Ref.: W. Sansen : Analog Design Essentials, Springer 2006 Gulati, JSSC Dec.98, 2010-2019
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Miller CMOS OTA : GBW Miller CMOS OTA : poles and zero
Cc
M7 1 : B fd fz
M5
1pF
5 fnd
0.1pF
v- v 4 Pole splitting
+ Cc 10fF f
3 M2 1k 1M Hz
M1
|Av| Av0
RL CL 1000 is sufficient
Cc = 0
for Cc = 1pF
100
2 1 M6
gm1 10 Cc = 1pF
M3 M4 Cn1 GBW =
2π Cc BW
1
GBW
0.1 f
1k 1M
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Optimum design for high speed Miller OTA Maximum GBW versus channel length L

gm1 GBW
CL = α Cc α≈2 VGS-VT ≈ 0.2 V
GBW =
GHz
2π Cc vsat α  ≈ 2
Cc = β Cn1 = β CGS6 β≈3
gm6 1 10 β≈3
fnd = fnd = γ GBW γ≈2 γ  ≈ 2
2π CL 1 + Cn1/Cc or 16 x
CGS = kW k = 2 10 -11 F/cm µ
1
fT6
fnd gm6 1 fT6 fT6 GBW ≈
GBW = = = = 16
γ 2π CL γ (1 + 1/ β) αβ γ (1 + 1/ β) 16 0.1
10 nm 100 nm L 1 µm

CL = α Cc = α β Cn1 = α β CGS6 = α β kW6 W6 if CL

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Symmetrical CMOS OTA : GBW Folded cascode CMOS OTA :
VDD VDD
M9 M5 M6
M7 M9 M8
1:1 7 6
M1 M2
M7 M8
5 4 vOUT - 3 + vOUT
- 3 +
5
4

M1 M2 CL + CL
M3 M4
2 1
2 1
gm1 gm1
GBW =
M5 M3 M4 M6 GBW = B 2π CL
B:1 1:B 2π CL
VSS M10 M11

VSS
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Comparison amplifiers Table of contents

ITOT dvin,eq2 Speed Swing

1.  Nanometer CMOS
8/3 kT df fT
mA
gm1 2.  Noise

Telescopic casc. 0.25 4 8 small 3.  Distortion

Symmetrical (B= 3) 0.33 16 18 avg.

4.  Analog Signal Processing

Folded cascode 0.5 4 8 avg. 5.  Efficient opamp design

Miller 2-stage* 1.1 4 16 max. 6.  Efficient Gm-C design

GBW = 100 MHz CL = 2 pF VGS-VT = 0.2 V Fully differential 7.  Sub-1 Volt realizations
* CL/Cc= 2.5 Ref.: W. Sansen : Analog Design Essentials, Springer 2006
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Increasing the IP3 by Feedback Increasing the IP3 by Feedback

R2 I2 R2

2R
R1 R1

More FB with opamps

Ref. Lo, ESSCIRC 2007, pp. 210-213

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Parallel diff.pairs with different transistor sizes Linearized transconductors

iout -iout α  = IB2 / IB1 vout

v = VGST1 / VGST2 VDD
M1a M2a M1b M2b very linear !
vid/2 -vid/2 VGST = VGS-VT

n = α v2 Q
n:1 1:n

Ref. in CMOS : vin

IB1 IB2 Nedungadi, CAS
Oct 84, 891-894 0 VDD
VTn VTp
Voorman, JSSC CMFB
Aug.00, 1097-1108
Luh, ESSCIRC 00
MOST : n ≈ 5 Yodprasit, JSSC
July 03, 1189-1197 Ref. Voorman, JSSC, Aug.2000, 1097-1108

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Transconductors with linear MOSTs IM3 Intermodulation-free DR : IMFDR3

Vout (dB) 1 dB -1 dB
Compression
VDS1 = RDID ≈ 0.2 V point

IDS1 = β1VDS1 (VGS1-VT) ~Vin IM3 2/3

IP3
IMFDR3 =( )
gm1 = β1VDS1 is constant VNin
IMFDR3
~Vin3
over wide range ! IP3 is the IM3
Intercept point
Ref. Alini, JSSC, Dec.92, pp.1905-1915 VNout
Chamla JSSC, July 05, pp.1443-1450 Noise IP3
Pavan JSSC, April 00, pp.503-511
Vin (dB)
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FOM for continuous-time filters FOM versus Power per Pole

FOM = 160 FOM = 140
IMFDR3 BW TuR 140
FOM = 10 log ( )
PopP 130

120 FOM = 120

♦  IMFDR3 is a ratio (no units)
♦  BW is the -3 dB cut off frequency in Hz 110
♦  TuR is the Tuning Ratio BWmax/BWmin (no units)
100
♦  PopP is the Power consumption per Pole in Watts
90
0.1 1 10 100 1000 mW
Ex.: IMFDR3 = 500; BW = 20 MHz; TuR = 40; PopP = 4 mW
gives FOM = 140
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FOM versus Power per Pole Table of contents
FOM = 160 FOM = 140
140 1.  Nanometer CMOS
130 2.  Noise
120 FOM = 120 3.  Distortion
110 4.  Analog Signal Processing
100 5.  Efficient opamp design
90 6.  Efficient Gm-C design
0.1 1 10 100 1000 mW 7.  Sub-1 Volt realizations
Alini Bollati Chang Chamla Hollman
Ref.: W. Sansen : Analog Design Essentials, Springer 2006
Krummenacher Lo Pavan Yodprasit
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Sub-1 Volt switched OTA 1-Volt opamp with Bulk-driven MOSTs

VT ≈ 0.7 V (n-well CMOS)

Bulk input :
At 0.4 V only 0.1 pA

gmB CD
= n - 1 =
gm Cox

GBW = 0.6 MHz (15 pF)

1 V 80 µW (min: VT+2VDSsat) 1 V 45 µA
Fully differential 4 Switches 2n : In & Output range:
75 dB 30 MHz Only 2nd stage switched off ! 0.2 … 0.88 V

Baschirotto, .. JSSC Dec.97,pp.1979-1986 Allen, .. ISSCC Febr.95, 192-193

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Noise with the substrate as input 1-V opamp with current-driven Bulk bias

VT reduced
dvieq2 dvieqb2
from 0.6 V
gmb to 0.4 V
n-1 = by bulk-bias !
gm
≈ 0.3
VDD,SS = 1 V
2= 2/3 2=
2/3 gm
dvieq 4kT ( ) df dvieqb 4kT ( ) df
gm gmb2

Lehmann, .. JSSC July 2001, pp. 1082-1086

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0.5 Volt opamp with Gate drive and Bulk bias Class AB differential V-I converter
VDD = 0.9 V VT = 0.5 V
VT ≈ 0.5 V (n-well
VGS - VT = 0.2 V
0.18 µm CMOS) M3 M4
VGS = 0.7 V
≈ Vin2 0.5 V VDSsat = 0.2 V
Pseudo-differential
Vin1 Vin2
Cross-coupling M1 M2 iout M2 is source follower
for higher gain ! 0 V
VGS1 = Vin1 - Vin2
0.2 V
IB1 IB2 iout ~ (Vin1 - Vin2)2

>>> Class AB
GBW = 15 MHz (10 pF) 0.5 V 0.4 mA
Chatterjee, JSSC Peluso,…, JSSC Dec.98, pp.1887-1896
Dec.05, 2373-2387
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Class AB characteristic Table of contents

1.  Nanometer CMOS

2.  Noise
3.  Distortion
4.  Analog Signal Processing
5.  Efficient opamp design
6.  Efficient Gm-C design
7.  Sub-1 Volt realizations

Ref.: W. Sansen : Analog Design Essentials, Springer 2006

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