POWER PC
A Brief Overview of PowerPC
ARKADIP RAY
M.Tech IT - 11
Abstract— This study provides an overview of the PowerPC
microprocessor features including a block diagram showing
the major functional components. It also provides an overview
of the PowerPC architecture and working process.
I. INTRODUCTION
PowerPC (Performance Optimization With Enhanced RISC
– Performance Computing, sometimes abbreviated as PPC)
is a reduced instruction set computing (RISC) instruction set
architecture (ISA) created by the 1991 Apple–IBM–
Motorola alliance, known as AIM. PowerPC was the
cornerstone of AIM's PReP and Common Hardware
Reference Platform initiatives in the 1990s. Originally
intended for personal computers, the architecture is well
known for being used by Apple's Power Macintosh,
PowerBook, iMac, iBook, and Xserve lines from 1994 to
2006. It has since become niche in personal computers, but
remain popular as embedded and high-performance
processors. Its use in video game consoles and embedded
applications provided an array of uses.
II. BRIEF HISTORY
The history of RISC began with IBM's 801 research project,
where developed the concepts of RISC in 1975-78. 801-
based microprocessors were used in a number of IBM
embedded products, eventually becoming the 16-register
ROMP (Research Office Products Division Micro
Processor) processor used in the IBM RT. RT was a rapid
design implementing the RISC principles, and the
performance was disappointing in comparison to the high
performance 68000 microprocessor from Motorola.
Between the years of 1982-1984 IBM started a project to
build the fastest microprocessor on the market and
development was goes another 4-5 years. The result was the
POWER instruction set architecture, introduced with the
RISC System/6000 in early 1990. In 1991, the PowerPC
was just one facet of a larger alliance among these three
companies. At the time, most of the personal computer
industry was shipping systems based on the Intel 80386 and
80486 chips, which had a CISC architecture, and
development of the Pentium processor was well underway.
The PowerPC chip was one of several joint ventures
involving the three, in their efforts to counter the growing
Microsoft-Intel dominance of personal computing. By July
2010, the POWER architecture IBM developed is still very
much alive on their server offerings for large businesses and
continues to evolve (and current POWER processors
implement the full PowerPC instruction set architecture).
For example, IBM's servers based on POWER have the
highest revenue market share (53.9%) among UNIX servers.
The PowerPC specification is now handled by Power.org.
III. OVERVIEW
 The 601 is the first implementation of the PowerPC
family of reduced instruction set computer (RISC)
microprocessors.
 The 601 implements the 32-bit portion of the PowerPC
architecture, which provides 32- bit effective (logical)
addresses, integer data types of 8, 16, and 32 bits, and
floating-point data types of 32 and 64 bits.
 For 64-bit PowerPC implementations, the PowerPC
architecture provides 64-bit integer data types, 64-bit
addressing, and other features required to complete the
64-bit architecture.
 The 601 is a superscalar processor capable of issuing
and retiring three instructions per clock, one to each of
three execution units.
 The 601 integrates three execution units—an integer
unit (IU), a branch processing unit (BPU), and a
floating-point unit (FPU). The ability to execute three
instructions in parallel and the use of simple
instructions with rapid execution times yield high
efficiency and throughput for 601-based systems.
 The 601 includes an on-chip, 32-Kbyte, eight-way set-
associative, physically addressed, unified instruction
data cache and an on-chip memory management unit
(MMU).
 The 601 has a 64-bit data bus and a 32-bit address bus.
IV. FEATURES
Originally intended for personal computers, PowerPC CPUs
have since become popular with embedded and high-
performance processors as well. It is largely based and
compatible with POWER microprocessor. Design features
of PowerPC are as follows -
 High-performance, superscalar microprocessor
 As many as three instructions in execution per
clock (one to each of the three execution units)
 Single clock cycle execution for most instructions
 Pipelined FPU for all single-precision and most
double-precision operations
 Three independent execution units and two register files
 BPU featuring static branch prediction
 A 32-bit IU
 Fully IEEE 754-compliant FPU for both single-
and double-precision operations
 Thirty-two GPRs for integer operands
 Thirty-two FPRs for single- or double-precision
operands
 High instruction and data throughput
 Zero-cycle branch capability
 Programmable static branch prediction on
unresolved conditional branches
 Instruction unit capable of fetching eight
instructions per clock from the cache
 An eight-entry instruction queue that provides
look-ahead capability
 Interlocked pipelines with feed-forwarding that
control data dependencies in hardware
 Unified 32-Kbyte cache—eight-way set-
associative, physically addressed; LRU
replacement algorithm
 Cache write-back or write-through operation
programmable on a per page or per block basis
 Memory unit with a two-element read queue and a
three-element write queue
 Run-time reordering of loads and stores
 BPU that performs condition register (CR) look-
ahead operations
 Address translation facilities for 4-Kbyte page size,
variable block size, and 256-Mbyte segment size
 A 256-entry, two-way set-associative UTLB
 Four-entry BAT array providing 128-Kbyte to 8-
Mbyte blocks
 Four-entry, first-level ITLB
 Hardware table search (caused by UTLB misses)
through hashed page tables
 52-bit virtual address; 32-bit physical address
 Facilities for enhanced system performance
 Bus speed defined as selectable division of
operating frequency
 A 64-bit split-transaction external data bus with
burst transfers
 Support for address pipelining and limited out-of-
order bus transactions
 Snooped copyback queues for cache block (sector)
copyback operations
 Bus extensions for I/O controller interface
operations
 Multiprocessing support features that include the
following: Hardware enforced, four-state cache
coherency protocol (MESI)
 Separate port into cache tags for bus snooping
 In-system testability and debugging features through
boundary-scan capability
V. IMPLEMENTATION
The first implementation of the architecture was the Power-
PC 601, released in 1992, based on the RSC, implementing
a hybrid of the POWER1 and Power-PC instructions. This
allowed the chip to be used by IBM in their existing
POWER1-based platforms, although it also meant some
slight pain when switching to the 2nd generation "pure"
PowerPC designs. Apple continued work on a new line of
Macintosh computers based on the chip, and eventually
released them as the 601-based Power Macintosh on March
14, 1994.
The first 64-bit implementation was the PowerPC
620, but it appears to have seen little use because Apple
didn't want to buy it and because, with its large die area, it
was too costly for the embedded market. It was later and
slower than promised, and IBM used their own POWER3
design instead, offering no 64-bit "small" version until the
late-2002 introduction of the PowerPC 970.
The 970 is a 64-bit processor derived from the
POWER4 server processor. To create it, the POWER4 core
was modified to be backward-compatible with 32-bit
PowerPC processors, and a vector was added. IBM
developed a separate product line called the "4xx" line
focused on the embedded market. These designs included
the 401, 403, 405, 440, and 460. In 2004, IBM sold their
4xx product line to Applied Micro Circuits Corporation.
Honda also uses PowerPC processors for ASIMO.
There are many implementation of PPC concept
after 1991, some of those are:
 Gekko Microprocessor:
It is a 32-bit microprocessor custom made by IBM in 2000.
Gekko’s role in the gamming system was to facilitate game
scripting, artificial intelligence, physics and collision
detection, custom graphics lighting effects and geometry
such as smooth transformations, and moving graphics data  PowerPC e200 - 32 bit power architecture
through the system. The main features are: microprocessor - speed ranging up to 600 MHz - ideal
 Customized power Pc 750Cxe core. for embedded applications.
 Clock rate – 486MHz.  PowerPC e300 – similar to e200 with an increase in
 Integer unit 32-bit. speed upto 667 MHz.
 Floating point unit – 64-bit  PowerPC e600 – speed upto 2 Ghz – ideal for high
 SIMD instruction – PowerPC instructions + 50 performance routing and telecommunications
new SIMD instructions geared toward 3d graphics. applications.
 POWER5 – IBM – dual core μP
 Kilo core Microprocessor:
 POWER6 – IBM – Dual core μP - A notable difference
It is high performance, low power multi-core
from POWER5 is that the POWER6 executes
microprocessor that has 1025 core. It contains a single
instructions in-order instead of out-of-order
PowerPC processing core, and 1,024 eight-bit Processing
 PowerPC G3 - Apple Macintosh computers such as the
Elements running at 125 MHz each, which can be
PowerBook G3, the multicolored iMacs, iBooks and
dynamically reconfigured, connected by a shared
several desktops, including both the Beige and Blue and
interconnect. It allows high performance parallel processing.
White Power Macintosh G3s.
IBM says that the Kilocore1025 will enable "streaming live-
 PowerPC G4 - is a designation used by Apple
and high-definition video on a low-power, mobile device at
Computer to describe a fourth generation of 32-bit
five to 10 times the speed of existing processors.
PowerPC microprocessors.
 Power3, Power4, Power5 this all are invented by IBM.  PowerPC G5 - 64-bit Power Architecture processors
The differences on this are:  Xenon - based on IBM’s PowerPC ISA – XBOX 360
Frequency: (450MHz), (1.1GHz to 1.9GHz), (1.5GHz to game console.
2.3GHz).  Broadway – based on IBM’s PowerPC ISA – Nintendo
Produced: 1998, 2001, 2004. Wii gaming console
Min. feature size: (220nm to 180nm), (180nm to 130nm),  Blue Gene/L - dual core PowerPC 440, 700 MHz, 2004
(130nm to 90nm).  Blue Gene/P - quad core PowerPC 450, 850 MHz, 2007
Cores: 1, 2, 2.
VII. POWER PC ARCHITECTURE
 X704 Microprocessors:
It is a Microprocessor that implements the 32-bit version of
the PowerPC instruction set architecture (ISA) developed by
Exponential Technology. The microprocessor was notable
for its high clock frequency (for the time, circa 1997) in the
range of 400 to 533 MHz, its use of bipolar transistors for
logic and CMOS circuits for memory, and its failure to see
use in an Apple Macintosh, the opposite of what industry
observers.
From the beginning of the PowerPC to today’s
world, a huge change is observed. The frequency of
PowerPC is increased and cores are improved, also caches
of this type of microprocessors are changed hugely.

VI. POWER PC PROCESSOR

Many PowerPC designs are named and labelled by their
apparent technology generation. IBM and Motorola together
made G1, G2 and G3 series of processor. After that
Motorola made power-pc 7xx family and G4 series. IBM
produced separately POWER 3, 4, 5, 6, 6+, 7, 7+ series and
also RS64, G5 series. The POWER series are all 64-bit
processors. PowerPC Generations are as follows -
 VIII. OPERATING SYSTEMS
 Operating systems that work on the PowerPC architecture
are generally divided into those that are oriented toward
the general-purpose PowerPC systems, and those oriented
toward the embedded PowerPC systems.
e.g. - Apple’s Classic mac OS, IBM i5/OS, Linux
(Debian, Fedora, Mint, Red Hat Enterprise Edition,
Ubuntu, Solaris), Windows NT, CellOS for Playstation
 Companies that produces 32/64 bit PowerPC till date:
e.g. - Intel, Apple, Cisco Systems for Routers, Motorola,
Samsung, Xilinx, Microsoft, HCL, Sony, Toshiba
 Gaming Consoles:
e.g. - Bandai, Xbox, Nintendo, PlayStation
IX. PENTIUM VS. POWERPC
(1) Background: Pentium is a member of the series 8086.
It uses the same basic pattern as its predecessor. To keep
its compatibility with the existing software base, each
time it is improved, Intel’s engineers must retain its old
features. On the other hand, PowerPC uses the totally
new technology called RISC. In RISC, the number of
instructions, addressing modes, and format are reduced.
RISC technology was developed.
(2) Instruction Size: Pentium use varies instruction set
sizes. In the Pentium, instruction set format can be 1, 2,
or even 6 bytes. On the other hand, the PowerPC, like
other RISC processors uses 4 byte instruction sets. All
the instruction sets have the same length. If there are
instructions with size less than 4 bytes, then they are
filled in with zeros. This difference of instruction sizes
affects the pipelining process between the two
processors.
(3) Instruction Set: The PowerPC only has a few types of
instruction sets. If there are instructions which are not in
the PowerPC’s instruction set library, then the
programmer/compiler has to implement those instructions
by using available PowerPC instructions. That is one
reason why PowerPC programmers like to use high level
language rather than assembly language. Inversely,
Pentium uses many instruction sets. This allows the
programmers to implement their program using assembly
language. It also decreases the length of program in CISC
rather than in RISC.
(4) Number of Registers: One of the major characteristics
of RISC architecture is a large number of registers.
PowerPC microprocessors have 32 general purpose
registers, GPR0 – GPR31, each 32 bits wide. Of these 32
registers, only a few of them are assigned to a dedicated
function. For example, GPR0 is automatically assigned
the value zero and no other value can be written to it. One
advantage of a large number of registers is that it avoids the
use of the stack to store parameters. Although a stack can be
implemented on a Power PC processor, it is not as necessary
as in a Pentium processor since there are so many registers
available. It must be noted that PowerPC processors have
another 32 registers for floating-point operations, besides
the 32 general-purpose registers. The floating-point register
can be configured as 64-bit in order to handle double-
precision operands.
(5) Floating Point: The similarities of Pentium and PowerPC
in floating point are both of them complying with IEEE-754
standard single-and-double precision floating point
arithmetic and having regular multiply and divide
instructions that operate entirely on registers. The main
differences are in the floating-point instructions. Both 32
single and 32 double precision floating-point registers are
offered in the Power PC.
CONCLUSION
As we have seen, Reduced Instruction Set Computing
(RISC) is an evolution in computer architectures that
emphasizes speed and cost-effectiveness over ease of
assembly-language programming and the conservation of
memory. In addition, RISC-based designs will continue to
grow in speed and ability much more rapidly than
comparable CISC designs over the next several years. These
factors make RISC an irresistible choice for the future of the
Macintosh product line. Yet, since Apple's customers have a
sizable investment in hardware and software, compatibility
is a key word among Apple's PowerPC engineers. This
compatibility is being maintained through software
emulation, significant amounts of compatibility testing, and
making sure that existing NuBus cards can work in the first
PowerPC machines.
ACKNOWLEDGEMENT
I hereby like this opportunity to express my gratitude
towards Ms. Paromita Dey, Professor of Dept. of
Information Technology, GOVERNMENT COLLEGE OF
ENGINEERING AND CERAMIC TECHNOLOGY, for
providing me the facility to undergo the presentation in the
organization. I also like to thank all the faculty members and
staff of the department of the INFORMATION
TECHNOLOGY. At the end, I am indebted to all, who have
directly helped, inspired and guided me in the completion of
the presentation.
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