Sie sind auf Seite 1von 446

UltraScale Architecture GTY Transceivers

User Guide

UG578 (v1.3) September 20, 2017

UltraScale Architecture GTY Transceivers User Guide UG578 (v1.3) September 20, 2017
Revision History The following table shows the revision history for this document. Date Version Revision

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

09/20/2017

1.3

Chapter 1: Added NE PMA loopback path to Figure 1-2.

Chapter 2: Updated Functional Description, page 29 with new limitations on GTY transceivers in UltraScale+ FPGAs. Added important note to Multiple External Reference Clocks Use Model and Functional Description. Updated SDM0DATA[24:0]/SDM1DATA[24:0] description in Table 2-14. Added PPF0_CFG/PPF1_CFG to Table 2-15. In Dynamic Frac-N for UltraScale+ FPGAs Only, replaced CLK with Clock. Updated descriptions of GTRESETSEL and GTTXRESETSEL in Table 2-21. Updated description of GTPOWERGOOD in Table 2-25 and Table 2-29. Updated direction and description of RXCKCALDONE in Table 2-29. Updated conditions in GTY Transceiver TX Reset in Response to Completion of Configuration and GTY Transceiver RX Reset in Response to Completion of Configuration.

Chapter 3: Added NE PMA loopback path to Figure 3-1. Removed S_TXSYNCDONE from Figure 3-26. Added bullet about incoming RX data stream to TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Multi-Lane Auto Mode. Added note 7 after Figure 3-30. In Table 3-35, updated description of TXDIFFCTRL[4:0] and TXMAINCURSOR[6:0], and added TXDIFFCTRL[4:0] for UltraScale+ FPGAS only. Added TXSWBST_EN, TXSWBST_BST, TXSWBST_MAG, TXFE_CFG0, TXFE_CFG1, TXFE_CFG2, and TXFE_CFG3 to Table 3-36.

Chapter 4: Added NE PMA loopback path to Figure 4-1. Added OOB and Electrical Idle Use Modes. Updated Reset and CDR Configuration for SATA. Added note 7 after Table 4-13. Updated RX_PROGDIV_CFG description in Table 4-15. Updated RXPRBSERR description in Table 4-24. Updated RX_PRBS_ERR_CNT description in Table 4-26. Removed state D from Figure 4-31. In Table 4-30, changed direction of RXCTRL0[15:0] from In to Out.

Chapter 5: Updated first paragraph in Termination Resistor Calibration Circuit. Specified PSG side in Analog Power Supply Pins. Added note 2 after Figure 5-8. Updated MGTAVTTRCAL and MGTRREF recommendations in Table 5-5.

Chapter 6: Updated PCIE_PLL_SEL_MODE_GEN4 description in Table 6-2.

Appendix B: In Table B-2, added DRP address 000Bh, and updated DRP addresses 003Eh, 0063h, and 00C6h.

Appendix C: In Table C-2, added DRP addresses 0003h, 000Ah, 000Bh, and 0059h, and updated 0250h.

UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017

0059h , and updated 0250h . UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017 www.xilinx.com

2

Date Version Revision 12/21/2016 1.2 Chapter 1 : Updated first sentence in GTYE3/4_COMMON Attributes and

Date

Version

Revision

12/21/2016

1.2

Chapter 1: Updated first sentence in GTYE3/4_COMMON Attributes and GTYE3/4_CHANNEL Attributes. Added SIM_DEVICE to Table 1-2 and Table 1-3. Updated second paragraph in Functional Description, page 29. Added paragraph to the end of Multiple External Reference Clocks Use Model.

Chapter 2: Updated description of MGTAVCC in Input Mode, page 23 and Figure 2-1. Updated GTREFCLK11 connection in Figure 2-8. Replaced Quad PLL1 with MGTREFCLK1 and Quad PLL0 with MGTREFCLK0 in description of GTNORTHREFCLK00/01/10/11 and GTSOUTHREFCLK00/01/10/11 in Table 2-8. Updated CPLLLOCKEN description in Table 2-10. In Functional Description, page 48, updated line rate from 16.375 Gb/s to 28.1 Gb/s. Added VCO to title of Table 2-12. Removed SDM0DATA1_0/SDM1DATA1_0 and SDM0DATA1_1/SDM1DATA1_1 from Table 2-15. Updated Dynamic Frac-N for UltraScale FPGAs Only title. In paragraph after Figure 2-14, updated width of SDM[0/1]DATA to 25 bits. Added row to Table 2-17. Added Dynamic Frac-N for UltraScale+ FPGAs Only. Updated third instruction for reset mode being defaulted to single mode in GTY Transceiver TX Reset in Response to Completion of Configuration. Removed “after entering or exiting near-end PMA loopback” row from Table 2-28 and added it to Table 2-33. Added paragraph about power savings after Table 2-37. Updated near-end and far-end PMA loopback bullets after Figure 2-28. Updated DRPADDR width from 16 to 10 bits in Table 2-40 and Table 2-41. In Table 2-42, updated DMONITOROUT descriptions and added DMONITOROUTCLK. Added Capturing the Digital Monitor Output through IBERT.

Chapter 3: Updated paragraph after Table 3-1. Added TX Asynchronous Gearbox Bit and Byte Ordering. Updated TXSYNCMODE description in Table 3-20. Added note to Table 3-22. Added TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Multi-Lane Auto Mode. Updated TXPRBSFORCEERR description in Table 3-25. In Table 3-33, changed TXPIPPMEN clock domain from async to TXUSRCLK2 and updated TXPIPPMSEL description. In Table 3-35, changed TXBUFDIFFCTRL[2:0] default value from 3’b100 to 3’b000. Updated TXPD[1:0] clock domain in Table 3-37 and Table 3-39.

Chapter 4: In Table 4-6, added sentence about maximum supported line rate to RXELECIDLE description, and added RXCDRHOLD and RXCDROVRDEN. Added Reset and CDR Configuration for SATA. In Table 4-18, updated maximum ES_PRESCALE for bus widths 80, 128, and 160 at BER floor of 10 6 . Updated ES_HORZ_OFFSET description in Table 4-20. Added TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Multi-Lane Auto Mode. Added note to Table 4-34.

Chapter 5: Added nominal voltages to MGTAVCC description in Table 5-1. Updated MGTAVCC for UltraScale and UltraScale+ FPGAs in Figure 5-1. Added rules for powering PSGs to Analog Power Supply Pins. Updated paragraphs before Figure 5-3 and Figure 5-4. Updated Figure 5-6 for UltraScale and UltraScale+ FPGAs. In Overview, page 332, updated MGTAVCC for UltraScale and UltraScale+ FPGAs. In Table 5-5, updated recommendations for MGTREFCLK0P/N and MGTREFCLK1P/N, and nominal voltages for MGTAVCC[N].

Chapter 6: Added RXSTATUS[2:0] to Table 6-1.

Appendix B: In Table B-1, added DRP address 0099h, and removed 00A8h and 00A9h. Updated DRP addresses in Table B-2.

12/21/2016

1.2

Appendix C: In Table C-1, updated DRP address 001Eh, added 001Fh, 002Dh, 008Fh, 0099h, 009Fh, and 025Fh, and removed 00A8h and 00A9h. In Table C-2, updated DRP addresses 0011h, 008Fh, and 00Fbh, and added 0009h, 006Fh, 0090h, 0263h, and 0269h.

(Cont’d)

UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017

, and 0269h . (Cont’d) UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017 www.xilinx.com 3

3

Date Version Revision 11/24/2015 1.1 Removed “Advance Specification” from document title. Added

Date

Version

Revision

11/24/2015

1.1

Removed “Advance Specification” from document title. Added UltraScale+ FPGAs throughout.

Chapter 1: Updated Introduction to UltraScale Architecture. Updated line rates in Features, Table 1-1, and Key Differences from Previous FPGA Generations. Updated to 15-tap DFE in Table 1-1. Added GTYE4_CHANNEL, GTYE4_COMMON, IBUFDS_GTE4, and OBUFDS_GTE4 primitives to Figure 1-1 and Figure 1-3. Updated pattern generator connection in Figure 1-2. Added Ports and Attributes.

Chapter 2: Added IBUFDS_GTE4, OBUFDS_GTE4, and OBUFDS_GTE4_ADV primitives throughout. Added Output Mode heading. Updated OBUFDS_GTE3/4 and OBUFDS_GTE3/4_ADV headings. Updated second paragraph in Functional Description, page 29. Updated paragraphs before Figure 2-4 and Figure 2-5. Added Single External Reference Clock Use Model and Multiple External Reference Clocks Use Model. Updated CPLLREFCLKSEL[2:0] description in Table 2-7. Updated description of QPLL0REFCLKSEL[2:0] and QPLL1REFCLKSEL[2:0] in Table 2-8. Removed Table 2-8: GTYE3_CHANNEL Clocking Attribute and Table 2-10: GTYE3_COMMON Clocking Attributes. Updated description of CPLLRESET and added note to Table 2-10. In Table 2-11, removed SIM_CPLLREFCLK_SEL, updated CPLL_CFG3 type, and designated CPLL_INIT_CFG1 as being applicable to UltraScale FPGAs only. Updated Equation 2-3 and Equation 2-5. Removed SIM_QPLL0REFCLK_SEL/SIM_QPLL1REFCLK_SEL from Table 2-15. Added Resetting Multiple Lanes and Quads. Replaced CPLLRESET with CPLLPD in CPLL Reset and Figure 2-10. Updated second and third paragraphs in Functional Description, page 48. Updated VCO block in Figure 2-13. Updated Equation 2-3. In Table 2-13, updated valid settings for N, and added RATE, SDMDATA, and SDMWIDTH factors. Added QPLL0FBDIV[7:0]/QPLL1FBDIV[7:0], SDM0TOGGLE/SDM1TOGGLE, SDM0FINALOUT[3:0]/SDM1FINALOUT[3:0], and SDM0TESTDATA[14:0]/SDM1TESTDATA[14:0] to Table 2-14. In Table 2-15, updated BIAS_CFG_RSVD type, added QPLL[0/1]CLKOUT_RATE, QPLL0CLKOUT_RATEPPF0_CFG, QPLL[0/1]CLKOUT_RATE, QPLL[0/1]_PCI_EN, and QPLL0_RATE_SW_USE_DRP, updated valid divider settings for QPLL[0/1]_FBDIV, and designated SDM[0/1]DATA1_0, SDM[0/1]DATA1_1, SDM[0/1]_DATA_PIN_SEL and SDM[0/1]_WIDTH_PIN_SEL as being applicable to UltraScale FPGAs only. Added Use Modes, page 55. In Table 2-21, designated GTRESETSEL as being applicable to UltraScale FPGAs only, and added GTTXRESETSEL and GTRXRESETSEL. In Table 2-22, updated description of CPLLRESET, and added CPLLPD and table note. Removed Table 2-19: CPLL Reset Attributes. Added TXDCCDONE, TXDCCFORCESTART, and TXDCCRESET to Table 2-25. Added TX_DCC_LOOP_RST_CFG to Table 2-26. Updated Figure 2-21. Added RXRATEMODE setting to second paragraph in RX Rate Change. In Table 2-28, updated Components to be Reset and Recommended Reset columns and added two new situations. Added RXCKCALDONE, RXCKCALRESET, and RXCKCALSTART[6:0] to Table 2-29. Added CKCAL1_CFG_0/1/2/3, CKCAL2_CFG_0/1/2/3/4, RXCKCAL1_[IQ/I/Q]_LOOP_RST_CFG, RXCKCAL2_[DX/D/S/X]_LOOP_RST_CFG, and SRSTMODE to Table 2-30. Updated Figure 2-26. Updated Components to be Reset and Recommended Reset columns in Table 2-33. Updated first paragraph in RX Rate Change.

UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017

paragraph in RX Rate Change . UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017 www.xilinx.com

4

Date Version Revision 11/24/2015 1.1 Added Powering Up/Down Multiple Lanes and Quads . Added

Date

Version

Revision

11/24/2015

1.1

Added Powering Up/Down Multiple Lanes and Quads. Added recommendation

(Cont’d)

for CPLL power down to PLL Power Down. In Functional Description, page 86, replaced RXREC with RXDES in near-end PCS loopback bullet, updated description under near-end PMA loopback bullet, and added sentence about TX phase interpolator PPM controller to far-end PMA loopback bullet. Added Table 2-39. In Table 2-40, updated descriptions of DRPEN and DRPRDY, and added DRPADDR[15:0], PCSRSVDIN[2], and DRPRST. Added DRPADDR[15:0], and updated descriptions of DRPEN and DRPRDY in Table 2-41. Added Digital Monitor.

Chapter 3: Updated pattern generator connection in Figure 3-1, Figure 3-14, and Figure 3-17. In Table 3-4, changed clock domain for TXDATAEXTENDRSVD from TXUSRCLK2 to Async. Added BUFG_GT_SYNC to note 1 after Figure 3-2 and Figure 3-3, and to note 2 after Figure 3-4 and Figure 3-5. Added description of middle GTY transceiver selection before Figure 3-3. Updated descriptions of TXCTRL1[15:0] and TXCTRL0[15:0] in Table 3-7. In Using the TX Synchronous Gearbox, updated GEARBOX_MODE[0] setting and removed sentence about data pause. Updated Figure 3-9 and Figure 3-10. Added sentence about TXHEADER[5:3] and TXDATA[127:64] to step 3, page 124. Removed 4-byte gearboxes from CAUI Interface and Figure 3-11. Updated GEARBOX_MODE[0] setting in Enabling the TX Asynchronous Gearbox. Added Reading Datapath Latency. Added TXUSRCLK jitter sensitivity to Table 3-17. Added TX_FIFO_BYP_EN to Table 3-19. Updated Functional Description, page 137. Added Figure 3-18. In Table 3-20, replaced TXUSRCLK with TXOUTCLK in description of TXPHDLYRESET, updated descriptions of TXDLYSRESET, TXPHDLYTSTCLK, TXDLYHOLD, TXDLYUPDOWN, TXPHALIGNDONE, TXSYNCMODE, TXSYNCALLIN, TXSYNCIN, TXSYNCOUT, and TXSYNCDONE and changed clock domains for TXDLYHOLD and TXDLYUPDOWN to Async. In Table 3-21, added TX_FIFO_BYP_EN and updated descriptions of TX_XCLK_SEL, TXSYNC_MULTILANE, TXSYNC_SKIP_DA, and TXSYNC_OVRD. In Using TX Buffer Bypass in Multi-Lane Manual Mode, removed redundant sentence from first paragraph and updated master bullet. Expanded list of square wave test patterns in paragraph after Table 3-23 and Figure 3-28. In Table 3-25, updated internal data widths and square wave periods in TXPRBSSEL[3:0] description. Added Using TX Pattern Generator. Added BUFG_GT_SYNC to note 6 after Figure 3-30. Updated supported divider values and 10 bullet in TX Programmable Divider. In Table 3-30, updated description of TX_PROGDIV_CFG and added TX_PROGDIV_RATE. Updated TXRATEMODE description in Table 3-31. Updated TX_PROGCLK_SEL description in Table 3-32. Updated Functional Description, page 164. Added description of internal 25 MHz clock before Table 3-32. In Table 3-33, changed clock domain for TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMSEL, and TXPIPPMSTEPSIZE[4:0] to Async and updated description for TXPIPPMOVRDEN and TXPIPPMSEL. In Table 3-34, updated TXPI_CFG0/1 types for UltraScale+ FPGAs, added TXPI_PPM, and designated TXPI_CFG2/3/4/5 and TXPI_PPMCLK_SEL as being applicable to UltraScale FPGAs only. Added example Verilog code after Table 3-34. In Table 3-35, changed clock domain for TXBUFDIFFCTRL[2:0], TXDEEMPH, and TXDIFFCTRL[4:0] to Async, added TXDEEMPH[1:0], updated TXDIFFCTRL[4:0] description, designated TXBUFDIFFCTRL[2:0], TXDEEMPH, and TXDIFFPD as being applicable to UltraScale FPGAs only, and removed TXPOSTCURSORINV, TXPRECURSORINV, TXQPIBIASEN, TXQPISENN, TXQPISENP, TXQPISTRONGPDOWN, and TXQPIWEAKPUP. In Table 3-36, added TX_DEEMPH2[5:0] and TX_DEEMPH3[5:0], updated TX_EIDLE_ASSERT_DELAY description, removed TX_QPI_STATUS_EN, and designated TXDRVBIAS_P, TXDRVBIAS_N, TX_DCD_CFG, and TX_DCD_EN as being applicable to UltraScale FPGAs only.

UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017

to UltraScale FPGAs only. UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017 www.xilinx.com 5

5

Date Version Revision 11/24/2015 1.1 Changed TXPDELECIDLEMODE clock domain to Async in Table 3-39 .

Date

Version

Revision

11/24/2015

1.1

Changed TXPDELECIDLEMODE clock domain to Async in Table 3-39. Updated SATA_BURST_SEQ_LEN[3:0] description in Table 3-40.

(Cont’d)

Chapter 4: Removed GND connection from RX_CM_SEL[1:0] in Figure 4-2. Added RXTERMINATION, and removed RXQPISENN, RXQPISENP, and RXQPIEN from Table 4-1. Updated descriptions of RX_CM_SEL[1:0] and RX_CM_TRIM[3:0] in Table 4-2. Updated usage notes in Table 4-4 and Table 4-5. Removed Table 4-5: Use Mode 3—RX Termination and Figure 4-5: Use Mode 3. Added note to Table 4-5. Updated TXSYSCLKSEL description in Table 4-6. In Table 4-7, designated SAS_MIN_COM, SAS_MIN_INIT, SAS_MIN_WAKE, SAS_MIN_BURST, SAS_MAX_BURST, SAS_MAX_COM, SAS_MAX_INIT, and SAS_MAX_WAKE attributes as being applicable to UltraScale FPGAs only. Reversed order of KH and KL in Figure 4-12. Updated Figure 4-13. In Table 4-9, changed clock domain for all ports to Async, removed RXDFEXYDEN, added RXMONITOROUT[7:0], RXAFECFOKEN, FREQOS, RXDFECFOKFCNUM[3:0], RXDFECFOKFEN, RXDFECFOKFPULSE, {RXDFECFOKHOLD, RXDFECFOKOVREN}, and {RXDFEKHHOLD, RXDFEKHOVRDEN}, and updated descriptions throughout. In Table 4-10, added sentence saying that attribute is shared between DFE and LPM modes to descriptions for RX_DFE_KL_LPM_KH_CFG1[2:0], RX_DFE_KL_LPM_KL_CFG1[2:0], and RX_DFE_AGC_CFG1[2:0], added attributes ADAPT_CFG2, CTLE3_OCAP_EXT_CTRL, CTLE3_OCAP_EXT_EN, RXDFE_KH_CFG0/1/2/3, RXDFE_UT_CFG2, and RX_EN_CTLE_RCAL_B, and designated RX_CTLE3_LPF, RX_EN_HI_LR, RX_SUM_RES_CTRL, RX_DFE_AGC_CFG0[1:0], DFE_D_X_REL_POS, and DFE_VCM_COMP_EN as being applicable to UltraScale FPGAs only. Updated GTY Use Modes and GTY Transceivers: Switching Between LPM and DFE Modes at Run Time. In Table 4-11, designated RXCDRRESETRSV as being applicable to UltraScale FPGAs only and added INCPCTRL, CDRSTEPSX, CDRSTEPSQ, and CDRSTEPDIR. In Table 4-12, added RXCDR_CFG2_GEN2, RXCDR_CFG3_GEN2, RXCDR_CFG2_GEN4, RXCDR_CFG3_GEN4, RXCDR_LOCK_CFG3, RXCDR_LOCK_CFG4, RX_WIDEMODE_CDR_GEN3, RX_WIDEMODE_CDR_GEN4, RX_XMODE_SEL, and SAMPLE_CLK_PHASE, and designated RXPI_CFG2/3/4/5/6 as being applicable to UltraScale FPGAs only. Added RX CDR Lock to Reference. Added BUFG_GT_SYNC to note 6 after Figure 4-16. Updated type and valid settings for RX_PROGDIV_CFG in Table 4-15. Updated RXRATEMODE description in Table 4-16. Added description of internal 25 MHz clock before Table 4-17. Updated Eye Scan Theory. In Eye Scan Architecture, expanded description after Figure 4-19, and added Equation 4-2, Equation 4-3, and Table 4-18. Replaced COE status register with DRP read-only register in paragraph before Table 4-19. In Table 4-19, changed EYESCANTRIGGER domain from RXUSRCLK2 to Async and designated EYESCANMODE as being applicable to UltraScale FPGAs only. In Table 4-20, updated maximum prescale value for ES_PRESCALE and descriptions of ES_QUALIFIER, ES_SDATA_MASK, ES_ERRDET_EN, USE_PCS_CLK_PHASE_SEL, ES_CLK_PHASE_SEL, and RX_EYESCAN_VS_RANGE, added ISCAN_CK_PH_SEL2, and changed ES_EYE_SCAN_EN and ES_ERRDET_EN type from 1-bit binary to boolean. Split off lowercase attributes from Table 4-20 into new Table 4-21. Split off RX_PRBS_ERR_CNT attribute from Table 4-25 into new Table 4-26. Reversed direction of serial data stream in Figure 4-22. Updated Figure 4-23 title. Replaced “closest boundary” with “symbol boundary” in Activating Comma Alignment and Alignment Status Signals. Updated first paragraph in Manual Alignment. Extended RXSLIDE pulse width to cover two RXUSRCLK2 cycles in Figure 4-28 and Figure 4-29. Updated paragraph before Figure 4-29. In Table 4-28, updated description of RXSLIDE_MODE and split off COMMA_ALIGN_LATENCY into new Table 4-29. In 8B/10B Bit and Byte Ordering, replaced RXDISPERR and RXCHARISK with RXCTRL1 and RXCTRL0, respectively.

UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017

and RXCTRL0, respectively. UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017 www.xilinx.com 6

6

Date Version Revision 11/24/2015 1.1 Updated RX_DATA_WIDTH settings in Enabling and Disabling 8B/10B

Date

Version

Revision

11/24/2015

1.1

Updated RX_DATA_WIDTH settings in Enabling and Disabling 8B/10B Decoding. Updated Figure 4-32 and paragraph before it. In Table 4-32, updated descriptions of RXPHDLYPD, RXPHOVRDEN, and RXDLYEN, and removed RXDDIEN, RXPHMONITOR, and RXPHSLIPMONITOR ports. In Table 4-33, added RXPHBEACON_CFG, RXPHSAMP_CFG, and RXPHSLIP_CFG, removed RXPH_CFG and RXDLY_TAP_CFG, and updated descriptions of RX_XCLK_SEL, RXPHDLY_CFG, and RX_DDI_SEL. Updated master bullet in Using RX Buffer Bypass in Multi-Lane Manual Mode. Removed M_RXDDIEN and S_RXDDIEN from Figure 4-36. In Table 4-35, updated initialization for RX elastic buffer and added row for RXUSRCLK jitter sensitivity. Updated descriptions of RX_XCLK_SEL, RX_DEFER_RESET_BUF_EN, RXBUF_RESET_ON_CB_CHANGE, RXBUF_RESET_ON_COMMAALIGN, and RXBUF_RESET_ON_EIDLE in Table 4-37. Updated RX8B10BEN description in Table 4-39. In Table 4-40, removed duplicate RX_INT_DATAWIDTH, updated RX_DATAWIDTH description, and added PCIE3_CLK_COR_EMPTY_THRSH, PCIE3_CLK_COR_FULL_THRSH, PCIE3_CLK_COR_MAX_LAT, PCIE3_CLK_COR_MIN_LAT, and PCIE3_CLK_COR_THRSH_TIMER. Updated third and fourth paragraphs in Setting Clock Correction Sequences. Updated first paragraph in RX Channel Bonding. Updated RXCHANISALIGNED description in Table 4-42. In Table 4-43, removed PCS_PCIE_EN and updated descriptions of CHAN_BOND_MAX_SKEW, CHAN_BOND_KEEP_ALIGN, CHAN_BOND_SEQ_1_1/2/3/4, CHAN_BOND_SEQ_1_ENABLE, CHAN_BOND_SEQ_2_1/2/3/4, CHAN_BOND_SEQ_2_ENABLE, FTS_DESKEW_SEQ_ENABLE, and FTS_LANE_DESKEW_CFG. Updated RXDATAVALID, RXHEADER, and RXHEADERVALID descriptions in Table 4-44. Updated paragraph before Figure 4-48. Updated Figure 4-49 and title. Updated descriptions of RXGEARBOXSLIP, RXHEADER[5:0], and RXHEADERVALID[1:0] in Table 4-47. Corrected Table 4-47 title. Updated Enabling the RX Asynchronous Gearbox. Added RXHEADER[1:0] to Figure 4-60. Added Reading Datapath Latency.

Chapter 5: Updated direction and description columns for MGTREFCLK0P/N and MGTREFCLK1P/N in Table 5-1. Updated first paragraph in Termination Resistor Calibration Circuit. Added Table 5-2 and Table 5-3 to Analog Power Supply Pins. Added Reference Clock Output Buffer and Power Up/Down and Reset on Multiple Lanes. Updated capacitor tolerance to ±10% in Table 5-4 and Table 5-5. Updated recommendations for MGTREFCLK0P/N, MGTREFCLK1P/N, and MGTHRXP/N[3:0] in Table 5-5.

(Cont’d)

Chapter 6: Added new chapter.

Appendix B: Added DRP address 0019h to Table B-1. In Table B-2, added DRP addresses 0035h, 0036h, 008Ch (RX_DFE_KL_LPM_KL_CFG0 and RX_DFE_KL_LPM_KL_CFG1), 0099h (GEARBOX_MODE and TXPI_VREFSEL), 009Ah, 009Bh (RX_DFELPM_CFG0), 009Ch (RXPI_CFG5), 00ACh (RX_CLK_SLIP_OVRD), 00BAh (DDI_CTRL), 00BBh (TXGBOX_FIFO_INIT_RD_ADDR, TX_SAMPLE_PERIOD, RXGBOX_FIFO_INIT_RD_ADDR, and RX_SAMPLE_PERIOD), 00CDh (RX_DDI_SEL), 00E0h (CTLE3_OCAP_EXT_CTRL), 00FAh (RX_VREG_CTRL and RX_VREG_PDB), 0103h (RX_PROGDIV_RATE), 0105h (TX_PROGDIV_RATE), 007Fh through 0083h, 0150h through 015Fh, and 00D5h through 00D9h, and updated 0028h, 002Ah, 003Eh, and 00C6h.

Appendix C: Added new appendix.

Appendix D: Updated References.

06/23/2014

1.0

Initial Xilinx release.

UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017

1.0 Initial Xilinx release. UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017 www.xilinx.com 7

7

Table of Contents Revision History . . . . . . . . . .

Table of Contents

Revision History

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

Chapter 1: Transceiver and Tool Overview

 

Introduction to UltraScale Architecture

. UltraScale FPGAs Transceivers Wizard

Features

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

Simulation

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

Implementation

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

Chapter 2: Shared Features

Reference Clock Input/Output Structure

 

Reference Clock Selection and Distribution

 

Channel PLL

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

. Reset and Initialization

Quad PLL.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

Power Loopback.

Dynamic Reconfiguration Port

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

Digital

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

Chapter 3: Transmitter

TX Overview .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

. TX 8B/10B Encoder

TX Interface

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

TX Synchronous

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

TX Asynchronous Gearbox

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

. TX Buffer Bypass TX Pattern TX Polarity TX Fabric Clock Output TX Phase Interpolator PPM Controller

TX Buffer.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

TX Configurable

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

UltraScale Architecture GTY Transceivers UG578 (v1.3) September 20, 2017

Transceivers UG578 (v1.3) September 20, 2017 www.xilinx.com . . . . . . . . .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2

11

12

18

18

20

23

29

43

48

59

83

86

88

92

101

102

112

116

128

134

137

153

156

157

164

167

8

TX Receiver Detect Support for PCI Expre ss TX Out-of-Band   . . . .

TX Receiver Detect Support for PCI Express TX Out-of-Band

 

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

Chapter 4: Receiver

RX Overview RX Analog Front End

. RX Out-of-Band Signaling

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

RX Equalizer (DFE and LPM)

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

</