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.: FLIP FLOP D:
In this circuit there is no possibility that the two inputs are at high level, since it has an
inverter between them, so that R = ~ S, observe the following graph, here the input is
assumed Data at level 0 ...
Let's see what happens when the input Data, passes to 1 and CK changes state also
passing to 1, according to how the data is transmitted through the gates results Q = 1
and ~ Q = 0.
In order for the flip-flop to return to its initial state, the Data D input must pass to 0 and
will only be transferred to the output if Ck is 1 . Again the case is repeated that to read
the data must be ck = 1.
It is an arrangement of two independent FFs. The first acts as Master and the other as
Slave. With the difference that in this case the inputs Set and Reset are fed back by the
outputs Q and ~ Q respectively, leaving only the CK input free.
I know, it will be difficult to analyze, but we will make it easy, let's see ...
Now, when CK returns to its initial state (CK = 0) the Slave will switch the outputs Q
and ~ Q leaving Q = 1 and ~ Q = 0. When changing status CK (CK = 1) the outputs
will not be affected. This can be summarized in a small truth table, like this one ...
This type of flip-flop has been given the possibility to preset the status of its outputs,
adding two more entries, Preset ( Pr ) and Clear ( Clr ) , which would be something
like Set and Reset respectively, but of course, we must warn that the situation must be
avoided Pr = Clr = 0 It