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UNIT-1 MATERIAL

CMOS VLSI DESIGN


Course code: 12-EC206
II B.Tech. (ECE) II Semester

Prepared by
Dr. Fazal Noorbasha
M.Tech., Ph.D., MISTE, MIAENG, SMIACSIT
Associate Professor
VLSI Systems Research Group (VSRG) Head
Department of ECE – KL University
E-Mail Id: fazalnoorbasha@kluniversity.in

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING


KL UNIVERSITY
VADDESWARAM, GUNTUR – 522 502 (A.P.) INDIA

2013-14

This is only for reference purpose.


Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 2
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 3
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 4
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 5
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 6
1.6.1 nMOSFET:
Enhancement type nMOSFET:

Fig. 1.10 The physical structure of n-channel enhancement-type MOSFET.

Fig. 1.11 Output and Transfer Characteristics of n-channel enhancement-type MOSFET.


Points to remember:
1. It is a enhancement type nMOSFET
2. Substrate (B) is p-type
3. Source (S) and Drain (D) diffusions are n+ type
4. There is no channel between source and drain when No Gate voltage i.e. Vg=0V
5. It conducts for positive gate voltages only.
6. Linear current will increase by increasing the positive gate voltage.
7. After positive gate threshold voltage (VT,n), the conduction will start.

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 7
Definition of Output characteristics: It is a set of drain characteristic curves also called volt-
amper characteristics. The plots are Variation of Drain current (Id) with the drain-to-source
voltage (Vds) for a fixed value of gate-to-source voltage (Vgs). The conduction starts after
threshold voltage VT,n.
Definition of Transfer Characteristics: It gives the variation of the drain current (Id) with the
gate-to-source voltage (Vgs) for a fixed value of drain-to-source voltage (Vds).

Depletion type nMOSFET:

Fig. 1.12 The physical structure of n-channel depletion-type MOSFET.

Fig. 1.13 Output and Transfer Characteristics of n-channel depletion-type MOSFET.

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 8
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 9
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 10
Fig. 1.17 Output and Transfer Characteristics of p-channel depletion-type MOSFET.
Points to remember:
1. It is a depletion type pMOSFET
2. Substrate (B) is n-type
3. Source (S) and Drain (D) diffusions are p+ type
4. There is a channel between source and drain when NO Gate voltage i.e. Vg=0V
5. It conducts for negative as well as positive gate voltages.
6. Gate threshold voltage (VT,n) starts from the positive values.
7. Linear current will increase by increasing the gate voltage from the +Ve to -Ve gate
voltages.

Fig. 1.18 Structures, symbols and I/V characteristics of P- and N- channel MOSFETs of
enhancement and depletion types (A Summary report)

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 11
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 12
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 13
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 14
Fig.1.23 Cross-sectional view of an n-channel (nMOS) transistor,
(a) Operating in the linear region, [Conditions: VGS > VT & VDS = 0V]
(b) Operating at the edge of saturation, [Conditions: VGS > VT & VDS < VGS-VT]
(c) Operating beyond saturation. [Conditions: VGS > VT & VDS > VGS-VT]

Points to remember: After certain pinch-off point the transistor becomes stay in saturation
mode. Due to large increases of the VDS; If we increase gate voltage (i.e. VGS) the width of the
inverse channel will increase; Due to this ID current will increase means linear mode will rise.

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 15
1.9 nMOS Fabrication

Fig. 1.24 Process steps required for patterning of silicon dioxide

Basic steps:

1. Take a Si- substrate


2. Dry or Wet oxidation with silicon substrate
3. We will get a SiO2 layer on the silicon substrate
4. Epitaxy a photoresist (Si3N4) on the SiO2 layer
5. Take a GLASS MASK-1 our required feature
6. Explore UV-light through the glass mask on the photoresist
7. Use chemical (HF) or dry (Plasma) etching process to remove the exposed SiO2 layer
8. Remove the remaining photoresist
9. We get final model as shown in Fig. 1.24 (g).
Note: For every pattern generation or MASK c, d and e steps are common but diffusion or
deposition metals will different according to step.

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 16
Fig. 1.25 Process flow for the fabrication of an n-type MOS transistor

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 17
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 18
Step-5: A heavy boron implant can be used to form the p+ source and drain regions of the p-
MOSFETs. A layer of photoresist can be used to block the regions where n-MOSFETs are to be
formed.
Note: In the both cases the separation between the source and drain diffusions – channel
length – is defined by the polysilicon gate mask alone, hence the self-aligned property.
Step – 6: A photo-mask is used to define the contact window opening followed by a wet or dry
oxide etch.
Step-7: A thin aluminum layer is evaporated or sputtered onto the wafer. A final masking and
etching step is used to pattern the interconnections.

Fig. 1.26 A Typical n-well CMOS process flow


Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 19
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 20
than 10GHz. Normally, an n+ buried layer is used to reduce the series resistance of the collector
since the n-well has a very high resistivity.

Fig. 1.27 Cross-sectional diagram of a BiCMOS process

Table 1.2 n-well BiCMOS Fabrication Steps


Points to remember: CMOS for Logic implementation; BiCMOS for I/O and driver circuits;
Bipolar transistors also provide higher gain, better noise and high frequency characteristics than
MOS transistors. We can effectively increase the speed of VLSI circuits Using BiCMOS gates.

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 21
Table 1.3 Comparisons between CMOS and Bipolar Technologies

Flow Chart 1.1: Main steps in a typical n-well process

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 22
Some more points to remember regarding IC technology:

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 23
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 24
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 25
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 26
Fig. 2.4 Czochralski Crystal growth

Fig. 2.5 Silicon ingot and wafer slices

Fig. 2.6 Wafer with identification flats

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 27
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 28
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 29
2.10 Positive and Negative Photoresist

There are two types of photoresist: positive and negative. For positive resists, the resist is
exposed with UV light wherever the underlying material is to be removed. In these resists,
exposure to the UV light changes the chemical structure of the resist so that it becomes more
soluble in the developer. The exposed resist is then washed away by the developer solution,

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 30
leaving windows of the bare underlying material. In other words, "whatever shows, goes." The
mask, therefore, contains an exact copy of the pattern which is to remain on the wafer.
Negative resists behave in just the opposite manner. Exposure to the UV light causes the
negative resist to become polymerized, and more difficult to dissolve. Therefore, the negative
resist remains on the surface wherever it is exposed, and the developer solution removes only
the unexposed portions. Masks used for negative photoresists, therefore, contain the inverse
(or photographic "negative") of the pattern to be transferred. The figure below shows the
pattern differences generated from the use of positive and negative resist.
Negative resists were popular in the early history of integrated circuit processing, but positive
resist gradually became more widely used since they offer better process controllability for
small geometry features. Positive resists are now the dominant type of resist used in VLSI
fabrication processes.

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 31
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 32
Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 33
2.4.8 Metallization
The purpose of metallization is to interconnect the various components of the integrated circuit
(transistors, capacitors, etc.) to form the desired circuit. Metallization involves the deposition of
a metal (aluminum) over the entire surface of the silicon. The required interconnection pattern
is then selectively etched. The aluminum is deposited by heating it in vaccum until it vaporizes.
The vapors then contact the silicon surface and condense to form a solid aluminum layer.

Fig 2.15 Vacuum Evaporation for metallization

2.5 Integrated Resistors


Resistors in integrated form are not very precise. They can be made from varours diffusions, as shown in
Fig. 2.15. Different diffused regions have different resistivity. They n-well is usually used for medium-
value resistors, whereas the n+ and p+ diffusions are useful for low-value resistors. The actual resistance
value can be defined by changing the length and width of duffused regions. The tolerance of the
resistors value is very poor (20% to 50%), but the matching of two similar resistor values is quite good
(5%). Thus circuit designers should design circuits that exploit resistor matching and should avoid all
circuits that require a specific resistor value. Also note that diffused resistors have a significant
temperature coefficient.

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 34
All diffused resistors are slef-isolated by the reverse-biased pn junctions. One serious drawback for these
resistors is the fact that they are accompanied by a substantial parasitic junction capacitance, masking
them not very useful for high-frequency applications.
A more useful resistor can be fabricated using the polysilicon layer placed on top of the thick field oxide.
The thin layer provides a better provides a better surface area matching and hence more accurate
resistor ratios. Furthermore, the polyresistor is physically separated from the substrate and exhibits a
much lower parasitic capacitance.

Fig. 2.16 Cross sections of various types of resistors available from a typical n-well CMOS Process

2.6 Integrated Capacitors


Two types of capacitor structures are available in CMOS processes, MOS and inter-poly capacitors. The
cross sections of these structures are shown in Fig. 2.16. The MOS gate capacitance, depicted by the
center structure, is basically the gate-to-source capacitance of a MOSFET. The capacitance value is
dependent on the gate area. The oxide thickness is the same as the gate oxide thickness in the
MOSFETs. This capacitor exhibits a large voltage dependence. To eliminate this problem, an addition n+
implant is required to form th bottom plate of the capacitors, as shown in the structure on the right.
Both of these MOS capacitors are physically in contact with the substrate, resulting in a large parasitic
pn junction capacitance at the bottom plate.
The inter poly capacitor exhibits near ideal characteristics but at the expense of the addition of a second
poly layer to the CMOS process. Since this capacitor is placed on top of the thick field oxide,parasitic
effects as kept to a minimum.
A third and less often used capacitor is the junction capacitor. Any pn junction under reverse bias
produces a depletion region that acts as a dielectric between the p- and the n- regions. The capacitance

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 35
is determined by gemetry and doping levels and with a large voltage coefficient. The fact that this
capacitor works only with reverse bias voltages makes it less useful.
The inter-poly and the MOS capacitors, the capacitance values can be contgrolled to within 1%.
Paractical capacitance values range from 0.5 pF to a few 10s of pF. The matching between similar-size
capacitors can be within 0.1%. This property is extremely useful for designing precision anolog CMOS
circuit.

Fig. 2.17Inner-poly and MOS capacitors in an n-well CMOS Process

2.7 Different Packing Styles and Process Summarize:

Fig. 2.18 Exploded view of lead TO-5 package

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 36
Fig. 2.19 Exploded view of 14-lead version of the flat package

SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

Fig. 2.20 Design Abstraction Levels


TEXT BOOKS:

1. Kamran Ehraghian, Dauglas A. Pucknell and Sholeh Eshraghiam, “Essentials of VLSI


Circuits and Systems” – PHI, EEE, 2005 Edition.
2. Neil H. E. Weste and David. Harris Ayan Banerjee, “CMOS VLSI Design” - Pearson
Education, 1999.
3. Sung-Mo Kang, Yusuf Leblebici,”CMOS Digital Integrated Circuits” TMH 2003

Dr. Fazal Noorbasha, Associate Professor, VLSI Systems Research Group Head, M.Tech. Admin. Incharge , Dept. of ECE - KLU 37