ModelSim

Verilog
Tutorial
Watch Design

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4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390;
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5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189; 5,410,194; 5,414,377;
5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,455,525; 5,466,117;
5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478; 5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196;
5,498,979; 5,498,989; 5,499,192; 5,500,608; 5,500,609; 5,502,000; 5,502,440; 5,504,439; 5,506,518; 5,506,523; 5,506,878; 5,513,124;
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5,752,006; 5,752,035; 5,754,459; 5,758,192; 5,760,603; 5,760,604; 5,760,607; 5,761,483; 5,764,076; 5,764,534; 5,764,564; 5,768,179;
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5,821,772; 5,821,774; 5,825,202; 5,825,662; 5,825,787; 5,828,230; 5,828,231; 5,828,236; 5,828,608; 5,831,448; 5,831,460; 5,831,845;
5,831,907; 5,835,402; 5,838,167; 5,838,901; 5,838,954; 5,841,296; 5,841,867; 5,844,422; 5,844,424; 5,844,829; 5,844,844; 5,847,577;
5,847,579; 5,847,580; 5,847,993; 5,852,323; 5,861,761; 5,862,082; 5,867,396; 5,870,309; 5,870,327; 5,870,586; 5,874,834; 5,875,111;
5,877,632; 5,877,979; 5,880,492; 5,880,598; 5,880,620; 5,883,525; 5,886,538; 5,889,411; 5,889,413; 5,889,701; 5,892,681; 5,892,961;
5,894,420; 5,896,047; 5,896,329; 5,898,319; 5,898,320; 5,898,602; 5,898,618; 5,898,893; 5,907,245; 5,907,248; 5,909,125; 5,909,453;
5,910,732; 5,912,937; 5,914,514; 5,914,616; 5,920,201; 5,920,202; 5,920,223; 5,923,185; 5,923,602; 5,923,614; 5,928,338; 5,931,962;
5,933,023; 5,933,025; 5,933,369; 5,936,415; 5,936,424; 5,939,930; 5,942,913; 5,944,813; 5,945,837; 5,946,478; 5,949,690; 5,949,712;
5,949,983; 5,949,987; 5,952,839; 5,952,846; 5,955,888; 5,956,748; 5,958,026; 5,959,821; 5,959,881; 5,959,885; 5,961,576; 5,962,881;
5,963,048; 5,963,050; 5,969,539; 5,969,543; 5,970,142; 5,970,372; 5,971,595; 5,973,506; 5,978,260; 5,986,958; 5,990,704; 5,991,523;
5,991,788; 5,991,880; 5,991,908; 5,995,419; 5,995,744; 5,995,988; 5,999,014; 5,999,025; 6,002,282; and 6,002,991; Re. 34,363, Re. 34,444,
and Re. 34,808. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free
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ModelSim Verilog Tutorial
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The following table shows the revision history for this document.

Date Version Revision

06/01/00 1.0 Initial Xilinx release.
07/21/00 1.1 Accumulated miscellaneous updates and bug fixes.

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Contents

ModelSim Verilog Tutorial

Design Description ............................................................................................................... 1
Inputs................................................................................................................................... 1
Outputs ................................................................................................................................ 1
Functional Blocks ............................................................................................................... 2
Before Beginning the Tutorial.......................................................................................... 2
Tutorial Installation ............................................................................................................ 2
Tutorial Directory and Files................................................................................................ 2
Copying the Tutorial Files .................................................................................................. 3
Verilog Design Files ........................................................................................................... 3
Script Files .......................................................................................................................... 3
Verilog Libraries .................................................................................................................. 3
UniSim Library ................................................................................................................... 3
CORE Generator Library .................................................................................................... 3
SimPrim Library ................................................................................................................. 4
Creating the Tenths CORE Generator Component ................................................. 4
Instantiating the CORE Generator Module ................................................................ 7
RTL Simulation .................................................................................................................... 7
Using the glbl.v Module...................................................................................................... 8
Running Verilog Simulation ............................................................................................... 8
Compiling the Verilog Libraries ......................................................................................... 8
Starting ModelSim ............................................................................................................... 8
Copying Source Files to the RTL Simulation Directory..................................................... 9
Creating the Work Directory............................................................................................... 9
Compiling the Verilog Source Files.................................................................................... 9
Invoke the Simulator ......................................................................................................... 10
Running the Simulation .................................................................................................... 10
Implementing the Watch Design ................................................................................... 11
Verilog Timing Simulation .............................................................................................. 12

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ModelSim Verilog Tutorial

This tutorial shows you how to use MTI’s ModelSim Verilog for simulation. It guides you through
a typical FPGA HDL-based design procedure using an unfinished design that you download from
the Xilinx Web site. The tutorial design is named “watch” and is intended to perform like a track
coach's stopwatch. This tutorial contains the following sections.
• “Design Description”
• “Before Beginning the Tutorial”
• “Tutorial Installation”
• “Verilog Libraries”
• “Creating the Tenths CORE Generator Component”
• “Instantiating the CORE Generator Module”
• “RTL Simulation”
• “Starting ModelSim”
• “Implementing the Watch Design”
• “Verilog Timing Simulation”

Design Description
The design used in this tutorial is a hierarchical, HDL-based design. The top-level design file is an
HDL file that references several other lower-level macros. The lower-level macros are either HDL
modules or CORE Generator modules.
The tutorial begins with an unfinished design. You will complete the design by generating some of
the modules from scratch, and by completing other modules from existing files. When the design is
complete, it is simulated to verify functionality.
The Watch design is intended to perform like a track coach’s stopwatch. There are three external
inputs, and three external output buses in the completed design. The system clock is an externally
generated signal. The inputs, outputs, and functional blocks are listed below.

Inputs
• STRTSTOP — This is an active low signal that starts and stops the stopwatch.
• RESET—Resets the stopwatch to 00.0 after it has been stopped.
• CLK—Externally generated system clock.

Outputs
• TENSOUT[6:0]—7-bit bus that represents the tens digit of the stopwatch value. This bus is in
7-segment display format as viewable on the 7-segment LED display on the Xilinx
demonstration board.
• ONESOUT[6:0]—Similar to TENSOUT, but represents the ones digit of the stopwatch value.

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• TENTHSOUT[9:0]—10-bit one-hot encoded bus that represents the tenths digit of the
stopwatch value.

Functional Blocks
• STATMACH
State Machine module.
• CNT60
HDL-based module that counts from 0 to 59 in decimal. This macro has two 4-bit outputs that
represent the ones and tens digits of the decimal values, respectively.
• TENTHS
CORE Generator 4-bit, binary encoded counter. This macro outputs a 4-bit code that is decoded
to represent the tenths digit of the stopwatch value as a 10-bit one-hot encoded value.
• HEX2LED
HDL-based macro. This macro decodes the ones and tens digit values from hexadecimal to 7-
segment display format.
• SMALLCNTR
A simple counter.

Before Beginning the Tutorial

Before you begin this tutorial, set up your system to use the Model Technology and Xilinx software
as follows.
1. Install the following software.
- Xilinx Development System 3.1i
- Model Technology ModelSim EE/PE/XE 5.3a or later
2. Verify that your system is properly configured. Consult the release notes and installation notes
that came with your software package for more information.

Tutorial Installation
The Watch tutorial file is available for download from the Xilinx Web site at
http://support.xilinx.com/support/techsup/tutorials.

Tutorial Directory and Files

The tutorial directory and files needed to complete the design are provided for you. The following
table lists the contents of the tutorial directories.

Directory Description
mti_vlog/watch working directory
mti_vlog/watch_source Verilog source and script files
mti_vlog/watch_solution Verilog solution files

Copying the Tutorial Files

In this tutorial, “watch” is the name of the directory where the tutorial will be performed. Copy all
of the files from the mti_vlog/watch_source directory to the mti_vlog/watch directory.

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Verilog Design Files

Watch is the top-level design. The tutorial uses the following Verilog files.
• stopwatch.v
• statmach.v
• smallcntr.v
• decode.v
• cnt60.v
• hex2led.v
• stopwatch_tb.v (Verilog test fixture for simulation)

Script Files
The following script files are provided to automate the steps in this tutorial.
• rtl_sim.do
• stim.do
• time_sim.do

Verilog Libraries
To simulate the Watch design, you need the following simulation libraries.

UniSim Library
The UniSim library is used for functional simulation only. The models in this library contain only
unit delays. This library includes all Xilinx Unified Library primitives that are inferred by most
popular synthesis tools.
For Verilog, separate libraries are provided for common technologies that share the same
functionality. This combined library makes it easy to retarget designs to other technologies. It is not
necessary to change the library mapping statements when switching from Virtex™ to Virtex-E or
from Spartan™ to Virtex.
The Verilog UniSim Library source files are provided in $XILINX/verilog/src/unisims (Series 4KE,
4KX, 4KL, 4KXV, Spartan, Virtex).

CORE Generator Library

CORE Generator is a graphical interactive design tool for creating high-level modules such as
counters, shift registers, RAM and multiplexers. You can customize and pre-optimize the modules
to take advantage of the inherent architectural features of FPGAs, such as Fast Carry Logic for
arithmetic functions, and on-chip, dual-port and synchronous RAM. You can also select the
appropriate HDL model type as output.
The CORE Generator HDL library models are used for RTL simulation. The models do not use
library components for global signals.
The Verilog CORE Generator source files are provided in $XILINX/verilog/src/XilinxCoreLib.

SimPrim Library
The SimPrim library is used for post-NGDBuild (gate-level functional), post-Map (partial timing),
and post-PAR (full timing) simulations. This library is architecture independent.
The Verilog SimPrim Library source files are provided in $XILINX/verilog/src/simprims.

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Creating the Tenths CORE Generator Component

If you have previously created the CORE Generator component, you may skip this section without
loss of continuity in the tutorial.
The first step in this tutorial is creating the CORE Generator component. When you create the
component, you will create a behavioral simulation netlist for RTL simulation and an
implementation netlist.
The CORE Generator module is named Tenths, and is a 4-bit binary encoded counter. The 4-bit
number is decoded to count the tenths digit of the stopwatch time value.
To create the CORE Generator component, follow these steps.
1. To invoke the CORE Generator, type coregen at the UNIX prompt, or if you are using a PC,
click on the CORE Generator icon in the Xilinx Program group.
2. From Project → Project Options, select Verilog and your synthesis vendor of choice for your
design entry.
3. In the Target Architecture field, select Virtex.

Figure 1: CORE Generator Setup Dialog

4. Click OK to close the dialog box.

5. A list of possible COREs are available. Double click on Basic Elements - Counters.
6. Double click on Binary Counter to open the Binary Counter dialog box. This dialog box
allows you to customize the counter to the design specifications.
7. Fill in the Binary Counter dialog box with the following settings.
- Component Name: tenths
Defines the name of the module.
- Output Width: 4
Defines the width of the output bus.

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- Operation: Up
Defines how the counter will operate. This field is dependent on the type of module you
select.
- Count Restrictions: Restrict Count to A
This specifies the maximum count value.
- Output Options: Threshold 0 set to A
Signal goes high when the value specified has been reached.
- Output Options: Registered

Figure 2: CORE Generator Module Selection

8. Click on the Register Options button to open the Register Options dialog box. Enter the
following settings.
- Clock Enable: Selected
- Asynchronous Settings: Init with a value of 1
- Synchronous Settings: None

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Click OK.

Figure 3: Register Options Dialog

9. Check that only the following pins are used.

- AINIT
- CE
- Q
- Q_Thresh0
- CLK
10. Click Generate to create the module.
11. Select Cancel and close CORE Generator.
CORE Generator generates the following output files.
- tenths.edn
Netlist file that is used during the Translate phase of implementation
- tenths.veo
Instantiation template that is used to incorporate the CORE Generator module in your
source Verilog file
- tenths.xco
Stores the configuration information for the Tenths module

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- coregen.prj
Stores the CORE Generator configuration for the project

Instantiating the CORE Generator Module

If you have previously instantiated the CORE Generator component, you may skip this section
without loss of continuity in the tutorial.
To instantiate the CORE Generator module, you must copy information from the tenths.veo file to
the stopwatch.v file, as described in the following steps.
1. Open stopwatch.v in your favorite editor, and then open the tenths.veo file. Copy the module
declaration from the tenths.veo file to the stopwatch.v file at the following location.
"// Place the Coregen Module Declaration for Tenths here"
The template module declaration for the Coregen instantiation is inserted.
2. From the tenths.veo file, copy from the line “Tenths your_instance_name” to
“.AINIT=(AINIT));” to stopwatch.v at the following location.
"--Place the CoreGen Component Instantiation for Tenths here."
3. In the stopwatch.v file, change “your_instance_name” to “XCOUNTER”.
4. Edit the following code in the stopwatch.v file to connect the signals in the stopwatch design to
the ports of the CoreGen module.
tenths XCOUNTER (.Q(Q), .CLK(CLK), .Q_THRESH0(xtermcnt),
.CE(clkenable), .AINIT(rstint));

5. Save stopwatch.v and exit the editor.

RTL Simulation
RTL-level (behavioral) simulation allows you to verify or simulate a description at the system or
chip level. This first pass simulation is typically performed to verify code syntax, and to confirm that
the code is functioning as intended. At this step in the tutorial, no timing information is provided and
simulation is performed in a unit-delay mode to avoid the possibility of a race condition.
RTL simulation is not architecture-specific unless the design contains instantiated UniSim, CORE
Generator, or LogiBLOX components.
A general suggestion during the initial design creation is to keep the code behavioral. Avoid
instantiating specific components unless necessary. This allows for more readable code, faster and
simpler simulation, code portability (the ability to migrate to different device families) and code
reuse (the ability to use the same code in future designs). However, you may find it necessary to
instantiate components structurally in order to obtain the desired design structure or performance.
It is important to address the built-in reset circuitry behavior in a design starting with the first
simulation to ensure that subsequent simulations agree at different points.
Virtex devices have register (flip-flops and latches) set/reset circuitry that pulses at the end of the
configuration mode. This pulse is automatic and does not need to be programmed. All the flip-flops
and latches receive this pulse through a dedicated global set/reset (GSR). The registers either set or
reset, depending on how the registers are defined.
If the you do not simulate GSR behavior prior to synthesis and PAR, the RTL and possibly post-
synthesis simulations will not initialize to the same state as the post-route timing simulation. As a
result, various design descriptions are not functionally equivalent and simulation results will not
match.
Even if GSR behavior is not described, the actual chip initializes during configuration, and the post-
route netlist will have this net that must be driven during simulation.
In addition to the set/reset pulse, all output buffers are tristated during configuration mode with the
dedicated global output tristate enable (GTS) net.

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Using the glbl.v Module

The general procedure for specifying global signals for a Verilog simulation flow includes defining
the global signals with the $XILINX/verilog/src/glbl.v module. This module allows a global signal
to be modeled as a wire in a global module. The glbl.v module enables the use of the global set/reset
in the design, and it is referenced by the UniSim and SimPrim libraries.
The glbl.v module must be loaded in the simulation process.

Running Verilog Simulation

There are two methods for running Verilog simulation. You can use library source files with compile
time options, or you can use shared pre-compile libraries.

Using Library Source Files with Compile Time Options

Depending on the type of design (Xilinx instantiated primitives, or CORE Generator components)
for RTL simulation, specify the following at the ModelSim prompt.
vlog -y $XILINX/verilog/src/unisims +incdir+$XILINX/verilog/src
+libext+.v $XILINX/verilog/src/glbl.v -incr -R testfixture.v design.v

Using Shared Pre-compiled Libraries

Depending on the type of design (Xilinx instantiated primitives, or CORE Generator components)
for RTL simulation, specify the following at the ModelSim prompt:
vlog $XILINX/verilog/src/glbl.v testfixture.v design.v -incr -R -L
unisims_ver -L xilinxcorelib_ver -

Compiling the Verilog Libraries

For ModelSim, you may need to compile the HDL libraries before using them for design
simulations. The advantages of the compiled approach are speed of execution and economy of
memory.
Xilinx provides a utility to compile the HDL libraries with most popular simulators. This utility is
available at $XILINX/bin/platform/compile_hdl.pl
Refer to http://support.xilinx.com/techdocs/8066.htm for information on compiling the
XilinxCoreLib library.

Starting ModelSim
If you are using the PC, invoke the simulator by selecting the following from the Start menu.
Programs → Model Tech → ModelSim
For UNIX workstations, type the following at the prompt.
vsim -i &
Set the project directory using the File → Change Directory menu command and select watch/rtl.

Copying Source Files to the RTL Simulation Directory

For the Verilog tutorial, copy the following files into the mti_vlog/watch/rtl directory from the
mti_vlog/watch_source directory.
• stopwatch.v
• statmach.v
• smallcntr.v
• decode.v
• cnt60.v
• hex2led.v

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• stopwatch_tb.v
• rtl_sim.do
• glbl.v

Creating the Work Directory

Before compiling the Verilog source files, you must create a directory to use as a library. Type the
following at the ModelSim prompt.
vlib work
This action is echoed in the Transcript window as shown in the following figure.

Figure 4: MTI Transcript Window

Compiling the Verilog Source Files

Copy the $XILINX/verilog/src/glbl.v file to your working directory.
Since a shared pre-compiled simulation approach will be used, you must open the stopwatch.v file
and comment out the following line.
// ‘include "XilinxCoreLib/C_COUNTER_BINARY_V1_0.v"
The C_COUNTER_BINARY_V1_0 module has already been compiled and mapped to the
xilinxcorelib_ver library.
The Vlog command compiles Verilog code for use with Vsim RTL simulation. Type the following
at the ModelSim prompt.
vlog stopwatch_tb.v stopwatch.v statmach.v decode.v hex2led.v cnt60.v
smallcntr.v glbl.v

Invoke the Simulator

Type the following at the ModelSim prompt to invoke the ModelSim simulator.
vsim -L xilinxcorelib_ver -L unisims_ver test glbl
Note: You can run the rtl_sim_xilinx.do file to execute the above commands instead of
executing each command. To run this file, type the following at the ModelSim prompt.
do rtl_sim.do
Optionally, you can launch the macro with the Macro → Execute Macro menu command.

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Running the Simulation

To perform simulation using ModelSim, follow these steps.
1. To view all the ModelSim debug windows, type the following.
view *
2. Add the signals from the selected region in the Structure window to the Wave and List windows
by entering the following commands at the ModelSim prompt.
add wave /test/*
add list /test/*

3. In the Structure window, notice that Verilog modules are indicated by circles. You can expand
and collapse regions of hierarchy by clicking on the (+) and (-) notations.
4. To run the simulation for a specified amount of time at the ModelSim prompt, type the
following.
run 100000 ns
The simulation output is displayed in the Wave window. You may have to zoom in or out to
view the waveforms.
5. In the Wave window, try adding or removing cursors with the Cursor → Add | Remove menu
command. When multiple cursors are drawn, ModelSim adds a delta measurement showing the
time difference between the cursors. The selected cursor is drawn as a solid line and the values
at the cursor location are shown to the right of the signal name. All other cursors are drawn as
dotted lines. If you cannot see the signal value next to the signal name, select the bar separating
the signal names from the waveforms and drag it to the right.
Note: The above commands have been combined into a macro file called stim.do that you can
run at the ModelSim prompt.

Figure 5: Simulation Output in Wave Window

Implementing the Watch Design

To implement the Watch design, refer to the Xilinx Design Manager Tutorial. You need the
following files for implementation.
• watch.edf
• tenths.edn

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Before you implement the Watch design with the Xilinx Design Manager, you need to set the
Implementation Options Timing Template to ModelSim Verilog to produce the time_sim.v file, and
time_sim.sdf for timing simulation. To set these options, follow these steps.
1. In the Design Manger Implement window, select Design → Options to open the Options dialog
box.
2. In the Program Options section of the dialog box, set Simulation to ModelSim Verilog.

Figure 6: Design Manager Options Dialog Box

3. Proceed with the Design Manager Tutorial.

Note: Although not included in this tutorial, it is possible to run a post-NGDBuild and post-
Map simulation, which may be helpful for debugging the design.

Verilog Timing Simulation

You need two files from the Xilinx tools.
• time_sim.v
• time_sim.sdf
To perform timing simulation, follow these steps.
1. Copy time_sim.v, time_sim.sdf, and testfixture.v to the following directory.
mti_vlog/watch/time_sim
2. Launch ModelSim, and navigate to the mti_vlog/watch/time_sim directory.
3. Create the work directory.
vlib work
4. Compile the Verilog file and the test fixture.

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vlog testfixture.v time_sim.v

5. Read in the SDF file for timing simulation. NGD2VER automatically writes out a directive,
$sdf_annotate, within the time_sim.v file. This directive specifies the appropriate SDF file to
use in conjunction with the generated netlist. Consequently, you do not need to specify an
option for ModelSim to read the SDF.
vsim -L simprims_ver test
At this point, the HDL netlist has been resolved into primitives, and the next step is to provide
the simulation models to the SimPrim library.
6. View the necessary debugging windows by typing the following command at the ModelSim
prompt.
view wave signals source

7. View and add the signals of the design to the waveform window.
8. At the ModelSim prompt, type.
run 100000 ns
9. To zoom in, right click in the waveform window, or press and hold the middle mouse button and
draw a square around the area you want to zoom in on. After simulating, you can zoom in and
view the delay from the clock edge to the TENSOUT, ONESOUT, and TENTHSOUT output
change.
Note: The above commands are included in the macro file, time_sim.do, and can be executed at
the ModelSim prompt.
The MTI ModelSim Vlog/Xilinx Tutorial is now completed!

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