An On-Chip All-Digital Measurement

Circuit to Characterize Phase-Locked

Loop Response in 45-nm SOI
Dennis Fischette, Richard DeSantis, John H. Lee1

AMD, Sunnyvale, California, USA

1 MIT, Cambridge, Massachusetts, USA

Custom Integrated Circuits Conference

September 16, 2009

1
Outline
 Motivation
 Loop Measurement Circuit
• Algorithm
• Architecture
 Silicon Results
 Conclusion

2
 PLL Closed-Loop Transfer Function
 Frequency domain model
 Input: “excess” phase modulation of input (reference) clock
 Output: “excess” phase modulation of feedback clock

+6

Normalized Jitter Transfer (dB)

refclk t   2 fc t  mod t 
Peaking Low
+4 damping
High
+2
damping

PLL 0
BW
-2

feedback t   2 fc t  f mod t  -4

-6
100kHz 1MHz 10MHz 100MHz

Jitter Modulation Frequency

3
Motivation
 Strict bandwidth and peaking requirements
 e.g., PCI Express Generation II @ 5 Gb/s
 58 MHz BW / < 1 dB peaking
 816 MHz BW / < 3 dB peaking

 Locktime (function of BW) increasingly important

given frequent exit from sleep/power-save states
 Device PVT variation  simulations inadequate
 Standard methods
 Spectrum Analyzer, Waveform Generator

 Problems with standard methods

 Slow  expensive
 Wafer? Package? Product?  inflexible

4
Outline
 Motivation
 Loop Measurement Circuit
• Algorithm
• Architecture
 Silicon Results
 Conclusion

5
Simulated Step Response vs. Time
+6

MaxOvershoot
+4
Phase Error (ns)

+2

-2

-4 Tcrossover

-6

-8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Time (µs)

6
Basis of Algorithm
 Relationship between time & frequency domain behavior
 Lower BW  higher Tcrossover
 Larger input phase step  larger peaking
Linear Fit Linear Fit
0.25 5

MaxOvershoot (ns)
0.20 4
Tcrossover (µs)

0.15 3

0.10 Trefclk 2 Trefclk

Phase Step Phase Step
0.05 50% 1 50%
75% 75%

0.00 0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 7 8 9

1/BW (µs) Peaking (dB)

7
Closed-Form Equations for Phase Error

 Damping Factor  < 1 (underdamped)

  
err t   step  e  n t
 cos n t 1   2   sin n t 1   
2

   1 2  
 

 Damping Factor  = 1 (critically damped)

err t   step  e nt  1  n t 

 Damping Factor  > 1 (overdamped)

err t   step  e  n t
  
 cosh n t  2  1   sinh n t  2  1 
    2
 1  
 

Source: Gardner, Phaselock Techniques, 2005

8
Closed-Form Equations vs. Simulations

75% Trefclk Phase Step 75% Trefclk Phase Step

0.25 5

MaxOvershoot (ns)
0.20 4
Tcrossover (µs)

0.15 3

0.10 2

0.05 Simulation 1 Simulation

Equation Equation

0.00 0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 7 8 9

1/BW (µs) Peaking (dB)

 Equations become less accurate at high  due to

smoothing loop filter pole for reference spur reduction

9
PLL + Loop Measurement Circuit
 Digital State Machine  no analog circuits
 Minimal overhead/intrusion  communicates with feedback divider only
 Instantaneously steps feedback clock phase – programmable, directional
 Measures Tcrossover and MaxOvershoot
Gain Control Range Control
RefClk
UP
Phase- Charge Voltage-
Frequency Pump Controlled Vco
Detector DN Oscillator

FbClk Feedback
Divider

FbCnt[5:0] FbDiv[5:0]

Nstep[5:0]
N[5:0] Loop BwCnt[9:0]
Measurement MaxOvershoot[5:0]
Circuit BwValid
Start

10
Loop Measurement Circuit
RefRise N[5:0]
FbDiv[5:0]
RefClk D Q D Q N[5:0]+K[5:0] To Feedback
Edge Detector Divider
FbRise BwValid RefRise
Vco Vco
Control RefFall
En Clr En
Delay D
Unit StartRise
Hold D
D until Q
until En=1
D Hold D Q
En=1 StepEn until Clr=1
Start D Q D Q
From Edge Detector Vco Vco
JTAG
Vco Vco

BwEn
Tcrossover Load_BBPD
RefRise
Detector En En En
BBPD BBPD1 BBPD2
FbClk D Q D Q D Q BW Q BwCnt[9:0]
Counter
To JTAG
RefClk
Vco Vco Vco
BwValid

MaxOvershoot Compare
NewMaxOS
RefRise UpdateOS
Detector En
FbCnt[5:0] SmplCnt[5:0]
D Q
From D Q MaxOvershoot[5:0]
Feedback To JTAG
Divider Vco
RefFall

11
Control Unit
Vco

RefClk
RefRise
RefFall
Start
StartRise
FbRise
StepEn
BwEn

RefRise N[5:0]
FbDiv[5:0]
RefClk D Q D Q N[5:0]+K[5:0] To Feedback
Edge Detector Divider
FbRise BwValid RefRise
Vco Vco
RefFall
En Clr En
Hold D Delay D
StartRise until En=1
D until Q D Hold D Q
En=1 StepEn until Clr=1
Start D Q D Q
From Edge Detector Vco Vco BwEn
JTAG
Vco Vco

To Tcrossover
crossover Detector 12
Control Unit and Phase Step
Vco

RefClk

StepEn
FbDiv[5:0] 8 11 8

FbCnt[5:0] 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 0

FbClk

BwEn

BwCnt[9:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13

RefRise N[5:0]
FbDiv[5:0]
RefClk D Q D Q N[5:0]+K[5:0] To Feedback
Edge Detector Divider
FbRise BwValid RefRise
Vco Vco
RefFall
En Clr En
Hold D Delay D
StartRise until En=1
D until Q D Hold D Q
En=1 StepEn until Clr=1
Start D Q D Q
From Edge Detector Vco Vco BwEn
JTAG
Vco Vco

To Tcrossover
crossover Detector 13
Bandwidth/Tcrossover Test
Vco

RefClk

FbClk
BBPD

Load_BBPD

BBPD1
BBPD2

BwValid

BwCnt[5:0] 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

From Control Unit

Load_BBPD BwEn
RefRise

BBPD En BBPD1 En BBPD2 En

FbClk D Q D Q D Q BW Q BwCnt[9:0]
Counter
To JTAG
RefClk
Vco Vco Vco
BwValid

14
 Peaking/MaxOvershoot Test
RefClk

RefRise

RefFall

Vco

FbCnt[5:0] 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4

SmplCnt[5:0] 2 3 4 3 2

UpdateOS

MaxOvershoot[5:0] 0 3 4

BwValid

NewMaxOS
Compare
RefRise UpdateOS
En SmplCnt[5:0]
FbCnt[5:0] D Q
From D Q MaxOvershoot[5:0]
Feedback To JTAG
Divider Vco
RefFall

15
Outline
 Motivation
 Loop Measurement Circuit
• Algorithm
• Architecture
 Silicon Results
 Conclusion

16
Simulations vs. Measurements
 100 MHz refclk, feedback divisor = 50 (2x25)
Bandwidth (MHz) Peaking (dB)
Rlpf Icp Measured Measured
Case
(kW) (µA) Simulated Part Part Part Simulated Part Part Part
1 2 3 1 2 3
1 3.2 2.5 1.8 3.4 3.4 3.0 8.5 4.2 4.1 4.2
2 3.2 5 2.6 3.1 3.2 3.2 6.2 4.3 4.0 4.2
3 3.2 10 4.0 5.0 5.4 5.3 4.3 3.0 2.8 2.8
4 3.2 20 6.6 9.3 10.0 10.0 2.9 1.8 1.5 1.7
5 4.8 10 4.8 6.2 6.8 6.5 2.6 1.7 1.5 1.3
6 4.8 20 9.0 13.2 14.8 14.2 1.7 0.9 0.7 0.7
7 6.4 5 3.3 4.3 4.5 4.5 2.8 1.9 2.0 1.7
8 6.4 10 6.0 8.1 9.1 9.0 1.8 1.1 1.0 1.0
9 6.4 20 12.0 17.6 19.7 18.7 1.2 0.7 1.1 1.0
10 6.4 30 18.1 25.6 27.1 26.2 0.8 2.1 2.6 2.8
11 6.4 40 23.3 25.7 26.8 26.1 1.2 2.2 2.5 2.8
12 6.4 70 35.2 25.7 26.7 25.9 3.0 2.1 2.3 2.6
17
Measured Tcrossover vs. 1/BW

0.15

0.12
Tcrossover (µs)

0.09

0.06
Trefclk Phase Step
50% measured
0.03
75% simulated
75% measured
0.00
0.0 0.1 0.2 0.3 0.4

1/BW (µs)
18
Measured MaxOvershoot vs. Peaking

3.0

2.5
MaxOvershoot (ns)

2.0

1.5
Trefclk Phase Step
1.0 50% simulated
50% measured
0.5 75% simulated
75% measured
0.0
0 1 2 3 4 5
Peaking (dB)
19
Power and Area
 Power (simulated) = 2.5 mW
 Output frequency = 2.5 GHz
 VDD = 1.2 V
 Clocks gated when not in use

 Area = 2,750 µm2

 45-nm SOI-CMOS
 Can easily be reduced by 4050% by replacing
non-critical sense-amplifier flip-flops with smaller
master-slave flip-flops and optimizing overshoot
comparator
 Layout area not a serious concern in this design

20
Outline
 Motivation
 Loop Measurement Circuit
• Algorithm
• Architecture
 Silicon Results
 Conclusions

21
Conclusion

 An on-chip, all-digital state machine can be

used to accurately estimate PLL bandwidth
and peaking with potentially large savings in
tester time.

 This flexible circuit may be used from wafer

level to product level, minimizing die/package
waste and allowing for adaptive PLL loop
calibration.

22
Acknowledgments

 Alvin Loke - AMD

 Gerry Talbot - AMD

23