poor scalability in multiprocessor environments.

In many cases, the hardware has the final

decision as to which processor will be interrupted out of the possible set that the Plug and Play
manager selected for this interrupt, and there is little device drivers can do.

A solution to all these problems is a new interrupt mechanism first introduced in the PCI 2.2
standard called message-signaled interrupts (MSI). Although it remains an optional component
of the standard that is seldom found in client machines, an increasing number of servers and
workstations implement MSI support, which is fully supported by the all recent versions of
Windows. In the MSI model, a device delivers a message to its driver by writing to a specific
memory address. This action causes an interrupt, and Windows then calls the ISR with the
message content (value) and the address where the message was delivered. A device can also
deliver multiple messages (up to 32) to the memory address, delivering different payloads
based on the event.

Because communication is based across a memory value, and because the content is delivered
with the interrupt, the need for IRQ lines is removed (making the total system limit of MSIs
equal to the number of interrupt vectors, not IRQ lines), as is the need for a driver ISR to query
the device for data related to the interrupt, decreasing latency. Due to the large number of
device interrupts available through this model, this effectively nullifies any benefit of sharing
interrupts, decreasing latency further by directly delivering the interrupt data to the concerned
ISR.

Finally, MSI-X, an extension to the MSI model, which is introduced in PCI 3.0, adds support for
32-bit messages (instead of 16-bit), a maximum of 2048 different messages (instead of just 32),
and more importantly, the ability to use a different address (which can be dynamically
determined) for each of the MSI payloads. Using a different address allows the MSI payload to
be written to a different physical address range that belongs to a different processor, or a
different set of target processors, effectively enabling nonuniform memory access (NUMA)-
aware interrupt delivery by sending the interrupt to the processor that initiated the related
device request. This improves latency and scalability by monitoring both load and closest
NUMA node during interrupt completion.

Now practice.
Checking for PCI devices working in MSI-mode.
Go to Device Manager. Click in menu "View -> Resources by type". Expand "Interrupt request
(IRQ)" node of the tree. Scroll down to "(PCI) 0x... (...) device name" device nodes. Devices
with positive number for IRQ (like "(PCI) 0x00000011 (17) ...") are in Line-based interrupts-
mode. Devices with negative number for IRQ (like "(PCI) 0xFFFFFFFA (-6) ...") are in Message
Signaled-based Inte