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a Low-Cost 270 MHz

Differential Receiver Amplifiers


AD8129/AD8130
FEATURES CONNECTION DIAGRAM
High Speed (Top View)
AD8130: 270 MHz, 1090 V/s @ G = 1 SO-8 (R) and Micro_SO-8 (RM)
AD8129: 200 MHz, 1060 V/s @ G = 10 AD8129/
High CMRR AD8130
+IN 1 8 –IN
94 dB Min, DC to 100 kHz
80 dB Min @ 2 MHz –VS 2
+ 7 +VS
70 dB @ 10 MHz
PD 3 6 OUT
High-Input Impedance: 1 M Differential
Input Common-Mode Range 10.5 V REF 4 5 FB

Low Noise
AD8130: 12.5 nV/√Hz
AD8129: 4.5 nV/√Hz data transmission. The AD8129 and AD8130 are differential-
Low Distortion, 1 V p-p @ 5 MHz: to-single-ended amplifiers with extremely high CMRR at high
AD8130, –79 dBc Worst Harmonic @ 5 MHz frequency. Therefore, they can also be effectively used as
AD8129, –74 dBc Worst Harmonic @ 5 MHz high-speed instrumentation amps or for converting differential
User-Adjustable Gain signals to single-ended signals.
No External Components for G = 1 The AD8129 is a low-noise high-gain (10 or greater) version
Power Supply Range +4.5 V to 12.6 V intended for applications over very long cables where signal
Power-Down attenuation is significant. The AD8130 is stable at a gain of one
and can be used for those applications where lower gains are
APPLICATIONS
required. Both have user adjustable gain to help compensate for
High-Speed Differential Line Receiver
losses in the transmission line. The gain is set by the ratio of
Differential-to-Single-Ended Converter
two resistor values. The AD8129 and AD8130 have very high
High-Speed Instrumentation Amp
input impedance on both inputs regardless of the gain setting.
Level-Shifting
The AD8129 and AD8130 have excellent common-mode rejec-
GENERAL DESCRIPTION tion (70 dB @ 10 MHz) allowing the use of low cost unshielded
The AD8129 and AD8130 are designed as receivers for the twisted-pair cables without fear of corruption by external noise
transmission of high-speed signals over twisted-pair cables to sources or crosstalk.
work with the AD8131 or AD8132 drivers. Either can be
The AD8129 and AD8130 have a wide power supply range
used for analog or digital video signals and for high-speed
from single 5 V supply to ± 12 V, allowing wide common-mode
120 and differential-mode voltage ranges while maintaining signal
integrity. The wide common-mode voltage range will enable
110
the driver receiver pair to operate without isolation transform-
100 ers in many systems where the ground potential difference
90
between drive and receive locations is many volts. The AD8129
and AD8130 have considerable cost and performance improve-
CMRR – dB

80 ments over op amps and other multi-amplifier receiving solutions.


70 +VS
PD
60

50 VIN
VOUT
40

30
10k 100k 1M 10M 100M
FREQUENCY – Hz RG RF
Figure 1. AD8129 CMRR vs. Frequency
–VS
V OUT = VIN [1+(R F /R G )]

Figure 2. Typical Connection Configuration


REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD8129/AD8130–SPECIFICATIONS
5 V SPECIFICATIONS (AD8129 G = 10, AD8130 G = 1, TA = 25C, VS = 5 V, REF = 0 V, PD ≥ VIH, RL = 1 k, CL = 2 pF, unless
otherwise noted. TMIN to TMAX = –40C to +85C, unless otherwise noted.)
Model AD8129A AD8130A
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth VOUT ≤ 0.3 V p-p 175 200 240 270 MHz
VOUT = 2 V p-p 170 190 140 155 MHz
Bandwidth for 0.1 dB Flatness VOUT ≤ 0.3 V p-p, SOIC/µSOIC 30/50 45 MHz
Slew Rate VOUT = 2 V p-p, 25% to 75% 925 1060 950 1090 V/µs
Settling Time VOUT = 2 V p-p, 0.1% 20 20 ns
Rise and Fall Time VOUT ≤ 1 V p-p, 10% to 90% 1.7 1.4 ns
Output Overdrive Recovery 30 40 ns
NOISE/DISTORTION
Second Harmonic/Third Harmonic VOUT = 1 V p-p, 5 MHz –74/–84 –79/–86 dBc
VOUT = 2 V p-p, 5 MHz –68/–74 –74/–81 dBc
VOUT = 1 V p-p, 10 MHz –67/–81 –74/–80 dBc
VOUT = 1 V p-p, 10 MHz –61/–70 –74/–76 dBc
IMD VOUT = 2 V p-p, 10 MHz –67 –70 dBc
Output IP3 VOUT = 2 V p-p, 10 MHz 25 26 dBm
Input Voltage Noise (RTI) f ≥ 10 kHz 4.5 12.5 nV/√Hz
Input Current Noise (+IN, –IN) f ≥ 100 kHz 1 1 pA/√Hz
Input Current Noise (REF, FB) f ≥ 100 kHz 1.4 1.4 pA/√Hz
Differential Gain Error AD8130, G = 2, NTSC 200 IRE, R L ≥ 150 Ω 0.3 0.13 %
Differential Phase Error AD8130, G = 2, NTSC 200 IRE, R L ≥ 150 Ω 0.1 0.15 Degrees
INPUT CHARACTERISTICS
Common-Mode Rejection Ratio DC to 100 kHz, VCM = –3 V to +3.5 V 94 110 90 110 dB
VCM = 1 V p-p @ 2 MHz 80 80 dB
VCM = 1 V p-p @ 10 MHz 70 70 dB
CMRR with VOUT = 1 V p-p VCM = 2 V p-p @ 1 kHz, VOUT = ±0.5 V dc 100 83 dB
Common-Mode Voltage Range V+IN – V–IN = 0 V ±3.5 ±3.8 V
Differential Operating Range ±0.5 ±2.5 V
Differential Clipping Level ±0.6 ±0.75 ±0.85 ±2.3 ±2.8 ±3.3 V
Resistance Differential 1 6 MΩ
Common-Mode 4 4 MΩ
Capacitance Differential 3 3 pF
Common-Mode 4 4 pF
DC PERFORMANCE
Closed-Loop Gain Error VOUT = ± 1 V, RL ≥ 150 Ω ±0.4 ±1.5 ±0.15 ±0.6 %
TMIN to TMAX 20 10 ppm/°C
Open-Loop Gain VOUT = ±1 V 88 74 dB
Gain Nonlinearity VOUT = ±1 V 250 200 ppm
Input Offset Voltage 0.2 0.8 0.4 1.8 mV
TMIN to TMAX 2 10 µV/°C
TMIN to TMAX 1.4 3.5 mV
Input Offset Voltage vs. Supply +VS = +5 V, –VS = –4.5 V to –5.5 V –90 –84 –78 –74 dB
–VS = –5 V, +VS = +4.5 V to +5.5 V –94 –86 –80 –74 dB
Input Bias Current (+IN, –IN) ±0.5 ±2 ±0.5 ±2 µA
Input Bias Current (REF, FB) ±1 ±3.5 ±1 ±3.5 µA
TMIN to TMAX (+IN, –IN, REF, FB) 5 5 nA/°C
Input Offset Current (+IN, –IN, REF, FB) ±0.08 ±0.4 ±0.08 ±0.4 µA
TMIN to TMAX 0.2 0.2 nA/°C
OUTPUT PERFORMANCE
Voltage Swing RLOAD = 150 Ω/1 kΩ 3.6/4.0 3.6/4.0 ±V
Output Current 40 40 mA
Short Circuit Current To Common –60/+55 –60/+55 mA
TMIN to TMAX –240 –240 µA/°C
Output Impedance PD ≤ VIL, In Power-Down Mode 10 10 pF
POWER SUPPLY
Operating Voltage Range Total Supply Voltage ±2.25 ±12.6 ±2.25 ±12.6 V
Quiescent Supply Current 10.8 11.6 10.8 11.6 mA
TMIN to TMAX 36 36 µA/°C
PD ≤ VIL 0.68 0.85 0.68 0.85 mA
PD ≤ VIL, TMIN to TMAX 1 1 mA
PD PIN
VIH +VS – 1.5 +VS – 1.5 V
VIL +VS – 2.5 +VS – 2.5 V
IIH PD = Min VIH –30 –30 µA
IIL PD = Max VIL –50 –50 µA
Input Resistance PD ≤ +VS – 3 V 12.5 12.5 kΩ
PD ≥ +VS – 2 V 100 100 kΩ
Enable Time 0.5 0.5 µs

Specifications subject to change without notice.

–2– REV. 0
AD8129/AD8130
12 V SPECIFICATIONS (AD8129 G = 10, AD8130 G = 1, TA = 25C, VS = 12 V, REF = 0 V, PD ≥ VIH, RL = 1 k, CL = 2 pF,
unless otherwise noted. TMIN to TMAX = –40C to +85C, unless otherwise noted.)

Model AD8129A AD8130A


Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth VOUT ≤ 0.3 V p-p 175 200 250 290 MHz
VOUT = 2 V p-p 170 195 150 175 MHz
Bandwidth for 0.1 dB Flatness VOUT ≤ 0.3 V p-p, SOIC/µSOIC 50/70 110 MHz
Slew Rate VOUT = 2 V p-p, 25% to 75% 935 1070 960 1100 V/µs
Settling Time VOUT = 2 V p-p, 0.1% 20 20 ns
Rise and Fall Time VOUT ≤ 1 V p-p, 10% to 90% 1.7 1.4 ns
Output Overdrive Recovery 40 40 ns
NOISE/DISTORTION
Second Harmonic/Third Harmonic VOUT = 1 V p-p, 5 MHz –71/–84 –79/–86 dBc
VOUT = 2 V p-p, 5 MHz –65/–74 –74/–81 dBc
VOUT = 1 V p-p, 10 MHz –65/–82 –74/–80 dBc
VOUT = 2 V p-p, 10 MHz –59/–70 –74/–74 dBc
IMD VOUT = 2 V p-p, 10 MHz –67 –70 dBc
Output IP3 VOUT = 2 V p-p, 10 MHz 25 26 dBm
Input Voltage Noise (RTI) f ≥ 10 kHz 4.6 13 nV/√Hz
Input Current Noise (+IN, –IN) f ≥ 100 kHz 1 1 pA/√Hz
Input Current Noise (REF, FB) f ≥ 100 kHz 1.4 1.4 pA/√Hz
Differential Gain Error AD8130, G = 2, NTSC 200 IRE, R L ≥ 150 Ω 0.3 0.13 %
Differential Phase Error AD8130, G = 2, NTSC 200 IRE, R L ≥ 150 Ω 0.1 0.2 Degrees
INPUT CHARACTERISTICS
Common-Mode Rejection Ratio DC to 100 kHz, V CM = ± 10 V 92 105 88 105 dB
VCM = 1 V p-p @ 2 MHz 80 80 dB
VCM = 1 V p-p @ 10 MHz 70 70 dB
CMRR with VOUT = 1 V p-p VCM = 4 V p-p @ 1 kHz, VOUT = ±0.5 V dc 93 80 dB
Common-Mode Voltage Range V+IN – V–IN = 0 V ± 10.3 ± 10.5 V
Differential Operating Range ± 0.5 ± 2.5 V
Differential Clipping Level ± 0.6 ± 0.75 ± 0.85 ± 2.3 ± 2.8 ± 3.3 V
Resistance Differential 1 6 MΩ
Common-Mode 4 4 MΩ
Capacitance Differential 3 3 pF
Common-Mode 4 4 pF
DC PERFORMANCE
Closed-Loop Gain Error VOUT = ± 1 V, RL ≥ 150 Ω ± 0.8 ± 1.8 ± 0.15 ± 0.6 %
TMIN to TMAX 20 10 ppm/°C
Open-Loop Gain VOUT = ± 1 V 87 73 dB
Gain Nonlinearity VOUT = ± 1 V 250 200 ppm
Input Offset Voltage 0.2 0.8 0.4 1.8 mV
TMIN to TMAX 2 10 µV/°C
TMIN to TMAX 1.4 3.5 mV
Input Offset Voltage vs. Supply +VS = +12 V, –VS = –11.0 V to –13.0 V –88 –82 –77 –70 dB
–VS = –12 V, +V S = +11.0 V to +13.0 V –92 –84 –88 –70 dB
Input Bias Current (+IN, –IN) ± 0.25 ±2 ± 0.25 ±2 µA
Input Bias Current (REF, FB) ± 0.5 ± 3.5 ± 0.5 ± 3.5 µA
TMIN to TMAX (+IN, –IN, REF, FB) 2.5 2.5 nA/°C
Input Offset Current (+IN, –IN, REF, FB) ± 0.08 ± 0.4 ± 0.08 ± 0.4 µA
TMIN to TMAX 0.2 0.2 nA/°C
OUTPUT PERFORMANCE
Voltage Swing RLOAD = 700 Ω ±10.8 ±10.8 V
Output Current 40 40 mA
Short Circuit Current To Common –60/+55 –60/+55 mA
TMIN to TMAX –240 –240 µA/°C
Output Impedance PD ≤ VIL, In Power-Down Mode 10 10 pF
POWER SUPPLY
Operating Voltage Range Total Supply Voltage ±2.25 ±12.6 ±2.25 ±12.6 V
Quiescent Supply Current 13 13.9 13 13.9 mA
TMIN to TMAX 43 43 µA/°C
PD ≤ VIL 0.73 0.9 0.73 0.9 mA
PD ≤ VIL, TMIN to TMAX 1.1 1.1 mA
PD PIN
VIH +VS – 1.5 +VS – 1.5 V
VIL +VS – 2.5 +VS – 2.5 V
IIH PD = Min V IH –30 –30 µA
IIL PD = Max V IL –50 –50 µA
Input Resistance PD ≤ +VS – 3 V 3 3 kΩ
PD ≥ +VS – 2 V 100 100 kΩ
Enable Time 0.5 0.5 µs

Specifications subject to change without notice.

REV. 0 –3–
AD8129/AD8130–SPECIFICATIONS
5 V SPECIFICATIONS (AD8129 G = 10, AD8130 G = 1, TA = 25C, +VS = 5 V, –VS = 0 V, REF = 2.5 V, PD ≥ VIH, RL = 1 k, CL = 2 pF
unless otherwise noted. TMIN to TMAX = –40C to +85C, unless otherwise noted.)

Model AD8129A AD8130A


Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth VOUT ≤ 0.3 V p-p 160 185 220 250 MHz
VOUT = 1 V p-p 160 185 180 205 MHz
Bandwidth for 0.1 dB Flatness VOUT ≤ 0.3 V p-p, SOIC/µSOIC 25/40 25 MHz
Slew Rate VOUT = 2 V p-p, 25% to 75% 810 930 810 930 V/µs
Settling Time VOUT = 2 V p-p, 0.1% 20 20 ns
Rise and Fall Time VOUT ≤ 1 V p-p, 10% to 90% 1.8 1.5 ns
Output Overdrive Recovery 20 30 ns
NOISE/DISTORTION
Second Harmonic/Third Harmonic VOUT = 1 V p-p, 5 MHz –68/–75 –72/–79 dBc
VOUT = 2 V p-p, 5 MHz –62/–64 –65/–71 dBc
VOUT = 1 V p-p, 10 MHz –63/–70 –60/–62 dBc
VOUT = 2 V p-p, 10 MHz –56/–58 –68/–68 dBc
IMD VOUT = 2 V p-p, 10 MHz –67 –70 dBc
Output IP3 VOUT = 2 V p-p, 10 MHz 25 26 dBm
Input Voltage Noise (RTI) f ≥ 10 kHz 4.5 12.3 nV/√Hz
Input Current Noise (+IN, –IN) f ≥ 100 kHz 1 1 pA/√Hz
Input Current Noise (REF, FB) f ≥ 100 kHz 1.4 1.4 pA/√Hz
Differential Gain Error AD8130, G = 2, NTSC 100 IRE, R L ≥ 150 Ω 0.3 0.13 %
Differential Phase Error AD8130, G = 2, NTSC 100 IRE, R L ≥ 150 Ω 0.1 0.15 Degrees
INPUT CHARACTERISTICS
Common-Mode Rejection Ratio DC to 100 kHz, V CM = 1.5 V to 3.5 V 86 96 86 96 dB
VCM = 1 V p-p @ 1 MHz 80 80 dB
VCM = 1 V p-p @ 10 MHz 70 70 dB
CMRR with VOUT = 1 V p-p VCM = 1 V p-p @ 1 kHz, VOUT = ±0.5 V dc 80 72 dB
Common-Mode Voltage Range V+IN – V–IN = 0 V 1.25 to 3.7 1.25 to 3.8 V
Differential Operating Range ± 0.5 ± 2.5 V
Differential Clipping Level ± 0.6 ± 0.75 ± 0.85 ± 2.3 ± 2.8 ± 3.3 V
Resistance Differential 1 6 MΩ
Common-Mode 4 4 MΩ
Capacitance Differential 3 3 pF
Common-Mode 4 4 pF
DC PERFORMANCE
Closed-Loop Gain Error VOUT = ± 1 V, RL ≥ 150 Ω ± 0.25 ± 1.25 ± 0.1 ± 0.6 %
TMIN to TMAX 20 20 ppm/°C
Open-Loop Gain VOUT = ± 1 V 86 71 dB
Gain Nonlinearity VOUT = ± 1 V 250 200 ppm
Input Offset Voltage 0.2 0.8 0.4 1.8 mV
TMIN to TMAX 2 10 µV/°C
TMIN to TMAX 1.4 3.5 mV
Input Offset Voltage vs. Supply +VS = 5 V, –VS = –0.5 V to +0.5 V –88 –80 –74 –70 dB
–VS = 0 V, +VS = +4.5 V to +5.5 V –100 –86 –90 –76 dB
Input Bias Current (+IN, –IN) ± 0.5 ±2 ± 0.5 ±2 µA
Input Bias Current (REF, FB) ±1 ± 3.5 ±1 ± 3.5 µA
TMIN to TMAX (+IN, –IN, REF, FB) 5 5 nA/°C
Input Offset Current (+IN, –IN, REF, FB) ± 0.08 ± 0.4 ± 0.08 ± 0.4 µA
TMIN to TMAX 0.2 0.2 nA/°C
OUTPUT PERFORMANCE
Voltage Swing RLOAD ≥ 150 Ω 1.1 3.9 1.1 3.9 V
Output Current 35 35 mA
Short Circuit Current To Common –60/+55 –60/+55 mA
TMIN to TMAX –240 –240 µA/°C
Output Impedance PD ≤ VIL, In Power-Down Mode 10 10 pF
POWER SUPPLY
Operating Voltage Range Total Supply Voltage ±2.25 ±12.6 ±2.25 ±12.6 V
Quiescent Supply Current 9.9 10.6 9.9 10.6 mA
TMIN to TMAX 33 33 µA/°C
PD ≤ VIL 0.65 0.85 0.65 0.85 mA
PD ≤ VIL, TMIN to TMAX 1 1 mA
PD PIN
VIH +VS – 1.5 +VS – 1.5 V
VIL +VS – 2.5 +VS – 2.5 V
IIH PD = Min VIH –30 –30 µA
IIL PD = Max VIL –50 –50 µA
Input Resistance PD ≤ +VS – 3 V 12.5 12.5 kΩ
PD ≥ +VS – 2 V 100 100 kΩ
Enable Time 0.5 0.5 µs

Specifications subject to change without notice.

–4– REV. 0
AD8129/AD8130
ABSOLUTE MAXIMUM RATINGS 1, 2 2.0
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V

MAXIMUM POWER DISSIPATION – Watts


TJ (MAX) = 150C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . Refer to Figure 3 8-LEAD SOIC
Input Voltage (Any Input) . . . . . . . –VS – 0.3 V to +VS + 0.3 V 1.5
PACKAGE

Differential Input Voltage (AD8129)3 VS ≥ ± 11.5 V . . . ± 0.5 V


Differential Input Voltage (AD8129)3 VS < ± 11.5 V . . . ± 6.2 V
Differential Input Voltage (AD8130) . . . . . . . . . . . . . . ± 8.4 V 1.0
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C 8-LEAD
MICRO_SO
NOTES 0.5
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating 0
conditions for extended periods may affect device reliability. –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
2 AMBIENT TEMPERATURE – C
Thermal Resistance measured on SEMI standard 4-layer board.
8-Lead SOIC: θJA= 121°C/W; 8-Lead Micro_SO: θJA = 142°C/W
3
Refer to Applications section, Extreme Operating Condition, and Power Dissipation. Figure 3. Maximum Power Dissipation vs. Temperature

CONNECTION DIAGRAM
(Top View)
SO-8 (R) and Micro_SO-8 (RM)
AD8129/
AD8130
+IN 1 8 –IN

–VS 2
+ 7 +VS

PD 3 6 OUT

REF 4 5 FB

ORDERING GUIDE

Temperature Package Package Branding


Model Range Description Option Information
AD8129AR –40ºC to +85ºC 8-Lead SOIC SO-8
AD8129AR-REEL1 –40ºC to +85ºC 8-Lead SOIC 13" Tape and Reel
AD8129AR-REEL72 –40ºC to +85ºC 8-Lead SOIC 7" Tape and Reel
AD8129ARM –40ºC to +85ºC 8-Lead Micro_SO RM-8 HQA
AD8129ARM-REEL3 –40ºC to +85ºC 8-Lead Micro_SO 13" Tape and Reel HQA
AD8129ARM-REEL72 –40ºC to +85ºC 8-Lead Micro_SO 7" Tape and Reel HQA
AD8129-EVAL Evaluation Board with SOIC
AD8130AR –40ºC to +85ºC 8-Lead SOIC SO-8
AD8130AR-REEL1 –40ºC to +85ºC 8-Lead SOIC 13" Tape and Reel
AD8130AR-REEL72 –40ºC to +85ºC 8-Lead SOIC 7" Tape and Reel
AD8130ARM –40ºC to +85ºC 8-Lead Micro_SO RM-8 HPA
AD8130ARM-REEL3 –40ºC to +85ºC 8-Lead Micro_SO 13" Tape and Reel HPA
AD8130ARM-REEL72 –40ºC to +85ºC 8-Lead Micro_SO 7" Tape and Reel HPA
AD8130-EVAL Evaluation Board with SOIC
NOTES
1
13" Reel of 2500 each.
2
7" Reel of 1000 each.
3
13" Reel of 3000 each.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the AD8129/AD8130 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
ESD SENSITIVE DEVICE
are recommended to avoid performance degradation or loss of functionality.

REV. 0 –5–
AD8129/AD8130
AD8130 Frequency Response Characteristics
(G = 1, RL = 1 k, CL = 2 pF, VOUT = 0.3 V p-p, TA = 25C, unless otherwise noted.)
3 3 3
VOUT = 0.3V p-p VS = 2.5V VOUT = 1V p-p VS = 2.5V VOUT = 2V p-p
2 2 2
VS = 2.5V
1 1 1

0 0 0
VS = 5V VS = 5V
GAIN – dB

GAIN – dB
–1 –1

GAIN – dB
–1
VS = 12V VS = 5V
VS = 12V
–2 –2 –2 VS = 12V
–3 –3 –3

–4 –4 –4

–5 –5 –5

–6 –6 –6

–7 –7 –7
1 10 100 400 1 10 100 300 1 10 100 300
FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz

TPC 1. AD8130 Frequency Response TPC 2. AD8130 Frequency Response TPC 3. AD8130 Frequency Response
vs. Supply, VOUT = 0.3 V p-p vs. Supply, VOUT = 1 V p-p vs. Supply, VOUT = 2 V p-p

6 0.7 0.5
VS = 5V CL = 20pF RL = 1k VS = 2.5V RL = 150 VS = 2.5V
5 0.6 0.4

4 CL = 10pF 0.5 0.3


VS = 5V
3 0.4 0.2
CL = 5pF VS = 5V
GAIN – dB

GAIN – dB
0.1
GAIN – dB

0.3

1 0.2 0.0
0 0.1 –0.1
VS = 12V
–1 0.0 –0.2
CL = 2pF
–2 –0.1 –0.3
VS = 12V
–3 –0.2 –0.4
–4 –0.3 –0.5
1 10 100 300 1 10 100 300 1 10 100 300
FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz

TPC 4. AD8130 Frequency Response TPC 5. AD8130 Fine Scale Response TPC 6. AD8130 Fine Scale Response
vs. Load Capacitance vs. Supply, RL = 1 kΩ vs. Supply, RL = 150 Ω

3 3 3
RL = 150 G=2 G=2
2 VS = 2.5V 2 VOUT = 0.3V p-p 2 VOUT = 2V p-p
VS = 2.5V VS = 2.5V
1 1 1
0 0 0
VS = 5V
GAIN – dB

–1
GAIN – dB

–1 VS = 5V
GAIN – dB

–1 VS = 5V
–2 –2 –2
VS = 12V VS = 12V VS = 12V
–3 –3 –3
–4 –4 –4
–5 –5 –5
–6 –6 –6
–7 –7 –7
1 10 100 400 1 10 100 300 1 10 100 300
FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz

TPC 7. AD8130 Frequency Response TPC 8. AD8130 Frequency Response TPC 9. AD8130 Frequency Response
vs. Supply, RL = 150 Ω vs. Supply, G = 2, VOUT = 0.3 V p-p vs. Supply, G = 2, VOUT = 2 V p-p

–6– REV. 0
AD8129/AD8130
3 0.3 0.3
G=2 VS = 2.5V G=2
2 RF = RG = 1k 0.2 RL = 1k 0.2 RL = 150
RF = RG = 750 VS = 2.5V
1 0.1 0.1

0 0 0
RF = RG = 499
GAIN – dB

GAIN – dB
–1 –0.1

GAIN – dB
–0.1
VS = 5V VS = 5V
–2 –0.2 –0.2
RF = RG = 250 VS = 12V
–3 –0.3 –0.3
VS = 12V
–4 –0.4 –0.4
G=2
–5 VS = 5V –0.5 –0.5

–6 –0.6 –0.6

–7 –0.7 –0.7
1 10 100 300 1 10 100 1 10 100
FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz

TPC 10. AD8130 Frequency TPC 11. AD8130 Fine Scale Response TPC 12. AD8130 Fine Scale Response
Response for Various RF /RG vs. Supply, G = 2, RL = 1 kΩ vs. Supply, G = 2, RL = 150 Ω

3 0.3 3
G=2 VOUT = 2V p-p VOUT = 2V p-p
2 RL = 150 0.2 2
VS = 2.5V VS = 5V
1 VS = 2.5V 0.1 1

0 0 0
VS = 5V
G=5
GAIN – dB

–0.1
GAIN – dB

–1

GAIN – dB
VS = 12V –1
VS = 12V VS = 12V
–2 –0.2 –2
VS = 2.5V VS = 5V, 12V
–3 –0.3 –3
G=5
VS = 2.5V
–4 –0.4 –4
VS = 5V, 12V
–5 –0.5 –5
G = 10
–6 –0.6 G = 10 –6

–7 –0.7 –7
1 10 100 300 0.1 1 10 30 0.1 1 10 100
FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz

TPC 13. AD8130 Frequency Response TPC 14. AD8130 Fine Scale Response TPC 15. AD8130 Frequency Response
vs. Supply, G = 2, RL = 150 Ω vs. Supply, G = 5, G = 10, VOUT = 2 V p-p vs. Supply, G = 5, G = 10, VOUT = 2 V p-p

3 12
RL = 150 0dB = 1V RMS 1 TEK P6245
2 6 FET PROBE
50 8
1 VS = 5V, 12V 0 6
OUTPUT VOLTAGE – dBV

–6 4
0
RL CL
–12 5
GAIN – dB

–1
G = 10 G=5
–2 –18 RG RF
VS = 2.5V
–3 –24
VS = 5V, 12V
–4 –30
G RF RG
–5 –36 1 0 –
2 499 499
–6 –42 5 8.06k 2k
VS = 5V
10 4.99k 549
–7 –48
0.1 1 10 100 10 100 400
FREQUENCY – MHz FREQUENCY – MHz

TPC 16. AD8130 Frequency Response TPC 17. AD8130 Frequency Response TPC 18. AD8130 Basic Frequency
vs. Supply, G = 5, G = 10, RL = 150 Ω for Various Output Levels Response Test Circuit

REV. 0 –7–
AD8129/AD8130
AD8129 Frequency Response Characteristics
(G = 10, RL = 1 k, CL = 2 pF, VOUT = 0.3 V p-p, TA = 25C, unless otherwise noted.)
3 3 3
VOUT = 0.3V p-p VOUT = 1V p-p VS = 5V VOUT = 2V p-p
2 VS = 5V 2 2
VS = 2.5V VS = 2.5V VS = 2.5V
1 1 1

0 0 0
VS = 5V

GAIN – dB
–1

GAIN – dB
–1
GAIN – dB

–1 VS = 12V VS = 12V VS = 12V


–2 –2 –2

–3 –3 –3

–4 –4 –4

–5 –5 –5

–6 –6 –6

–7 –7 –7
1 10 100 300 1 10 100 300 1 10 100 300
FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz

TPC 19. AD8129 Frequency Response TPC 20. AD8129 Frequency Response TPC 21. AD8129 Frequency Response
vs. Supply, VOUT = 0.3 V p-p vs. Supply, VOUT = 1 V p-p vs. Supply, VOUT = 2 V p-p

4 0.5 0.3
VS = 5V CL = 20pF RL = 1k VS = 2.5V RL = 150 VS = 2.5V
3 CL = 10pF 0.4 0.2

2 CL = 5pF 0.3 VS = 5V 0.1


CL = 2pF
1 0.2 0
VS = 5V
GAIN – dB

GAIN – dB

0 0.1

GAIN – dB
–0.1

–1 0 –0.2
VS = 12V VS = 12V
–2 –0.1 –0.3

–3 –0.2 –0.4

–4 –0.3 –0.5
–5 –0.4 –0.6
–6 –0.5 –0.7
1 10 100 300 1 10 100 300 1 10 100 300
FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz

TPC 22. AD8129 Frequency Response TPC 23. AD8129 Fine Scale Response TPC 24. AD8129 Fine Scale Response
vs. Load Capacitance vs. Supply, RL = 1 kΩ vs. Supply, RL = 150 Ω

3 3 3
RL = 150 G = 20 G = 20
2 2 VOUT = 0.3V p-p 2 VOUT = 2V p-p
VS = 2.5V
1 1 1

0 0 0 VS = 5V, 12V
VS = 5V, 12V
GAIN – dB

–1
GAIN – dB

–1 –1
GAIN – dB

VS = 5V
–2 –2 –2
VS = 12V
–3 –3 –3

–4 –4 –4 VS = 2.5V
VS = 2.5V
–5 –5 –5

–6 –6 –6

–7 –7 –7
10 100 300 1 10 100 300 1 10 100 300
FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz

TPC 25. AD8129 Frequency Response TPC 26. AD8129 Frequency Response TPC 27. AD8129 Frequency Response
vs. Supply, RL = 150 Ω vs. Supply, G = 20, VOUT = 0.3 V p-p vs. Supply, G = 20, VOUT = 2 V p-p

–8– REV. 0
AD8129/AD8130
0.8 0.2 0.3
2k/221 G = 20 G = 20
G = 10
0.6 0.1 RL = 1k
VS = 5V 0.2 RL = 150
909/100
0.4 0
0.1
499/54.9 VS = 5V VS = 5V, 12V
0.2 –0.1 0
SOIC
GAIN – dB

0 –0.2

GAIN – dB

GAIN – dB
–0.1
–0.2 –0.3 –0.2
499/54.9 VS = 12V
0.2 909/100 –0.4 –0.3
SOIC
0 –0.5 –0.4
VS = 2.5V VS = 2.5V
–0.2 2k/221 –0.6 –0.5
–0.4 –0.7 –0.6
–0.6 –0.8 –0.7
1 10 100 300 1 10 30 0.1 1 10 30
FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz

TPC 28. AD8129 Fine Scale Response TPC 29. AD8129 Fine Scale Response TPC 30. AD8129 Fine Scale Response
vs. SOIC and µ SOIC for Various RF /RG vs. Supply vs. Supply

3 0.2 3
G = 20 VOUT = 2V p-p VOUT = 2V p-p
2 RL = 150 0.1 2
1 VS = 12V
0 1
0 –0.1 0
G = 100 G = 50
GAIN – dB

–1

GAIN – dB
–1 G = 50
GAIN – dB

VS = 5V, 12V –0.2 G = 100


VS = 2.5V
–2 –0.3 –2
–3 –0.4 VS = 5V –3
VS = 2.5V
–4 –0.5 –4
VS = 2.5V VS = 5V
–5 –0.6 VS = 12V –5
VS = 12V
–6 –0.7 –6
–7 –0.8 –7
1 10 100 300 0.1 1 10 0.1 1 10 50
FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz

TPC 31. AD8129 Frequency Response TPC 32. AD8129 Fine Scale Response TPC 33. AD8129 Frequency Response
vs. Supply, G = 20, RL = 150 Ω vs. Supply, G = 50, G = 100, vs. Supply, G = 50, G = 100,
VOUT = 2 V p-p VOUT = 2 V p-p

3 12
RL = 150 0dB = 1V RMS
2 6 1 TEK P6245
FET PROBE
1 0 50 8
OUTPUT VOLTAGE – dBV

6
0 –6 4
RL CL
GAIN – dB

–1 –12 5
G = 100 G = 50
–2 –18
RG RF
–3 VS = 2.5V –24

–4 –30
VS = 5V
G RF RG
–5 VS = 12V –36
10 2k 221
–6 –42 20 2k 105
VS = 5V 50 2k 41.2
–7 –48 100 2k 20
0.1 1 10 50 10 100 400
FREQUENCY – MHz FREQUENCY – MHz

TPC 34. AD8129 Frequency Response TPC 35. AD8129 Frequency Response TPC 36. AD8129 Basic Frequency
vs. Supply, G = 50, G = 100, for Various Output Levels Response Test Circuit
RL = 150 Ω

REV. 0 –9–
AD8129/AD8130
AD8130 Harmonic Distortion Characteristics
(RL = 1 k, CL = 2 pF, TA = 25C, unless otherwise noted.)
–60 –54 –55
VOUT = 1V p-p VOUT = 2V p-p
fC = 5MHz VS = 12V
–61 VS = 5V
–66 –60 G=1
VS = 5V
VS = 12V
–67
G=1

HD2 – dBc

HD2 – dBc
–66
HD2 – dBc

–72

–73

–78 –72
G=1
–79
VS = 12V
VS = 12V VS = 5V
–78 G=1 G=2 VS = 5V
–84
VS = 12V VS = 12V –85
G=2 G=2
VS = 5V
–90 –84 –91
1 10 40 1 10 40 0.5 1 10
FREQUENCY – MHz FREQUENCY – MHz VOUT – V p-p

TPC 37. AD8130 Second Harmonic TPC 38. AD8130 Second Harmonic TPC 39. AD8130 Second Harmonic
Distortion vs. Frequency Distortion vs. Frequency Distortion vs. Output Voltage

–51 –45 –46


VOUT = 1V p-p G=1 VOUT = 2V p-p G = 2, VS = 12V fC = 5MHz
–57 VS = 5V –51 –52
G=1 G = 2, VS = 5V VS = 12V
VS = 12V
–63 –57 –58
VS = 5V
–69 –63 –64

HD3 – dBc
HD3 – dBc

HD3 – dBc

–75 –69 –70


VS = 12V G=1 G=2
VS = 5V
–81 VS = 12V –75 VS = 5V –76
G=1 G=1 VS = 12V
–87 –81 –82
VS = 5V
–93 –87 –88
G=2 G=2
–99 –93 –94
1 10 40 1 10 40 0.5 1 10
FREQUENCY – MHz FREQUENCY – MHz VOUT – V p-p

TPC 40. AD8130 Third Harmonic TPC 41. AD8130 Third Harmonic TPC 42. AD8130 Third Harmonic
Distortion vs. Frequency Distortion vs. Frequency Distortion vs. Output Voltage

–43 –42 –46


VS = 2.5V VS = 2.5V VS = 2.5V G = 2, HD3
–48 –52 fC = 5MHz
–49 G = 1, HD3
–54 –58
G=1
–55 –60
VOUT = 2V p-p –64 G = 1, HD2
VOUT = 2V p-p
HD2 – dBc

HD3 – dBc

HD – dBc

–66 G = 2, HD2
–61 G=2 –70
G=2 G = 2, HD2
–72
G=1 –76
–67 –78
G=1 –82
–84 G = 2, HD3
–73 G=2
G=1 –88
VOUT = 1V p-p –90
VOUT = 1V p-p
G=2
–79 –96 –94
1 10 40 1 10 40 0 0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY – MHz FREQUENCY – MHz VOUT – V p-p

TPC 43. AD8130 Second Harmonic TPC 44. AD8130 Third Harmonic TPC 45. AD8130 Harmonic Distortion
Distortion vs. Frequency Distortion vs. Frequency vs. Output Voltage

–10– REV. 0
AD8129/AD8130
AD8129 Harmonic Distortion Characteristics
(RL = 1 k, CL = 2 pF, TA = 25C, unless otherwise noted.)
–51 –42 –50
VOUT = 1V p-p VOUT = 2V p-p fC = 5MHz

–57 –48
–56
G = 10
–54
–63 G = 10, –62
G = 10, VS = 12V G = 10,

HD2 – dBc
HD2 – dBc

HD2 – dBc
VS = 12V –60 VS = 12V
G = 20
–69 G = 20, –68
G = 10, –66 VS = 12V G = 10,
VS = 5V VS = 5V
–75 –74
G = 20, –72
VS = 12V G = 10, G = 20,
VS = 5V VS = 5V
–81 –80
–78
G = 20, G = 20, G = 20,
VS = 5V VS = 5V VS = 12V
–87 –84 –86
1 10 40 1 10 40 0.5 1 10
FREQUENCY – MHz FREQUENCY – MHz VOUT – V p-p

TPC 46. AD8129 Second Harmonic TPC 47. AD8129 Second Harmonic TPC 48. AD8129 Second Harmonic
Distortion vs. Frequency Distortion vs. Frequency Distortion vs. Output Voltage

–54 –45 –48


VOUT = 1V p-p VOUT = 2V p-p G = 10,
G = 10, fC = 5MHz G = 10,
–60 VS = 5V –51 VS = 5V –54 VS = 12V
G = 10,
G = 10, –60 VS = 5V
–66 –57
VS = 12V G = 10,
VS = 12V
–66
HD3 – dBc

HD3 – dBc

HD3 – dBc
–72 –63
G = 10, –72
–78 –69 VS = 12V
G = 20,
–78
VS = 5V
–84 –75 G = 20,
G = 20, –84
G = 10, VS = 5V VS = 5V
–90 G = 20,
–81 VS = 5V
G = 20, –90 G = 20,
VS = 12V VS = 12V VS = 12V
–96 –87 –96
1 10 40 1 10 40 0.5 1 10
FREQUENCY – MHz FREQUENCY – MHz VOUT – V p-p

TPC 49. AD8129 Third Harmonic TPC 50. AD8129 Third Harmonic TPC 51. AD8129 Third Harmonic
Distortion vs. Frequency Distortion vs. Frequency Distortion vs. Output Voltage

–44 –42 –50


VS = 2.5V VS = 2.5V VOUT = 2V p-p VS = 2.5V
VOUT = 2V p-p –48 fC = 5MHz
–50 –56
–54
–56 –62
–60 G = 20 G = 20
HD3 – dBc
HD2 – dBc

G = 20
HD – dBc

HD3 HD2
–62 –66 –68
G = 10
G = 20 VOUT = 1V p-p VOUT = 1V p-p
HD2
–72
–68 –74
G = 10
–78 G = 10
HD3
–74 –80
–84
G = 10
–80 –90 –86
1 10 40 1 10 40 0 0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY – MHz FREQUENCY – MHz VOUT – V p-p

TPC 52. AD8129 Second Harmonic TPC 53. AD8129 Third Harmonic TPC 54. AD8129 Harmonic Distor-
Distortion vs. Frequency Distortion vs. Frequency tion vs. Output Voltage

REV. 0 –11–
AD8129/AD8130
–39 –61 –50
G=1 G=1 VOUT = 1V p-p G=1 VOUT = 2V p-p
VOUT = 2V p-p fC = 5MHz
–45 fC = 5MHz
VS = 5V –67 –56
HD2
–51 RL = 1k VS = 2.5V HD2
fC = 5MHz VS = 2.5V

DISTORTION – dBc
DISTORTION – dBc

DISTORTION – dBc
–73 –62
–57 HD2
VS = 5V, 12V
–63 –79 –68 HD2
HD3 VS = 5V, 12V
VS = 5V
–69
–85 –74
HD2 HD3
–75
VS = 12V HD3
–91 –80 VS = 2.5V
–81 HD3 HD3 HD3
VS = 2.5V VS = 5V, 12V
–87 –97 –86
–5 –4 –3 –2 –1 0 1 2 3 4 5 100 1k 100 1k
VCM – V RL –  RL – 

TPC 55. AD8130 Harmonic Distortion TPC 56. AD8130 Harmonic Distortion TPC 57. AD8130 Harmonic Distortion
vs. Common-Mode Voltage vs. Load Resistance vs. Load Resistance

–36 –48 –44


G = 10 G = 10 G = 10 VOUT = 2V p-p
VOUT = 1V p-p
VOUT = 2V p-p fC = 5MHz fC = 5MHz
–42 –54
VS = 5V –50
RL = 1k VS = 2.5V VS = 2.5V
–48 fC = 5MHz –60 VS = 12V VS = 12V
DISTORTION – dBc

DISTORTION – dBc
DISTORTION – dBc

HD2 –56
VS = 5V VS = 5V
–54 –66
–62
–60 VS = 12V
–72 VS = 2.5V
VS = 5V
–68
–66 –78
HD2 HD3 VS = 12V
HD3
–72 –74
HD3 –84
VS = 2.5V
VS = 5V
–78 –90 –80
–5 –4 –3 –2 –1 0 1 2 3 4 5 100 1k 100 1k
VCM – V RL –  RL – 

TPC 58. AD8129 Harmonic Distortion TPC 59. AD8129 Harmonic Distortion TPC 60. AD8129 Harmonic Distortion
vs. Common-Mode Voltage vs. Load Resistance vs. Load Resistance

VCM 100 100


CURRENT NOISE – pA/ Hz

VOLTAGE NOISE – nV/ Hz

200

10
1:2
RL AD8130
CL 10

RG RF AD8129
1.0

G RF RG
1 0 –
MINI CIRCUITS:
2 499 499
# T4 – 6T, fC ⱕ 10MHz
10 2k 221
# TC4 – 1W, fC ⬎ 10MHz 0.1 1.0
20 2k 105
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz FREQUENCY – Hz

TPC 61. AD8129/AD8130 Basic Distor- TPC 62. AD8129/AD8130 Input TPC 63. AD8129/AD8130 Input
tion Test Circuit, VCM = 0 V Unless Current Noise vs. Frequency Voltage Noise vs. Frequency
Otherwise Noted

–12– REV. 0
AD8129/AD8130
–30 0 0
–40 –10 –10
COMMON-MODE REJECTION – dB

POWER SUPPLY REJECTION – dB


POWER SUPPLY REJECTION – dB
–50 –20 –20
–30 –30
–60
–40 –40
–70
–50 –50
–80
–60 –60
VS = 2.5V VS = 2.5V
–90
–70 VS = 12V –70
–100
–80 –80
VS = 5V, 12V VS = 5V
–110 –90 –90
VS = 2.5V VS = 5V VS = 12V
–120 –100 –100
10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

TPC 64. AD8130 Common-Mode TPC 65. AD8130 Positive Power TPC 66. AD8130 Negative Power
Rejection vs. Frequency Supply Rejection vs. Frequency Supply Rejection vs. Frequency

–30 0 0

–40 –10 –10


COMMON-MODE REJECTION – dB

POWER SUPPLY REJECTION – dB


POWER SUPPLY REJECTION – dB

–50 –20 –20

–30 –30
–60
–40 –40
–70
–50 –50
–80 VS = 2.5V
–60 –60
–90
–70 –70
VS = 12V VS = 5V
–100
–80 VS = 2.5V –80 V = 12V
S
–110 VS = 5V, 12V –90
–90
VS = 5V VS = 2.5V
–120 –100 –100
10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M
FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

TPC 67. AD8129 Common-Mode TPC 68. AD8129 Positive Power TPC 69. AD8129 Negative Power
Rejection vs. Frequency Supply Rejection vs. Frequency Supply Rejection vs. Frequency

80 90 100

70 180 80 180
GAIN GAIN 10
PHASE MARGIN – Degrees

60 70
OUTPUT IMPEDANCE – 
PHASE MARGIN – Degrees
OPEN-LOOP GAIN – dB
OPEN-LOOP GAIN – dB

50 135 60 135 VS = 5V


1
40 50

30 + PHASE 90 AD8130, G = 1
– VOUT
40
VOUT
PHASE 90 100m
20 + 30
1k 2pF 1k 2pF

10 45 20 45 10m
1k 1k 100 1k
0 10 φM = 56
VIN φM = 58 VIN
AD8129, G = 10
–10 0 0 0 1m
1k 10k 100k 1M 10M 100M 300M 1k 10k 100k 1M 10M 100M 300M 1k 10k 100k 1M 10M 100M
FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

TPC 70. AD8130 Open Loop Gain TPC 71. AD8129 Open Loop Gain TPC 72. Closed-Loop Output
and Phase vs. Frequency and Phase vs. Frequency Impedance vs. Frequency

REV. 0 –13–
AD8129/AD8130
AD8130 Transient Response Characteristics
(G = 1, RL = 1 k, CL = 2 pF, VS = 5 V, TA = 25C, unless otherwise noted.)
VOUT = 1V p-p VOUT = 1V p-p VOUT = 1V p-p
VS = 2.5V VS = 5V VS = 12V

250mV 5.00ns 250mV 5.00ns 250mV 5.00ns

TPC 73. AD8130 Transient Response, TPC 74. AD8130 Transient Response, TPC 75. AD8130 Transient Response,
VS = ± 2.5 V, VOUT = 1 V p-p VS = ± 5 V, VOUT = 1 V p-p VS = ± 12 V, VOUT = 1 V p-p

VS = 2.5V VOUT = 0.2V p-p VS = 2.5V VOUT = 1V p-p VS = 2.5V VOUT = 2V p-p
VS = 5V VS = 5V CL = 5pF VS = 5V CL = 5pF

VS = 12V VS = 12V
VS = 12V

50mV 5.00ns 250mV 5.00ns 500mV 5.00ns

TPC 76. AD8130 Transient Response TPC 77. AD8130 Transient Response TPC 78. AD8130 Transient Response
vs. Supply, VOUT = 0.2 V p-p vs. Supply, VOUT = 1 V p-p, CL = 5 pF vs. Supply, VOUT = 2 V p-p, CL = 5 pF

CL = 10pF VOUT = 0.2Vp-p


CL = 5pF
CL = 2pF 2V p-p 4V p-p

1V p-p 2V p-p

0.5V p-p 1V p-p

50mV 10.0ns 500mV 5.00ns 1.00V 5.00ns

TPC 79. AD8130 Transient Response TPC 80. AD8130 Transient Response TPC 81. AD8130 Transient Response
vs. Load Capacitance, VOUT = 0.2 V p-p vs. Output Amplitude, vs. Output Amplitude,
VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p VOUT = 1 V p-p, 2 V p-p, 4 V p-p

–14– REV. 0
AD8129/AD8130

VOUT = 1V p-p VOUT = 2V p-p VOUT = 8V p-p G=2


G=2 VS = 5V, CL = 10pF G=2 VS = 5V VS = 5V
CL = 10pF

VS = 5V, CL = 2pF VS = 12V


CL = 2pF

250mV 5.00ns 500mV 5.00ns 2.00V 5.00ns

TPC 82. AD8130 Transient Response TPC 83. AD8130 Transient Response TPC 84. AD8130 Transient Response
vs. Load Capacitance, VOUT = 1 V p-p, vs. Supply, VOUT = 2 V p-p, G = 2 vs. Load Capacitance, VOUT = 8 V p-p
G=2

G=2
VOUT = 10V p-p VS = 12V
VIN

VOUT VOUT

VIN

1.00V 5.00ns 2.50V 5.00ns


1.00V 5.00ns

TPC 85. AD8130 Transient Response TPC 86. AD8130 Transient Response TPC 87. AD8130 Transient Response,
with +3 V Common-Mode Input with –3 V Common-Mode Input VOUT = 10 V p-p, G = 2, VS = ± 12 V

G=5 G=5 VOUT = 20V p-p G=5


VS = 5V VOUT = 8V p-p VS = 5V VS = 12V
4V p-p CL = 10pF CL = 10pF
CL = 10pF
2V p-p

1V p-p

1.00V 10.0ns 2.00V 10.0ns 5.00V 10.0ns

TPC 88. AD8130 Transient Response TPC 89. AD8130 Transient Response, TPC 90. AD8130 Transient Response,
vs. Output Amplitude VOUT = 8 V p-p, G = 5, VS = ± 5 V VOUT = 20 V p-p, G = 5, VS = ± 12 V

REV. 0 –15–
AD8129/AD8130
AD8129 Transient Response Characteristics
(G = 10, RF = 2 k, RG = 221 , RL = 1 k, CL = 1 pF, VS = 5 V, TA = 25C, unless otherwise noted.)
VS = 2.5V VOUT = 1V p-p VS = 5V VOUT = 1V p-p VS = 12V VOUT = 1V p-p

250mV 5.00ns 250mV 5.00ns 250mV 5.00ns

TPC 91. AD8129 Transient Response, TPC 92. AD8129 Transient Response, TPC 93. AD8129 Transient Response,
VS = ± 2.5 V, VOUT = 1 V p-p VS = ± 5 V, VOUT = 1 V p-p VS = ± 12 V, VOUT = 1 V p-p

VS = 5V VOUT = 0.4V p-p VS = 5V VOUT = 1V p-p VS = 2.5V VOUT = 2V p-p
VS = 2.5V VS = 2.5V CL = 5pF VS = 5V CL = 5pF

VS = 12V VS = 12V VS = 12V

100mV 5.00ns 250mV 5.00ns 500mV 5.00ns

TPC 94. AD8129 Transient Response TPC 95. AD8129 Transient Response TPC 96. AD8129 Transient Response
vs. Supply, VOUT = 0.4 V p-p vs. Supply, VOUT = 1 V p-p, CL = 5 pF vs. Supply, VOUT = 2 V p-p, CL = 5 pF

CL = 5pF VOUT = 0.4V p-p


VO = 2V p-p VO = 4V p-p
CL = 10pF

VO = 1V p-p VO = 2V p-p
CL = 2pF
VO = 0.5V p-p VO = 1V p-p

100mV 5.00ns 500mV 5.00ns 1.00V 5.00ns

TPC 97. AD8129 Transient Response TPC 98. AD8129 Transient Response TPC 99. AD8129 Transient Response
vs. Load Capacitance, VOUT = 0.4 V p-p vs. Output Amplitude, vs. Output Amplitude,
VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p VOUT = 1 V p-p, 2 V p-p, 4 V p-p

–16– REV. 0
AD8129/AD8130

VOUT = 1V p-p G = 20 VOUT = 2V p-p G = 20 VOUT = 8V p-p G = 20


CL = 20pF CL = 20pF CL = 20pF

250mV 5.00ns 500mV 5.00ns 2.00V 5.00ns

TPC 100. AD8129 Transient Response, TPC 101. AD8129 Transient Response, TPC 102. AD8129 Transient Response,
VOUT = 1 V p-p, VS = ±2.5 V to ±12 V VOUT = 2 V p-p, VS = ±5 V VOUT = 8 V p-p, VS = ±5 V

VOUT = 10V p-p G = 20


VIN VS = 12V
CL = 20pF

VOUT

VOUT

VIN
1.00V 5.00ns 2.50V 5.00ns

TPC 103. AD8129 Transient Response TPC 104. AD8129 Transient Response TPC 105. AD8129 Transient Response,
with +3.5 V Common-Mode Input with –3.5 V Common-Mode Input VOUT = 10 V p-p, G = 20

G = 50 VOUT = 8V p-p G = 50 VOUT = 20V p-p G = 50


VS = 5V VS = 5V VS = 12V
4V p-p CL = 20pF CL = 10pF
CL = 20pF
2V p-p

1V p-p

1.00V 12.5ns 2.00V 12.5ns 5.00V 12.5ns

TPC 106. AD8129 Transient Response TPC 107. AD8129 Transient Response, TPC 108. AD8129 Transient Response,
vs. Output Amplitude, VOUT = 1 V p-p, VOUT = 8 V p-p, G = 50, VS = ±5 V VOUT = 20 V p-p, G = 50, VS = ± 12 V
2 V p-p, 4 V p-p

REV. 0 –17–
AD8129/AD8130
3.0
23 37 AD8130
G=1 G = 10
VS = 5V 2.0
VS = 10V
VOUT = 100mV AC @ 1kHz

DIFFERENTIAL INPUT – V
SUPPLY CURRENT – mA

SUPPLY CURRENT – mA
20 31
1.0

17 25 0.0 AD8129

–1.0
14 19
AD8130
–2.0
11 13
–5 –4 –3 –2 –1 0 1 2 3 4 5 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
–3.0
DIFFERENTIAL INPUT – V DIFFERENTIAL INPUT – V –50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE – C

TPC 109. AD8130 DC Power Supply TPC 110. AD8129 DC Power Supply TPC 111. AD8129/AD8130 Input
Current vs. Differential Input Voltage Current vs. Differential Input Voltage Differential Voltage Range vs. Tem-
perature, 1% Gain Compression

4
GAIN NONLINEARITY – 0.08%/DIV

G=1 G=1
VS = 5V VS = 5V 3
VS = 5V
GAIN NONLINEARITY –

RL = 1k RL = 1k
2
0.005%/DIV

VOUT – V
0

–1

–2

–3

–4
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 –5 –4 –3 –2 –1 0 1 2 3 4 5
OUTPUT VOLTAGE – V OUTPUT VOLTAGE – V DIFFERENTIAL INPUT – V

TPC 112. AD8130 Gain Nonlinearity, TPC 113. AD8130 Gain Nonlinearity, TPC 114. AD8130 Differential Input
VOUT = 2 V p-p VOUT = 5 V p-p Clipping Level

8
G = 10 G = 10
VS = 5V VS = 12V 6
VS = 10V
GAIN NONLINEARITY –

GAIN NONLINEARITY –

RL = 1k RL = 1k
OUTPUT VOLTAGE – V

4
0.005%/DIV

2
0.2%/DIV

–2

–4

–6

–8
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 –5 –4 –3 –2 –1 0 1 2 3 4 5 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
OUTPUT VOLTAGE – V OUTPUT VOLTAGE – V DIFFERENTIAL INPUT – V

TPC 115. AD8129 Gain Nonlinearity, TPC 116. AD8129 Gain Nonlinearity, TPC 117. AD8129 Differential Input
VOUT = 2 V p-p VOUT = 10 V p-p Clipping Level

–18– REV. 0
AD8129/AD8130
15 17 0.60 40
16

INPUT OFFSET CURRENT – nA


14 15

INPUT BIAS CURRENT – A


SUPPLY CURRENT – mA
SUPPLY CURRENT – mA

14 VS = 12V IB
13 VS = 5V 0.45 30
13 IOS

12 12

11
11 0.30 20
10 VS = 2.5V

9
10
8

9 7 0.15 10
0 5 10 15 20 25 30 –50 –35 –20 –5 10 25 40 55 70 85 100 –50 –35 –20 –5 10 25 40 55 70 85 100
TOTAL SUPPLY VOLTAGE – V TEMPERATURE – C TEMPERATURE – C

TPC 118. Quiescent Power Supply TPC 119. Quiescent Power Supply TPC 120. Input Bias Current and
Current vs. Total Supply Voltage Current vs. Temperature Input Offset Current vs. Temperature

4.00 4.00 11.0


3.75 3.75 10.5
3.50 AD8130 AD8130
3.50 AD8130 10.0
INPUT COMMON-MODE – V

INPUT COMMON-MODE – V

INPUT COMMON-MODE – V
AD8129
3.25 VS = 12V
3.25 9.5 AD8129
3.00 VS = 5V VS = 5V AD8129
2.75 3.00 9.0
2.50 VOUT = 100mV VOUT = 100mV VOUT = 100mV
2.75 8.5
AC AT 1kHz AC AT 1kHz AC AT 1kHz
2.25 –3.00 –9.0
2.00
–3.25 –9.5
1.75 AD8129 AD8130
AD8129 AD8130 –3.50 –10.0 AD8129 AD8130
1.50
1.25 –3.75 –10.5

1.00 –4.00 –11.0


–50 –35 –20 –5 10 25 40 55 70 85 100 –50 –35 –20 –5 10 25 40 55 70 85 100 –50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE – C TEMPERATURE – C TEMPERATURE – C

TPC 121. Common-Mode Voltage TPC 122. Common-Mode Voltage TPC 123. Common-Mode Voltage
Range vs. Temperature, Typical 1% Range vs. Temperature, Typical 1% Range vs. Temperature, Typical 1%
Gain Compression Gain Compression Gain Compression

4.0 4.0 11
VS = 5V VS = 5V VS = 12V

3.5 3.5 10
OUTPUT VOLTAGE – V
OUTPUT VOLTAGE – V

SOURCING
OUTPUT VOLTAGE – V

3.0 3.0 9
+100C –40C +25C
+100C –40C +25C +100C –40C +25C

2.0 –3.0 –9

SINKING
1.5 –3.5 –10
VOUT = 100mV VOUT = 100mV VOUT = 100mV
AC AT 1kHz AC AT 1kHz AC AT 1kHz
1.0 –4.0 –11
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
OUTPUT CURRENT – mA OUTPUT CURRENT – mA OUTPUT CURRENT – mA

TPC 124. Output Voltage Range vs. TPC 125. Output Voltage Range vs. TPC 126. Output Voltage Range vs.
Output Current, Typical 1% Gain Output Current, Typical 1% Gain Output Current, Typical 1% Gain
Compression Compression Compression

REV. 0 –19–
AD8129/AD8130
THEORY OF OPERATION Thus, the input dynamic ranges are limited to about 2.5 V for
The AD8129/AD8130 use an architecture called active feed- the AD8130 and 0.5 V for the AD8129 (see Specification
back which differs from that of conventional op amps. The section for more detail). For this and other reasons, it is not
most obvious differentiating feature is the presence of two sepa- recommended to reverse the input and feedback stages of the
rate pairs of differential inputs compared to a conventional op AD8129/AD8130, even though some apparently normal func-
amp’s single pair. Typically for the active-feedback architecture, tionality might be observed under some conditions.
one of these input pairs is driven by a differential input signal,
while the other is used for the feedback. This active stage in the A few simple circuits can illustrate how the active feedback
feedback path is where the term “active feedback” is derived. architecture of the AD8129/AD8130 operates.
The active feedback architecture offers several advantages over a Op Amp Configuration
conventional op amp in several types of applications. Among If only one of the input stages of the AD8129/AD8130 is used,
these are excellent common-mode rejection, wide input common- it will function very much like a conventional op amp. (See
mode range and a pair of inputs that are high-impedance and Figure 4.) Classical inverting and noninverting op amps circuits
totally balanced in a typical application. In addition, while an can be created, and the basic governing equations will be the
external feedback network establishes the gain response as same as for a conventional op amp. The unused input pins form
in a conventional op amp, its separate path makes it totally the second input and should be shorted together and tied to
independent of the signal input. This eliminates any interaction ground or some midsupply voltage when they are not used.
between the feedback and input circuits, which traditionally
+V
causes problems with CMRR in conventional differential-input
op amp circuits.
0.1F 10F
Another advantage is the ability to change the polarity of the
gain merely by switching the differential inputs. A high input- + PD +VS
impedance inverting amplifier can be made. Besides a high
input impedance, a unity-gain inverter with the AD8130 will VIN +
VOUT

have a noise gain of unity. This will produce lower output noise –VS
and higher bandwidth than op amps that have noise gain equal
RF
to 2 for a unity gain inverter.
The two differential input stages of the AD8129/AD8130 are each RG
transconductance stages that are well matched. These stages –V
0.1F 10F
convert the respective differential input voltages to internal
currents. The currents are then summed and converted to a
Figure 4. With both inputs grounded, the feedback stage
voltage, which is buffered to drive the output. The compensa-
functions like an op amp: VOUT = VIN (1 + RF/RG). NOTE: This
tion capacitor is in the summing circuit.
circuit is provided to demonstrate device operation. It is
When the feedback path is closed around the part, the output not suggested to use this circuit in place of an op amp.
will drive the feedback input to that voltage which causes the
With the unused pair of inputs shorted, there is no differential
internal currents to sum to zero. This occurs when the two
voltage between them. This dictates that the differential input
differential inputs are equal and opposite; that is, their algebraic
voltage of the used inputs will also be zero for closed-loop
sum is zero.
applications. Since this is the governing principle of conven-
In a closed-loop application, a conventional op amp will have its tional op amp circuits, an active feedback amplifier can function
differential input voltage driven to near zero under nontransient as a conventional op amp under these conditions.
conditions. The AD8129/AD8130 generally will have differential
Note that this circuit is presented only for illustration purposes,
input voltages at each of its input pairs, even under equilibrium
to show the similarities of the active feedback architecture func-
conditions. As a practical consideration, it is necessary to inter-
tionality to conventional op amp functionality. If it is desired to
nally limit the differential input voltage with a clamp circuit.
design a circuit that can be created from a conventional op amp,
it is recommended to choose a conventional op amp whose
specifications are better suited to that application. These op amp
principles are the basis for offsetting the output as described in
the Output Offset/Level Translator section.

–20– REV. 0
AD8129/AD8130
APPLICATIONS Twisted-Pair Cable, Composite Video Receiver with Equal-
Basic Gain Circuits ization Using an AD8130
The gain of the AD8129/AD8130 can be set with a pair of feed- The AD8130 has excellent common-mode rejection at its inputs.
back resistors. The basic configuration is shown in Figure 5. This makes it an ideal candidate for a receiver for signals that
The gain equation is the same as that of a conventional op amp: are transmitted over long distances on twisted-pair cables. Cat-
G = 1 + RF/RG. For unity gain applications using the AD8130, egory 5 type cables are now very common in office settings and
RF can be set to zero (short circuit), and RG can be removed. are extensively used for data transmission. These same cables
(See Figure 6.) The AD8129 is compensated to operate at gains can also be used for the analog transmission of signals like video.
of 10 and higher, so shorting the feedback path to obtain unity These long cables will pick up noise from the environment they
gain will cause oscillation. pass through. This noise will not favor one conductor over an-
other, and will therefore be a common-mode signal. A receiver
+V
that rejects the common-mode signal on the cable can greatly
AD8129/ enhance the signal-to-noise ratio performance of the link.
AD8130 0.1F 10F The AD8130 is also very easy to use as a differential receiver,
because the differential inputs and the feedback inputs are
+ PD +VS
VIN entirely separate. This means that there is no interaction of the
VOUT feedback network and the termination network as there would
+
–VS
be in conventional op amp-type receivers.
Another issue to be dealt with on long cables is the attenuation
RF
of the signal at longer distances. This attenuation is a function of
RG frequency and increases as roughly as the square root of frequency.
0.1F 10F
–V For good fidelity of video circuits, the overall frequency response
of the transmission channel should be flat versus frequency. Since
Figure 5. Basic Gain Circuit: VOUT = VIN (1 + RF/RG) the cable attenuates the high frequencies, a frequency-selective
boost circuit can be used to undo this effect. These circuits
are called equalizers.
+V
An equalizer uses frequency-dependent elements (Ls and Cs) in
AD8130
order to create a frequency response that is the opposite of the
0.1F 10F rest of the channel’s response in order to create an overall flat
response. There are many ways to create such circuits, but a
VIN
+ PD +VS common technique is to put the frequency-selective elements in
the feedback path of an op amp circuit. The AD8130 in particu-
VOUT
+ lar makes this easier than other circuits, because, once again, the
–VS feedback path is totally independent of the input path and there
is no interaction.
0.1F 10F The circuit in Figure 7 was developed as a receiver/equalizer for
transmitting composite video over 300 m of Category 5 cable. This
–V cable has an attenuation of approximately 20 dB at 10 MHz
for 300 m. At 100 MHz, the attenuation is approximately
Figure 6. An AD8130 with Unity Gain 60 dB. (See Figure 8.)
The input signal can be applied either differentially or single- +V
endedly—all that matters is the magnitude of the differential
signal between the two inputs. For single-ended input applica-
AD8130
tions, applying the signal to the +IN with –IN grounded will 0.1F 10F
create a noninverting gain, while reversing these connections
+ PD +VS
will create an inverting gain. Since the two inputs are high- VIN 100
impedance and matched, both of these conditions will provide VOUT
+
the same high input impedance. Thus, an advantage of the
–VS
active feedback architecture is the ability to make a high-input-
impedance, inverting op amp. If conventional op amps are used,
RF
a high impedance buffer followed by an inverting stage is needed. R1
RG 1k
100 0.1F 10F
This requires two op amps. 499 –V
C1
200pF

Figure 7. An Equalizer Circuit for Composite Video


Transmission over 300 m of Category 5 Cable

REV. 0 –21–
AD8129/AD8130
20 20

10 10

0 0

–10 –10
I/O RESPONSE

I/O RESPONSE
–20 –20

–30 –30

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80
10k 100k 1M 10M 100M 10k 100k 1M 10M 100M
FREQUENCY – Hz FREQUENCY – Hz

Figure 8. Transmission Response of 300 m of Figure 10. Combined Response of Cable Plus Equalizer
Category 5 Cable Output Offset/Level Translator
The feedback network is between Pins 6 and 5 and from Pin 5 The circuit in Figure 6 has the reference input (Pin 4) tied to
to ground. C1 and RF create a corner frequency of about 800 kHz. ground, which produces a ground-referenced output signal. If it is
The gain increases to provide about 15 dB of boost at 8 MHz. desired to offset the output voltage from ground, the REF input
The response of this circuit is shown in Figure 9. can be used. (See Figure 11). The level VOFFSET appears at the
output with unity gain.
20
+V
10

0
AD8130
0.1F 10F
–10
I/O RESPONSE

+ PD +VS
–20 VIN
VOUT = VIN +VOFFSET
–30
VOFFSET +
–40 –VS

–50

–60

–70 0.1F 10F


–V
–80
10k 100k 1M 10M 100M
FREQUENCY – Hz
Figure 11. The voltage applied to Pin 4 adds to the unity-
gain output voltage produced by VIN.
Figure 9. Frequency Response of Equalizer Circuit
If the circuit has a gain higher than unity, the gain has to be
It is difficult to come up with the exact component values via factored in. If RG is connected to ground, the voltage applied to
strictly mathematical means, because the equations for the cable REF will be multiplied by the gain of the circuit and appear at
attenuation are approximate and have functions that are not the output; just like a noninverting conventional op amp, This
simply related to the responses of RC networks. The method situation is not always desirable and one may want VOFFSET to
used in this design was to approximate the required response via appear at the output with unity gain.
graphical means from the frequency response, and then select
components that would approximate this response. The circuit One way to accomplish this is to drive both REF and RG with
was then built and measured, and finally adjusted to obtain an the desired offset signal. (See Figure 12.) Superposition can be
acceptable response—in this case flat to 9 MHz to within used to solve this circuit. First break the connection between
approximately 1 dB. (See Figure 10.) VOFFSET and RG. With RG grounded the gain from Pin 4 to
VOUT will be 1 + RF/RG. With Pin 4 grounded, the gain though
RG to VOUT is –RF/RG. The sum of these is +1. If VREF is delivered
from a low-impedance source, this will work fine. However, if
the delivered offset voltage is derived from a high-impedance
source, like a voltage divider, its impedance will affect the gain
equation. This makes the circuit more complicated as it creates
an interaction between the gain and offset voltage.

–22– REV. 0
AD8129/AD8130
+V Summer
A general summing circuit can be made by the above technique.
AD8129/ A unity-gain configured AD8130 has one signal applied to +IN,
AD8130
0.1F 10F while the other signal is applied to REF. The output will be the
+ +VS
sum of the two input signals. (See Figure 15.)
VIN PD
+V
V OUT =
VOFFSET + V IN  (1+ R F /R G ) +V OFFSET
–VS
RG AD8130 0.1F 10F

V1 + PD +VS
RF
0.1F 10F VOUT = V1 + V2
–V V2 +
–VS
Figure 12. In this circuit, VOFFSET appears at the output
with unity gain. This circuit works well if the VOFFSET
Source Impedance is low.
0.1F 10F
A way around this is to apply the offset voltage to a voltage –V

divider whose attenuation factor matches the gain of the ampli-


Figure 15. A Summing Circuit that is Noninverting with
fier, and then apply this voltage to the high-impedance REF
High Input Impedance
input. This circuit will first divide the desired offset voltage by
the gain, and the amplifier will multiply it back up to unity. (See This circuit offers several advantages over a conventional op
Figure 13.) amp inverting summing circuit. First, the inputs are both high-
impedance and the circuit is noninverting. It would require
+V significant additional circuitry to make an op amp summing
circuit that has high input impedance and is noninverting.
AD8129/
AD8130
0.1F 10F
Another advantage is that the AD8130 circuit still preserves the
full bandwidth of the part. In a conventional summing circuit,
VIN
+ PD +VS the noise gain is increased for every additional input, so the
RF
V OUT = bandwidth response decreases accordingly. By this technique,
VOFFSET + V IN  (1+R F /R G ) + VOFFSET four signals can be summed by applying them to two AD8130s,
RG –VS and then summing the two outputs by a third AD8130.
Cable-Tap Amplifier
RG RF It is often desirable to have a video signal drive several different
0.1F 10F pieces of equipment. However, the cable should only be termi-
–V
nated once at its end point, so it is not appropriate to have a
termination at each device. A “loop-through” connection allows
Figure 13. Adding an attenuator at the offset input causes a device to tap the video signal while not disturbing it by any
it to appear at the output with unity gain. excessive loading.
Resistorless Gain-of-Two Such a connection, also referred to as a cable-tap amplifier, can
The voltage applied to the REF input (Pin 4) can also be a high be simply made with an AD8130. (See Figure 16.) The circuit is
bandwidth signal. If a unity-gain AD8130 has both +IN and configured with unity gain, and if no output offset is desired,
REF driven with the same signal, there will be unity gain from the REF pin is grounded. The negative differential input is
VIN and unity gain from VREF. Thus, the circuit will have a gain connected directly to the shield of the cable (or an associated
of two, and requires no resistors. (See Figure 14.) connector) at the point at which it wants to be “tapped.”
+V +V
AD8130
AD8130 75 0.1F 10F
0.1F 10F

VIN + PD +VS
+ PD +VS

VOUT
VOUT +
+
–VS
–VS

VIDEO
IN
0.1F 10F
0.1F 10F –V
–V 75

Figure 16. The AD8130 can tap the video signal at any
Figure 14. Gain-of-Two Connections with No Resistors point along the cable without loading the signal.

REV. 0 –23–
AD8129/AD8130
The center conductor connects to the positive differential input +V

of the AD8130. The amplitude of the video signal at this point


is unity, because it is between the two termination resistors. The AD8130 0.1F 10F
AD8130 provides a high impedance to this signal, so it does not VIN
disturb it. A buffered, unity-gain version of the video signal 1N4148
+ PD +VS
appears at the output.
VOUT
+
Power-Down VIN
–VS
The AD8129/AD8130 have a power-down pin that can be used
to lower the quiescent current when the amplifier is not being
used. A logic low level on the PD pin will cause the part to
power down. 0.1F 10F
–V
Since there is no “Ground” pin on the AD8129/AD8130, there
is no logic reference to interface to standard logic levels. For
Figure 18. Clamping Diodes at the Input Limit the Input
this reason, the reference level for the PD input is +VS. If the
Swing Amplitude
AD8129/AD8130 are run with +VS = 5 V, there will be direct
compatibility with logic families. However, if +VS is higher Another problem can occur with the AD8129 operating at supply
than this, a level-shift circuit will be needed to interface to con- voltage of greater than or equal to ± 12 V. The architecture
ventional logic levels. A simple level-shifting circuit that is causes the supply current to increase as the input differential
compatible with common logic families is presented in Figure 17. voltage increases. If the AD8129 differential inputs are over-
driven too far, excessive current can flow in the device and
+VS potentially cause permanent damage.
A practical means to prevent this from occurring is to differentially
clamp the inputs with a pair of antiparallel Schottky diodes.
7
1k +VS
(See Figure 19.) These diodes have a lower forward voltage
of approximately 0.4 V. If the differential voltage across the
3 PD
LOW= 4.99k 2N2222
inputs is restricted to these conditions, no excess current will
POWER-DOWN OR EQ AD8129/ be drawn by the AD8129 under these operating conditions.
AD8130
If the supply voltage is restricted to less than ± 11 V, the internal
Figure 17. Circuit that Shifts the Logic Level when +VS Is clamping circuit will limit the differential voltage and excessive
Not Equal to Approximately 5 V supply current will not be drawn. The external clamp circuit is
not needed.
Extreme Operating Conditions
The AD8129/AD8130 are designed to provide high perfor- +V
mance over a wide range of supply voltages. However, there are
some extremes of operating conditions that have been observed AD8129
0.1F 10F
to produce non-optimal results. One of these conditions occurs VIN
3
when the AD8130 is operated at unity gain with low supply + PD +VS
AGILENT
voltage—less than approximately ± 4 V. HSMS 2822
VOUT
At unity gain, the output drives FB directly. At supplies of ± VS VIN
1 2 +
less than approximately ± 4 V and unity gain, the voltage on FB –VS

can be driven by the output too close to the rail for the circuit to
stay properly biased. This can lead to a parasitic oscillation.
A way to prevent this is to limit the input signal swing with 0.1F 10F
–V
clamp diodes. Common silicon junction signal diodes like the
1N4148 have a forward bias of approximately 0.7 V when about
1 mA of current flow through them. Two series pairs of such Figure 19. Schottky Diodes Across the Inputs Limits the
diodes connected antiparallel across the differential inputs can Input Differential Voltage
be used to clamp the input signal and prevent this condition. It In both circuits, the input series resistors function to limit the
should be noted that the REF input can also shift the output current through the diodes when they are forward-biased. As a
signal, so this technique will only work when REF is at ground practical matter, these resistors need to be matched to the degree
or close to it. (See Figure 18.) that the CMRR needs to be preserved at high frequency. These
resistor will have minimal effect on the CMRR at low frequency.

–24– REV. 0
AD8129/AD8130
Power Dissipation The load current will be 6 V/250 Ω = 24 mA. This same current
The AD8129/AD8130 can operate with supply voltages from will flow through the output across a 6 V drop from +VS. This
+5 V to ± 12 V. The major reason for such a wide supply range will dissipate 144 mW. For the Micro_SO-8 package, this causes a
is to provide a wide input common-mode range for systems temperature rise of 20°C above ambient. Although this is a worst-
that might require this. This would be encountered when sig- case number, it is apparent that this can be a considerable
nificant common-mode noise couples into the input path. For additional amount of power dissipation.
applications that do not require a wide input or output dynamic
Several changes can be made to alleviate this. One is to use the
range, it is recommended to operate with lower supply voltages.
standard SO-8 package. This will lower the thermal impedance
The AD8129/AD8130 is also available in a very small Micro_SO-8 to 121°C/W, which is a 15% improvement. Next is to use a
package. This has higher thermal impedance than larger packages lower supply voltage unless absolutely necessary.
and will operate at a higher temperature with the same amount
Finally, do not use the AD8129/AD8130 to directly drive a
of power dissipation. Certain operating conditions that are within
heavy load when it is operating on high supply voltages. It is
the specification range of the parts can cause excess power dissi-
best to use a second op amp after the output stage. Some of the
pation. Caution should be exercised.
gain can be shifted to this stage so that the signal swing at the
The power dissipation is a function of several operating condi- output of the AD8129/AD8130 is not too large.
tions. These include the supply voltage, the input differential
Layout, Grounding and Bypassing
voltage, the output load and the signal frequency.
The AD8129/AD8130 are very high-speed parts that can be
A basic starting point is to calculate the quiescent power dissipa- sensitive to the PCB environment in which they have to oper-
tion with no signal and no differential input voltage. This is just ate. Realizing their superior specifications requires attention
the product of the total supply voltage and the quiescent operat- to various details of standard high-speed PCB design practice.
ing current. The maximum operating supply voltage is 26.4 V
The first requirement is for a good solid ground plane that cov-
and the quiescent current is 13 mA. This causes a quiescent
ers as much of the board area around the AD8129/AD8130 as
power dissipation of 343 mW. For the Micro_SO package, the
possible. The only exception to this is that the ground plane
θJA specification is 142°C/W. So the quiescent power will cause
around the FB pin should be kept a few mm away, and ground
about a 49°C rise above ambient in the Micro_SO package.
should be removed from inner layers and the opposite side of
The current consumption is also a function of the differential the board under this pin. This will minimize the stray capaci-
input voltage. (See TPCs 109 and 110.) This current should be tance on this node and help preserve the gain flatness versus
added on to the quiescent current and then multiplied by the frequency.
total supply voltage to calculate the power.
The power supply pins should be bypassed as close as possible
The AD8129/AD8130 can directly drive loads of as low as to the device to the nearby ground plane. Good high-frequency
100 Ω, such as a terminated 50 Ω cable. The worst-case power ceramic chip capacitors should be used. This bypassing should
dissipation in the output stage occurs when the output is at be done with a capacitance value of 0.01 µF to 0.1 µF for each
midsupply. As an example, for a 12 V supply and the output supply. Further away, low frequency bypassing should be provided
driving a 250 Ω load to ground, the maximum power dissipation with 10 µF tantalum capacitors from each supply to ground.
in the output will occur when the output voltage is 6 V.
The signal routing should be short and direct in order to avoid
parasitic effects. Where possible, signals should be run over
ground planes to avoid radiating, or to avoid being susceptible
to other radiation sources.

REV. 0 –25–
AD8129/AD8130
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead SOIC
(SO-8)

0.1968 (5.00)
0.1890 (4.80)

8 5
0.1574 (4.00) 0.2440 (6.20)
0.1497 (3.80) 1 4 0.2284 (5.80)

PIN 1
0.0500 (1.27) 0.0196 (0.50)
BSC  45
0.0099 (0.25)
0.0688 (1.75)
0.0098 (0.25) 0.0532 (1.35)
0.0040 (0.10) 8
0.0192 (0.49) 0.0500 (1.27)
SEATING 0.0098 (0.25) 0
PLANE 0.0138 (0.35) 0.0160 (0.41)
0.0075 (0.19)

8-Lead Micro_SO
(RM-8)

0.122 (3.10)
0.114 (2.90)

8 5
0.122 (3.10) 0.199 (5.05)
0.114 (2.90) 0.187 (4.75)
1 4

PIN 1
0.0256 (0.65) BSC
0.120 (3.05) 0.120 (3.05)
0.112 (2.84) 0.112 (2.84)
0.043 (1.09)
0.006 (0.15)
0.037 (0.94)
0.002 (0.05) 33
0.018 (0.46) 27 0.028 (0.71)
SEATING 0.008 (0.20) 0.011 (0.28)
PLANE 0.003 (0.08) 0.016 (0.41)

–26– REV. 0
–27–
–28–
PRINTED IN U.S.A. C02464–2.5–4/01(0)