2018 2DI4LabManual PDF

Digital Logic Design CoE 2DI4
2018 Laboratory Manual
by
Drs. Doyle and Bauman
Laboratory Manual
Issued with Labs 1, 2, 3, 4
Last Updated: September 21, 2018
McMaster University
Department of Electrical and Computer Engineering
Faculty of Engineering
Hamilton, Ontario, Canada
Copyright © 2018 by Drs. Doyle and Bauman

The manual was prepared to assist in meeting requirements
in the Principles of Programming undergraduate laboratory.
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ii
Abstract
The Laboratory Manual, which complements the course’s textbook and notes, defines
the scope, content, timing and academic standards in the laboratory component of
the Computer Engineering Logic Design (2DI4) course. Guidelines are included that
provide information on the expected form and content of the laboratory reports.
Although care has been taken to make the Manual reasonably accurate and helpful,
it should be stressed that no document can cover all the situations encountered in
engineering work.
iii
Contents
Abstract iii
Contents iv
List of Tables vii
List of Figures 1
1 Overview 3
1.1 Calendar Description of the Course . . . . . . . . . . . . . . . . . . . 3
1.2 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Laboratory Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Laboratory #1: Logic Gates 6

2.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Pre-Laboratory Preparation [20 marks total] . . . . . . . . . . . . . . 6
2.3 Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.1 TTL Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.2 Building Circuits, Expressions, and Truth Tables . . . . . . . 8
2.4.3 Logical Equivalence . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4.4 Enable/Disable Inverter . . . . . . . . . . . . . . . . . . . . . 11
2.4.5 Parity Generator . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.6 Equality Detection . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.7 Gate Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Discussion [10 marks total] . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6 Summary of Milestones . . . . . . . . . . . . . . . . . . . . . . . . . . 16
iv
2.7 Note Regarding Pre-Lab/Lab Format . . . . . . . . . . . . . . . . . . 16
2.8 Submission Requirements . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9 TA Grading Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Laboratory #2: Combinational Logic 19

3.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Pre-Laboratory Preparation [30 marks total] . . . . . . . . . . . . . 19
3.4 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1 The Karnaugh-Map for Boolean Minimization . . . . . . . . . 21
3.4.2 The Multiplexer (MUX) . . . . . . . . . . . . . . . . . . . . . 21
3.4.3 Half Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.4 Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4.5 n-bit Adder using 74LS283 . . . . . . . . . . . . . . . . . . . . 23
3.4.6 Addition and Subtraction using 74LS283 . . . . . . . . . . . . 24
3.4.7 Binary Code Decimal and the 7-Segment Display Encoder . . 25
3.4.8 BCD, 7-Segment Display, and the 2’s Complement . . . . . . . 27
3.4.9 Display the Correct Negative BCD . . . . . . . . . . . . . . . 27
3.6 TA Grading Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4 Laboratory #3: Programmable Logic 30

4.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.5 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.5.1 The Lamp Controller in HDL . . . . . . . . . . . . . . . . . . 32
4.5.2 3-to-8 Line Decoder . . . . . . . . . . . . . . . . . . . . . . . 32
4.5.3 3-to-8 Line Decoder in HDL . . . . . . . . . . . . . . . . . . . 33
4.5.4 Binary to Decimal Display Driver in HDL . . . . . . . . . . . 34
4.5.5 Bonus: Binary to Hexadecimal Display Driver in HDL . . . . 34
4.7 TA Grading Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5 Laboratory #4: Programmable & Sequential Logic 37

5.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2 Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
v
5.5 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5.1 The Versatile Flip-Flop: JK . . . . . . . . . . . . . . . . . . . 39
5.5.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.5.3 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.5.4 EPROM: Erasable Programmable Read Only Memory . . . . 44
5.7 TA Grading Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
vi
List of Tables
1.1 Laboratory evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Integrated Circuits for Lab 1 . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 4:1 MUX Function Table . . . . . . . . . . . . . . . . . . . . . . . . 21
vii
List of Figures
2.1 TTL Logic Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Logic Circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Logic Circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Logic Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Logic Circuit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 Logic Circuit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 Logic Circuit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.8 Logic Circuit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.9 Logic Circuit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.10 Logic Circuit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.11 Logic Circuit 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.12 Logic Circuit 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 4:1 MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2 The half-adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 The full-adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Function table for the 74LS283 . . . . . . . . . . . . . . . . . . . . . 24
3.5 Addition and Subtraction with the 74LS283 . . . . . . . . . . . . . . 25
3.6 BCD to 7-Segment Display . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 The sn74LS138 is a 3-to-8 line decoder as a programmable adder . . . 33
5.1 The JK FF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 A Shift Register Implementation . . . . . . . . . . . . . . . . . . . . . 41
5.3 A Shift Register Implementation in Schematic Capture . . . . . . . . 41
5.4 A Circular Shift Register Implementation . . . . . . . . . . . . . . . . 42
5.5 A Circular Shift Register Implementation in Schematic Capture . . . 42
5.6 A Synchronous Up-Counter Implementation . . . . . . . . . . . . . . 43
5.7 A Synchronous Up-Counter Implementation in Schematic Capture . . 43
5.8 An EPROM Circuit Implementation . . . . . . . . . . . . . . . . . . 45
1
2
5.9 An EPROM Circuit to Measure Access Time . . . . . . . . . . . . . . 46

Chapter 1
Overview
1.1 Logic Design (2DI4):

Calendar Description
Principles of Programming (2DI4) is briefly described in the McMaster Academic

Calendar:
Binary numbers and codes; Boolean algebra; combinational circuit design; elec-
trical properties of logic circuits; sequential circuit design; computer arithmetic; pro-
grammable logic; CPU organization and design
Three lecture hours, one tutorial, one lab every other week; first term
Prerequisites: Registration in a program in Computer Engineering, Electrical En-

gineering, Engineering Physics (Photonics Engineering Stream) or Physics.
Antirequisites:COMPSCI 2MF3, ELECENG 2DI4, SFWRENG 2D03, 2D04, 2DA3,

SFWRENG 2DA4
3
Chapter 1. Overview 4
Table 1.1: Digital Logic Design Laboratory Evaluation

Laboratory Session
Marking Weight
Base (%)
Lab 1 (Logic gates) ML1 100 5.0
Lab 2 (Combinational Logic) ML2 100 5.0
Lab 3 (Programmable Logic) ML3 100 5.0
Lab 4 (Sequential Logic) ML4 100 5.0
Lab 5 (System Design) ML5 100 5.0
Lab 6 (Practical) ML6 100 10.0
Laboratory Mark MLA 600 35.0
1.2 Evaluation
The final mark in the Digital Logic Design (2DI4) course consists of the components
listed in the 2DI4 course outline. The laboratory component of the course mark is
determined as specified in table 1.1.
Laboratory exercises may offer bonus mark(s) for extra and/or advanced work
by the student. The bonus mark(s) will only apply to lab reports that make a
clear attempt to meet all non-bonus criteria (including pre-lab). For example, by
not attempting to answer a question from the Laboratory Prelab section, the bonus
mark(s) will not be considered in evaluation of the exercise. It should also be noted,
although the bonuses may make it possible to achieve greater than 100% in the
laboratory component of CoE 2DI4, the maximum grade assigned to the laboratory
component will not be greater than 100%.
1.3 Laboratory Schedule

Labs run every other week of the course. You are required to check CMS daily to
confirm the schedule and receive corrections and/or clarifications to the lab exercises.
Pre-labs are due at the beginning of lab. Laboratory report and code/HDL are due
during the student’s assigned section. The student is advised that a submission after
the laboratory session ends is considered late; no exceptions.
Chapter 1. Overview 5
It should be stressed that due to high course enrolment, students shall not be
admitted to other laboratory sessions than those assigned.
Please enter and exit the lab punctually and pay close attention to the time
limits your TAs give you for submitting your lab exercises. Failure to have your lab
execution checked because the lab time expired may result in a 0 for the lab - TAs are
instructed to not accept/review work that is late.. Failure to exit the lab punctually
may result in being assigned an automatic zero for the entire lab exercise.
Chapter 2
Laboratory #1: Logic Gates
2.1 Objective
To introduce fundamental concepts of digital logic gates and laboratory techniques.
2.2 Pre-Laboratory Preparation [20 marks total]

1. For each of the following logic operations define the i) truth table, ii) logic
symbol, and iii) integrated circuit name/identification (hint: how do you iden-
tify the integrated circuit – find the 2-input data sheet) for the following logic
operators [18]:
(a) AND,
(b) OR,
(c) NAND,
(d) NOR,
(e) XNOR, and
(f) XOR.
2. In the context of 2DI4, define the term “Logical equivalence” and provide an
example [2].
3. Complete the ECE lab safety quiz. [0]
6
Chapter 2. Laboratory #1: Logic Gates 7
2.3 Integrated Circuits

The following integrated circuits are to be used in this laboratory:
Table 2.1: Integrated Circuits for Lab 1

Identification Description
sn74LS00 2-input NAND
sn74LS04 1-input inverter
sn74LS86 2-input XOR
Obtain the data sheets for each of the above TTL devices. Familiarize yourself
with their logical and electrical characteristics and bring a copy to your lab session.
2.4 Experiment
Read the following experiment and study the circuits as shown. Pre-filling your re-
port with the necessary truth tables and structuring your report such that you only
need record experimental output will allow you to focus on the experiment(s).
ENSURE YOUR MILESTONES ARE VISUALLY CHECKED AND RECORDED

BY A TA.
2.4.1 TTL Levels

For input to a TTL gate, voltages from 0 to 0.8 V are taken to mean a logical LO
(or False). Input voltages between 2.0 and 5.0 are considered logical HI (or True).
Voltages between 0.8V and 2.0V are indeterminate and are avoided. These ranges
are slightly different for TTL outputs to allow some noise margin.
Using a function generator, set the output of the function generator to a 100KHz
triangular wave (carefully verifying that it is 5V peak-to-peak with 2.5V DC
offset using the oscilloscope). Apply this triangular waveform from the function
generator to the NAND gate input as shown below.
1. Display the function generator’s 100KHz triangular wave on channel 1 of the

oscilloscope.
2. Display the output of the NAND gate on channel 2 of the oscilloscope.
3. Using the automatic measuring functions of the digital oscilloscope, state at

what input voltage level the output of the NAND changes? Specifically –
does the automatic measuring function match the TTL levels for LO and HI?
Milestone 1: TA to check 3. [10 marks]
Figure 2.1: TTL Logic Test Circuit
2.4.2 Building Circuits, Expressions, and Truth Tables

4. Connect each of the following circuits and experimentally verify each circuit
truth table. For inputs use switches and for output connect light emitting
diodes (LEDs). For each circuit i) state the logical function, and ii) draw the
truth table.
Milestone 2: TA to check 4e. [10 marks]
(a)
Figure 2.2: Logic Circuit 1
(b)
(c)

(d)
(e)
2.4.3 Logical Equivalence

5. Build the following circuit and experimentally verify the truth table. Is this
logically equivalent to a logical operator that you have seen before? if so, which
one?
Milestone 3: TA to check 5 – answer equivalence question. [10 marks]

2.4.4 Enable/Disable Inverter
6. The output of the 2-input XOR gate is HI when its inputs are different and LO
otherwise. Verify the truth table for the XOR gate and explain how it could
also be considered to be a ”controllable inverter”.
(a)
2.4.5 Parity Generator
7. Parity bits are commonly used to detect errors in serial communications and
memory access. A binary number is said to have odd parity if the number of
1’s contained in it is odd; it has even parity when the number of 1’s is even.
This may be detected using an XOR gate circuit such as the one shown. Build
the following circuit to verify that the output FP arity is HI when the parity of
the input word wxyz is odd and LO otherwise. Draw the corresponding truth
table.
(a)
2.4.6 Equality Detection

8. The equality of two bits can be indicated with the XNOR (sometimes called
a ”coincidence gate”). Verify this by examining the truth table of the XNOR.
For testing the equality of multi-bit numbers, corresponding bits from each
number may be compared using an XNOR gate, and the results of each of
these AND’ed together. Build a circuit to implement the following logic and
verify that its output Fequality is HI only when 3-bit inputs abc and xyz are
equal.
Note: this idea is readily extended to produce a circuit that compares the
magnitude of input numbers. For example the SN74LS85 takes two 4-bit inputs
A and B, and produces three outputs that indicate A = B, A > B or A < B.
2.4.7 Gate Delay

Gate propagation delays can be used to the designer’s advantage to generate
a short pulse; however, when this is done inadvertently, it is called a ”glitch”
and can be the source of frustrating problems.
(a)
Pulse Generator
9. Build the circuit as shown below. For the input apply 100Hz square wave
(carefully verifying that it is 5V peak-to-peak with 2.5V DC offset using
the oscilloscope) to the clock input. Display the input signal on channel 1 of the
oscilloscope. Display the output signal (Fdelay ) on channel 2 of the oscilloscope
and explain the result. For your report you can carefully draw or photograph
the two wave forms and clearly label the axis, oscilloscope channels, pulse Fdelay
(channel 2) relative to the edges of the input waveform (channel 1), and the
total pulse delay. Before disconnecting this circuit, ensure you have noted the
Discussion requirement in section 2.5.
Milestone 4: TA to check 9b. [15 marks]
(a) Provide a clear sketch of both clock input and Fdelay . Label your axes.
(b) Comparing these two waveforms, what would you estimate for the tdelay .
(c) Vary the number of inverters in the circuit and state the effect.
(d) Replace the NAND gate in this circuit with an XOR gate and explain the
observed output.
Oscillator
10. Connect a series of 4 inverters plus a NAND gate (as shown below) and display
the output Foscillator on the oscilloscope. An odd number of inversions back-
to-back will produce an oscillator with a period equal to twice the delay of the
inverter chain.
Milestone 5: TA to check 10b. [15 marks]
(a) Measure and clearly state the time for 1/2 of one cycle of this circuit using
the automatic measurement functions of the oscilloscope.
(b) How does this measured time compare to parameters tP LH and tP HL from
the sn74LS00 data sheet? State tP LH and tP HL .
2.5 Discussion [10 marks total]

Referring back to the Gate Delay Measurement using the pulse Fdelay (see sec-
tion 2.4.7), sketch and explain the output you would expect to see if the NAND
in the original circuit were replaced with a NOR gate ( you are not required to
actually modify the circuit ).
2.6 Summary of Milestones

TA must visually verify and record your completion of:
1. 3
2. 4e
3. 5
4. 9b
5. 10b
2.7 Note Regarding Pre-Lab/Lab Format

Please note the following:
1. Prelab is to be prepared as a short report, submitted as a pair (same two

students that work together in lab), and uploaded to CMS by 2:45pm of your
assigned lab day.
2. Milestones must be checked off by TA
3. Milestones results/observations must be recorded in lab report as proof of work

and reference for students. (e.g., photo of oscilloscope waveform, photo of
circuit, etc.)
4. Complete lab report must be uploaded to CMS by 5:20 pm.
5. Students must exit laboratory no later than 5:30pm. No exceptions.
6. All files are submitted PDF format.
2.8 Submission Requirements

Please ensure you complete the following items prior leaving the laboratory:
1. At the beginning of each lab you are to have your Pre-Lab checked for com-
pletion by a TA.
2. Your lab report has a cover page clearly indicating the lab title, date, each
member’s name, and student number.
3. Cover page must also contain the following statement:
As a future member of the engineering profession, the student is

responsible for performing the required work in an honest manner,
without plagiarism and cheating. Submitting this work with my
name and student number is a statement and understanding that
this work is our own and adheres to the Academic Integrity Policy
of McMaster University and the Code of Conduct of the Professional
Engineers of Ontario.
4. Each experiment milestone has been checked by a TA.
5. One member has uploaded the lab report to Avenue (ensuring both have a
copy for future reference).
2.9 TA Grading Table
Component Weight Grade

Pre-lab 20
Milestone 1 10
Milestone 2 10
Milestone 3 10
Milestone 4 15
Milestone 5 15
Results and Report 20
Total 100
Deductions
Final Score
Chapter 3
Laboratory #2: Combinational

Logic
3.1 Objective
To introduce fundamental concepts of combinational logic and circuit design.

1. Define the term multiplexer and provide an example of where one would be
used in a digital system. [2 marks]
2. Define the term encoder and provide an example of where one would be used
in a digital system (not a software system/application).[2 marks]
3. Define the term decoder and provide an example of where one would be used
in a digital system (not a software system/application).[2 marks]
4. Define the term binary coded decimal and provide an example of where one
would be used in a digital system.[2 marks]
5. Minimize the following Boolean function and draw the circuit diagram (use
logic symbols) using only NAND gates (HINT: DeMorgan’s Theorem is re-
quired here).
19
Chapter 3. Laboratory #2: Combinational Logic 20
P
F (a, b, c, d) = (0, 2, 5, 7, 8, 10, 13, 15)
(a) Complete the correct K-map of function F (a, b, c, d).[4 marks]

(b) Write F (a, b, c, d) in standard form (terms must be correctly ordered in
increasing value).[4 marks]
(c) Write the minimized Boolean F (a, b, c, d) function using K-map reduction
techniques.[4 marks]
(d) Write the minimized Boolean F (a, b, c, d) function using ONLY NAND
gates. Show how you verified the minimized circuit.[4 marks]
(e) Using logic symbols draw the minimized Boolean F (a, b, c, d) function
using ONLY NAND gates.[6 marks]


sn74LS47 BCD-to-7-segment encoder
sn74LS86 2-input XOR
sn74LS283 4-bit binary adder
Obtain the data sheets for each of the above TTL devices. Familiarize yourself
with their logical and electrical characteristics and bring a copy to your lab session.
3.4 Experiment
Read the following experiment and study the circuits as shown.
REQUIRED: Pre-filling your report with the necessary truth tables, ta-
bles, circuit diagrams, etc. and structuring your report such that you
only need record experimental observations will allow you to focus on the
experiment(s). Failing to do this will result in an incomplete lab.
REQUIRED: ENSURE YOUR MILESTONES ARE VISUALLY CHECKED

AND RECORDED BY A TA.
3.4.1 The Karnaugh-Map for Boolean Minimization

1. Minimize and implement the following function using only NAND gates:
Milestone 1: TA to check 1
P
F (a, b, c, d) = (0, 2, 5, 7, 8, 10, 13, 15)
3.4.2 The Multiplexer (MUX)

2. A MUX is a combination circuit that selects binary information from one of

several inputs and logically directs that input to the output channel(s). Com-
plete the following circuit to implement a 4:1 MUX. The input are data lines
D0 to D3 . The select lines are S0 and S1 (hint: given two select variable, how
many items can you uniquely select?). Output is Y. Build the circuit and verify
the function table.
Table 3.2: 4:1 MUX Function Table

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Figure 3.1: 4:1 MUX
3.4.3 Half Adder
3. The fundamental circuit for computation is the half adder. Figure 3.2 illustrates
the half-adder combinational logic circuit. The output S is the sum of inputs
A and B, where Cout represents a carry out. Build this circuit and verify the
truth table. Use switches for inputs and LEDs for output(s).
Figure 3.2: The half-adder

3.4.4 Full Adder

4. The full adder is a combination of two half-adders to produce a combinational
logic circuit with a sum output (S), and a carry output (Cout ) from inputs A,
B, and Cin . Figure 3.3 illustrates the full-adder combinational logic circuit.
This arrangement permits fast parallel organization for the addition of n-bit
numbers. This circuit is the basis for many arithmetic functions, such as,
subtraction, multiplication, and division. Build this circuit and verify the truth
table. Use switches for inputs and LEDs for output(s).
Figure 3.3: The full-adder
3.4.5 n-bit Adder using 74LS283

5. An n-bit adder can be constructed by serially connecting the carry-out n full
adders. The input carry to the first full address in the serial chain is C0 and the
output from the final full adder is Cn . Because of the serial carry configuration,
this arrangement is often referred to as a ripple carry adder and as a result it
has the undesirable characteristic that add time is proportional to n.
A better approach is to form the sum and carry out in a parallel arrangement,
such as the arrangement of the 74LS283. The 74LS283 is a 4-bit parallel adder
with internal carry look-ahead. Review the data sheet for this IC and note the
internal configuration of gates.
Verify the operation of the 74LS283 by wiring the IC and completing the table
below. Use switches for inputs and LEDs for output(s). Clearly record the
output as unsigned and as signed 2’s complement.
Figure 3.4: Function table for the 74LS283
3.4.6 Addition and Subtraction using 74LS283
6. A parallel adder may be used to add or subtract 4-bit numbers. Given the
following arrangement , when S=0 the output is A+B. When S=1, the output
is A-B. Construct and verify this circuit. Explain the operation (hint: what
are S and the XORs doing?).
Note that this adder/subtractor may be used to take the 2’s complement of an
input B by setting A=0000 and S=1. Verify this for several test cases. This
feature will be used in a following circuit so do not disconnect this circuit.
Figure 3.5: Addition and Subtraction with the 74LS283
3.4.7 Binary Code Decimal and the 7-Segment Display

Encoder
7. The seven-segment display is an easy and very common way to display decimal
numbers from binary codes. Each segment of the display is lit by pulling
the input to the display LO. The 74LS47 BCD to 7-segment encoder will
drive the display with the correct current-limiting requirements. NEVER
CONNECT THE DISPLAY INPUTS TO GROUND OR +5V - YOU
WILL DESTROY THE DEVICE. Connect the circuit as shown below
and leave this circuit connected for use in a following circuit. However, before
proceeding you should connect the 4 BCD inputs to 4 sequential toggle switches
and verify you understand the device operation.
Figure 3.6: BCD to 7-Segment Display

3.4.8 BCD, 7-Segment Display, and the 2’s Complement
8. Connect the output of the adder/subtractor circuit from section 3.4.6 to the
input of of the 74LS47 BCD to 7-segment encoder circuit from section 3.4.7.
3.4.9 Display the Correct Negative BCD
After completing Milestones 1–4, design a combinational logic circuit to cor-

rectly display a negative BCD number after 74LS283 subtraction. (hint, return
to the algorithm provided in lecture). To denote a negative, turn on a decimal
point on the seven-segment display. You will have to explain your design.
Bonus Milestone: TA to check bonus design and implementation

1. At the beginning of each lab you are to have your Pre-Lab submitted no later
than 2:45pm.

5. One report uploaded per 2-member team. Please ensuring both team members
have a copy for future reference.

Pre-lab 30
Milestone 1 10
Milestone 2 10
Milestone 3 15
Milestone 4 15
Bonus Milestone 10
Experiment Observations and Report 20
Total 100
Deductions
Final Score
Chapter 4
Laboratory #3: Programmable

Logic
4.1 Objective
To introduce fundamental concepts of combinational logic and circuit design. To
demonstrate the use of a commercial Programmable Logic Device (PLD) design
package for schematic and Verilog entry. To introduce the design process for combi-
national logic in a Complex Programmable Logic Device (CPLD) device.
4.2 Resources
You will need the following resources to complete this lab:
1. Software: Quartus II Web Edition versions 9.0 (available in lab and can be
downloaded free from Altera)
2. Reference: ftp://ftp.altera.com/up/pub/Altera_Material/9.0/Tutorials/
Verilog/
3. Introduction: ftp://ftp.altera.com/up/pub/Altera_Material/9.0/Tutorials/
Verilog/Quartus_II_Introduction.pdf
30
Chapter 4. Laboratory #3: Programmable Logic 31

1. Review the Quartus II Introduction file specified in section Resources - item 3.
Complete the outlined example for the light controller circuit (an XOR circuit).
Implement the model as i) Primitive Gate Modelling, ii) Schematic Capture.
Provide a screen capture of both of your successful simulation. [10 marks]
2. Study the data sheet for the seven-segment-display (MAN34x0A,36x0A,38x0A,70A).

Design a minimized combinational logic circuit that takes a 2-bit binary code
and drives the display to show the decimal equivalent (e.g., 00 = 0, 01 = 1, 10
= 2, 11 = 3). Carefully note the required input to the seven-segment-display
to light an individual segment. Show your design steps. Describe the resultant
design using a Verilog modelling method of your choice. [10 marks]


sn74LS138 3-to-8 line decoder
MAX3000 EPM3032ALC44-10 CPLD
Seven segment display MAN34x0A,36x0A,38x0A,70A
Obtain the data sheets for each of the above devices. Familiarize yourself with
their logical and electrical characteristics and bring a copy to your lab session.
4.5 Experiment

4.5.1 The Lamp Controller in HDL

Milestone 1: Lamp Controller Your TA will ask you to compile in Quartus II
and load the CPLD with the lamp controller from either the Primitive Gates Model
(AND, OR, NOT, etc.) or the Schematic Capture Model that you completed in the
pre-lab. Wire to test.
4.5.2 3-to-8 Line Decoder

A binary code of n-bits can represent unto 2n unique elements. A decoder is a
combinational logic circuit that converts the n-bit binary code to 2n unique line
outputs. We generally refer to these as n − to − m-line decoders. The sn74LS138 is
a 3-to-8 line decoder and often used to convert from binary to octal, although it can
be used to decode any 3-bit code.
1. Verify the function table for the sn74LS138 is a 3-to-8 line decoder from Table
4.6 of your textbook (Truth Table of a Three-toEight-Line Decoder). Use
switches for X, Y, Z selects and LEDs for the outputs. Refer to the data sheet
for handling the enable pins.
2. Moving toward the concept of “programming” hardware, if we consider the

output of the decoder to be rows of a matrix connected to columns of NAND
gates (see fig. 4.1 then we may generate any logic function, such as F1 or F2, as
a “programming” task. We can “program” each function by connecting row to
column at their intersection – as shown, none of the intersections are currently
connected, but we can denote a connection by “fusing” the connection (just
place a dot at the intersection you’re connecting). Each function can be the
summation of any 4 minters of the XYZ inputs. Our example is limited to F1
and F2, but you are only limited in your own designs by the number of NAND
gates (1 NAND/function) and number inputs the NAND gate(s).
Referring to your textbook, find the truth table and logic expression for a full
adder (see Table 4.4). “Program” this full-adder circuit such that F1 represents
the sum (S) and F2 represents the carry (C). Mark every connected row-column
intersection with an X. Build the circuit and verify operation. (hint: consider
how DeMorgan’s can help here).
Figure 4.1: The sn74LS138 is a 3-to-8 line decoder as a programmable adder
4.5.3 3-to-8 Line Decoder in HDL

Milestone 3: HDL Model 3-to-8 Line Decoder Refer to your textbook for the
design of a 3-to-8 Line Decoder (input: 3-bits binary code. output: 1 of 8 bits). For
reference, a 3-to-8 line decoder schematic can be found in Mano Figure 4.18 (Figure
4.19 is a 2-to-4 line decoder with enable). HDL Example 4.1 is also a good starting
point. Using Quartus II define a 3-to-8 Line Decoder, compile your model and load
it on to the CPLD. For inputs connect wires from toggle switches to CPLD inputs.
For outputs connect CPLD outputs to LEDs.
For your report, include a screen capture of your modelling – ensure all team
member names and student numbers appear in the comments of the Verilog model
text.
4.5.4 Binary to Decimal Display Driver in HDL

Milestone 4: Binary to Decimal Display Design a minimized combinational
logic circuit that takes a 2-bit binary code and drives the display to show the decimal
equivalent (e.g., 00 = 0, 01 = 1, 10 = 2, 11 = 3). Carefully note the required input
to the seven-segment-display to light an individual segment. Describe the resultant
design using a textbfVerilog modelling method of your choice. Compile in Quartus
II, load on to the CPLD, and wire to test.
For your report include a screen capture of your modelling – ensure all team
member names and student numbers appear in the Verilog model screen capture.
4.5.5 Bonus: Binary to Hexadecimal Display Driver in HDL

Bonus Milestone: Binary to Hexadecimal Display Design a minimized com-
binational logic circuit that takes a 4-bit binary code and drives the display to show
the hexadecimal equivalent. Describe the resultant design using Verilog’s Boolean
Equations modelling method. Compile in Quartus II, load on to the CPLD, and
wire to test.
For your report include a screen capture of your modelling – ensure all team
member names and student numbers appear in the Verilog model screen capture.

than 2:45pm.


Pre-lab 20
Milestone 1 15
Milestone 2 15
Milestone 3 15
Milestone 4 15
Bonus Milestone 10
Total 100
Deductions
Final Score
Chapter 5
Laboratory #4: Programmable &

Sequential Logic
5.1 Objective
To apply the design process for combinational logic in a Complex Programmable
Logic Device (CPLD) device. To study the behaviour and application of sequential
circuits.
5.2 Resources
You will need the following resources to complete this lab:
1. Software: Quartus II Web Edition versions 9.0 (available in lab and can be
downloaded free from Altera)
2. Reference: ftp://ftp.altera.com/up/pub/Altera_Material/9.0/Tutorials/
Verilog/
3. Introduction: ftp://ftp.altera.com/up/pub/Altera_Material/9.0/Tutorials/
Verilog/Quartus_II_Introduction.pdf
37
Chapter 5. Laboratory #4: Programmable & Sequential Logic 38

1. Using Quartus II schematic capture, implement figure 5.2.
4. Define EPROM and provide a real-world example of where it would be used.


MAX3000 EPM3032ALC44-10 CPLD
Seven segment display MAN34x0A,36x0A,38x0A,70A
sn74LS00 Quad 2-input NAND
sn74LS76 Dual JK Master-slave flip flop
2732A EPROM
Obtain the data sheets for each of the above devices. Familiarize yourself with
their logical and electrical characteristics and bring a copy to your lab session.
5.5 Experiment

5.5.1 The Versatile Flip-Flop: JK

The JK flip-flop is a widely used and available device for the implementation of
sequential logic circuit design. The JK is easily used like an SR, T, or D flip-flop.
Figure 5.1: The JK FF
1. Verify the behaviour of the JK flip-flop by wiring up the IC and compare against
the characteristic table (inputs are toggle switches, output LEDs). Make note
of the following: i) is this device rising edge, falling edge, or a level trigger, ii)
what does the preset do, and iii) what does the clear do?
2. Modify your circuit from part-1 by using a single input toggle switch connected
to J and K. Compare to the characteristic table of a T flip-flop.
3. Modify your circuit from part-1 by using a single input toggle switch connected
to J with an inverter from J to K. Compare to the characteristic table of a D
flip-flop.
5.5.2 Registers
A register is a group of n flip-flops operating together to represent an n-bit binary
number. Each flip-flop represents a single bit. The simplest form of a register is used
to capture its input(s) and hold the value (e.g., the D flip-flop) in response to the
write command (a clock pulse). A common application in using registers is to shift
their content by one bit left or right. A left shift, moving all bits one position to the
left, has the effect of multiplying the content value by 2. Conversely, a right shift
has the effect of dividing the content value by 2.
For the implementation of these registers, please design the circuit using schematic
capture in the Quartus II IDE. Load each circuit onto the MAX3000 chip and test
with toggles switches and LEDs. Note that switches 12 15 are de-bounced.
1. There are a number of way to connect flip-flops in series to create shift registers.
Figure 5.2 illustrates a simple left-to-right shift register. Note it is constructed
using JK’s in such a way they operate like D flip-flops. Implement the cir-
cuit as shown in the HDL and load onto the CPLD. Tie your preset values
HI and experiment with this circuit sing a very low clock frequency supplied
by the physical bench top function generator (Alternatively you could use a
toggle switch to simulate the clock). Observe the register bit output patterns
(Q3 Q2 Q1 Q0 ) on LEDs. Remember to also use the toggle switches to input the
clear and serial data signals. If the HDL model of the flip-flop does not provide
a Q’ output then implement one using an inverter off of Q.
2. Modify your Shift Register circuit as shown in figure 5.4 to implement a circular
shift capability by connecting the Q0 output back to the input through an OR
gate. You will also find this implementation referred to as a ring counter.
Milestone 1: TA to check Circular Shift register operation
Figure 5.2: A Shift Register Implementation
Figure 5.3: A Shift Register Implementation in Schematic Capture
5.5.3 Counters
As we have a focus on synchronous sequential logic, you will only be required to build
a synchronous counter. However, the student is should be aware that there exist
Figure 5.4: A Circular Shift Register Implementation
Figure 5.5: A Circular Shift Register Implementation in Schematic Capture
many asynchronous counter designs which can cause difficulties due to intermediate
false outputs caused by time delays. Using HDL implement the synchronous counter
from figure 5.6. The counter from figure 5.6 is a better design because all flip-flops
receive a common clock pulse. Verify the timing and operation using the timing
diagram provided, Note: count enable can freeze the clock count, and clock transition
occur on rising edge.
Figure 5.6: A Synchronous Up-Counter Implementation
Figure 5.7: A Synchronous Up-Counter Implementation in Schematic Capture
Increase the clock frequency to 100KHz and record the frequency at each output.
Milestone 2: TA to check Synchronous Counter operation
5.5.4 EPROM: Erasable Programmable Read Only Memory

The EPROM is programmable memory that retains its contents even when power
is not supplied. This makes it a non-volatile read-only memory element. There are
numerous applications for the EPROMs - one such is the Look-Up Table (LUT). In
fact, we consider any ROM to be a look-up table. By programming the ROM with
a truth table, any combinational logic function can be implemented. Connect the
2732A as shown in figure 5.8. Note that the OE and CE lines must be low for out-
put data to appear on data output lines (O0 – O7 ). Connect toggle switches as shown.
The 2732A contains the binary to BCD conversion look-up table (LUT). A binary
Figure 5.8: An EPROM Circuit Implementation
number is applied to the address inputs (A0 – A7 ) and the equivalent BCD number is
read from the output. Given we have 8 output lines we can store 00-99 BCD values
for which we will require 7 bits (A0 – A6 ). The first 100 locations from address 0000
0000 0000 to 0000 0110 0011 of the EPROM are used for the binary-to-BCD LUT.
Verify the operation of the device and the conversion.
Milestone 3: TA to check EPROM Binary-to-BCD operation
Access time for peripheral digital devices is always a concern to the digital de-
signer. When the CE and OE lines are tied LO, the one way to calculate this
EPROM’s access time tACC is the delay between i) the application of an address
input, and ii) the appearance of stable data input outputs. Configure the EPROM
circuit as shown in figure 5.9 and observe the output from pin O1 on the oscilloscope.
Using this waveform, estimate the actual tACC for the 2732A EPROM. Sketch and
explain your observations.
Milestone 4: TA to check EPROM Access operation

Figure 5.9: An EPROM Circuit to Measure Access Time

than 2:45pm.


Pre-lab 20
Milestone 1 15
Milestone 2 15
Milestone 3 15
Milestone 4 15
Total 100
Deductions
Final Score

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Digital Logic Design CoE 2DI4

2018 Laboratory Manual

Drs. Doyle and Bauman

Copyright © 2018 by Drs. Doyle and Bauman

List of Tables vii

2 Laboratory #1: Logic Gates 6

3 Laboratory #2: Combinational Logic 19

4 Laboratory #3: Programmable Logic 30

5 Laboratory #4: Programmable & Sequential Logic 37

1.1 Laboratory evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Integrated Circuits for Lab 1 . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Integrated Circuits for Lab 1 . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 Integrated Circuits for Lab 1 . . . . . . . . . . . . . . . . . . . . . . . 31

5.1 Integrated Circuits for Lab 1 . . . . . . . . . . . . . . . . . . . . . . . 38

2.1 TTL Logic Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 4:1 MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 The sn74LS138 is a 3-to-8 line decoder as a programmable adder . . . 33

5.9 An EPROM Circuit to Measure Access Time . . . . . . . . . . . . . . 46

1.1 Logic Design (2DI4):

Principles of Programming (2DI4) is briefly described in the McMaster Academic

Prerequisites: Registration in a program in Computer Engineering, Electrical En-

Antirequisites:COMPSCI 2MF3, ELECENG 2DI4, SFWRENG 2D03, 2D04, 2DA3,

Table 1.1: Digital Logic Design Laboratory Evaluation

1.3 Laboratory Schedule

Laboratory #1: Logic Gates

2.2 Pre-Laboratory Preparation [20 marks total]

3. Complete the ECE lab safety quiz. [0]

2.3 Integrated Circuits

Table 2.1: Integrated Circuits for Lab 1

ENSURE YOUR MILESTONES ARE VISUALLY CHECKED AND RECORDED

2.4.1 TTL Levels

1. Display the function generator’s 100KHz triangular wave on channel 1 of the

2. Display the output of the NAND gate on channel 2 of the oscilloscope.

3. Using the automatic measuring functions of the digital oscilloscope, state at

Figure 2.1: TTL Logic Test Circuit

2.4.2 Building Circuits, Expressions, and Truth Tables

Figure 2.2: Logic Circuit 1

Figure 2.3: Logic Circuit 2

Figure 2.4: Logic Circuit 3

Figure 2.5: Logic Circuit 4

Figure 2.6: Logic Circuit 5

2.4.3 Logical Equivalence

Milestone 3: TA to check 5 – answer equivalence question. [10 marks]

Figure 2.7: Logic Circuit 6

2.4.4 Enable/Disable Inverter

Figure 2.8: Logic Circuit 7

2.4.5 Parity Generator

Figure 2.9: Logic Circuit 8

2.4.6 Equality Detection

2.4.7 Gate Delay

Figure 2.10: Logic Circuit 9

Figure 2.11: Logic Circuit 10

Figure 2.12: Logic Circuit 11

2.5 Discussion [10 marks total]

2.6 Summary of Milestones

2.7 Note Regarding Pre-Lab/Lab Format

1. Prelab is to be prepared as a short report, submitted as a pair (same two

2. Milestones must be checked off by TA

3. Milestones results/observations must be recorded in lab report as proof of work

4. Complete lab report must be uploaded to CMS by 5:20 pm.

5. Students must exit laboratory no later than 5:30pm. No exceptions.

6. All files are submitted PDF format.

2.8 Submission Requirements