Verilog Lab - Memory Model + In this example the Design/DUT is Memory Model. enable rdw Signal Definition Saran Dict ato Deng [Beep ek ina post som ft inst estan ro not peas aga eh he fasten seated oo Tea abe nal sae ate peer eat] a aaa et) co fects sirl redsOperations ie Gk eg ne ge ey address, rd_va = 0, enable and wr_data should be driven at the same clock cycle. Read Operation: ‘address rd_wr = 1, enable should be driven on the same clock cycle, design will respond with the rd_data in the next clack cycle. Design Features, ‘The Memory model is capable of storing 8bits of data per address location. Reset values of each address memory location is “AFF . Presened By Desi Resin Verification Plan * Verification pian is the list of scenarios need to be verified. = Write end Read to a particular memory location. + Perform write to any memory location, read ftom the same memory location, read data should be same as writen data = Write and Read to all memory location, + Perform write and read to all the memory locations (as adress is bi wit the possibie address are 2 6000, 28001, 26070 and 2/6011 20100, 2107, 2b110and 20111) ~ Defauit memory value check. *+ Check default memory values. (before wring any locations, do ead ‘operation. You should get default values as NF) Reset in Middle of WritelRead Operation + Assertresetin between write/read operations and check for default ‘values. (after ring to fe locations assert the resat and perform read ‘operation, you should get default memory location valve FF) Presened By Desi Resin