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. III.CIRCUIT UNDER TEST(U
UART)
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Table1.port name and functionality of UART transmitter III. UART RECEIVER SECTION
Port Port Function
Name Type
DB i/p 8-bit parallel data input to the transmitter
WR i/p A “low” writes the data from the data bus in
the transmitter buffer
ACK i/p Acknowledgement signal from the
peripheral (active high).
TxC i/p Transmitter clock signal.
RST i/p A “high” resets the transmitter.
TxD o/p Serial data output from the transmitter.
When no data is transmitted, this remains Figure7: UART receiver section architecture
“high”. Figure7 shows the architecture of UART receiver section. The
TxRDY o/p A “high” indicates that the transmitter is followings are the brief description of each block
ready to transmit data i.e. the transmitter Input Register: I/P register is a serial input and serial output
buffer is empty register which consists of 8 D-flip flops to store and shift 8 bit
TxE o/p A “high” indicates that the transmitter has input data. The input data of the register is the serially
no data in its output register to transmit transmitted data from the transmitter.
Receiver buffer register: It is a 8 bit serial in parallel out
FLOW CHART OF UART TRANSMITTER register. The data of i/p register is shifted and enters bit by bit
in every rising clock edge in Receiver Buffer Register. After
entering 8 bit data, the buffer gets full.
Receiver Control Logic: This block decides when data is to
be taken inside the receiver and when data is to be sent to
peripheral device.
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2) When the peripheral device does not want w data from the The figure8 is depicting the simulation result of Receiver
receiver but the receiver buffer register is fullf then any data section. Now, the first eight bits inside the left most donut are
cannot be taken inside the Receiver sectionn and if any data seen at the output of receiver after
a 16 clock cycle delay. After
arrives then data should be discarded. that the next input bits can be seen
s at the output of the receiver
3) When the peripheral device want data from the receiver at an interval of 8 clock pulses if, proper signals are there.
but the receiver buffer register is not full thenn no data is sent to
the peripheral and data is taken in Receiver buffer from input PERI-RQT is active high signnal. When the signal is high and
register. the receiver buffer is full the reeceiver buffer data is send to the
4) When the peripheral device does not want w data from the peripheral device. In the figuree the up arrow pointing towards
receiver and the receiver buffer register is noot full then data is the donut in which the rxfulll signal has gone high as the
taken inside Receiver buffer from input register r with each receiver buffer register becom me full but at the same time the
clock pulse rising but data is not sent to the peripheral.
p peripheral device does not wannt any data, so the receiver is not
sending the data towards periipheral at that instance. As the
receiver become full so the signal rxrdy (receiver ready)
FLOW CHART OF UART RECEIVER become low, indicating that thee receiver cannot take any more
data at that instance. So transm mitter should not send any data
towards the receiver.
Figure8.simulation result
Figure 9: Port mapping and thee internal components of LFSR
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In this figure9 a LFSR of polynomial X8+X6+X5+1 is made. A VI. SIMULATION RESULT OF BIST ENABLED UART
PISO with one 3 bit down counter & one 1 CLk delay In the figure12 the simulation result of the BIST enabled
component is connected. O/P from all DFF comes to the PISO UART is presented. The overall simulation result of the
, PISO has another two I/P sel & Reg_load & one PS O/P UART is shown in separate figures. Figure presents the
which serially fed to the receiver.3 bit down counter with 1 simulation result of the transmitter section and figure13
CLK delay is connected to the Reg_load of PISO. Now when represents that of the receiver section.
sel is zero O/P from DFF is fed to the receiver serially with
every count of the down counter (counter CLK is the trigger When the trg signal goes high, a new data is obtained from the
signal from comparator). Now when counter value goes to LFSR which is fed in parallel to the input of the transmitter.
zero i.e 8 bit data has been send to the receiver then PISO will After a certain number of clock cycles, the same data is
send all 8 bit data parallel to the transmitter in one clock obtained at the output of the transmitter as serial data. This
period. serial data is shifted in the SIPO of the comparator and this is
the sipo_op data. This sipo_op is compared with the ROM
data (romd). The shaded regions in the figure shows the time
SIMULATION RESULT of comparison. Depending on the comparison, the result (i.e.
The simulation results are presented in the figure 7.2. We can rslt) is generated. If the both sipo_op and romd are same then
observe that when the trigger signal goes high then only a new rslt=1, else rslt=0.
value is generated in the LFSR. This LFSR will generate (28-
As the receiver provides 8-bit parallel output, a SIPO is not
1) different pseudorandom values, and only some of them
required in this case. The output from the receiver “rop” is
have been shown in the simulation result. The parallel output
directly compared with romd. The shaded regions in the figure
“pp” is fed to the transmitter and the serial output is fed to the
too shows the comparison time. In all the shaded regions,
receiver section of the UART.
except the last one romd and rop are same and so the rslt is 1
in all those cases. But in the last comparison, due to the
intentionally stored incorrect data in the ROM the comparison
results in rslt=0. Henceforth comparison procedure is stopped
and the CUT is announced to be faulty.
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Minimum input arrival time before clock: 4.315ns
Maximum output required time after clock: 9.385ns
Maximum combinational path delay: 9.357ns
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Total 9.357ns (6.596ns logic, 2.761ns route)
(70.5% logic, 29.5% route)
Figure13. Simulation result of BIST enabled UART Receiver CPU : 10.80 / 11.06 s | Elapsed : 11.00 / 11.00 s
Total memory usage is 181896 kilobytes
VII. CONCLUSION Number of errors : 0 ( 0 filtered)
This paper implements the VHDL language based coding for Number of warnings : 11 ( 0 filtered)
BIST technique on UART. UART transmitter and receiver Number of infos : 6 ( 0 filtered)
sections are differently tested by BIST technique. Clock period: 2.633ns (frequency: 379.795MHz)
The transmitter is given a parallel 8 bit input and the serial Total number of paths / destination ports: 6 / 6
output of the transmitter is checked with the respective ideal
output stored in the ROM. The receiver is given a serial 8 bit A future BIST tester should have very short test time since this
input and the parallel output of the receiver is checked with ultimately determines the final testing cost. We need high-
the respective ideal output stored in the ROM. quality test algorithms, those with high coverage which has
The checking part is done by comparator section. It compares high correlation to yield. The hardware needs to be simple
the receiver or transmitter output with the corresponding data since this determine the speed and area overhead of the tester.
stored in the ROM. Automatic generation that can ease design efforts will soon
Using memory BIST has various advantages such as no demonstrate itself a great value due to the ever increasing
external test equipment, reduced development efforts, at-speed time-to-market pressure. The BIST circuit should possess
tests. However, there are many challenges associated with it certain degree of self-reparability to improve the fault-
such as silicon area overhead, extra pins and routing. In tolerance and increase reliability. Finally, a flexible BIST that
addition, the testability of the test hardware itself is another can adapt to engineering and algorithmic changes will greatly
difficult task. reduce system design cost.
An improvement can be made in the field of implementation
of the Test Response Analyser (TRA). Rather than using VIII. REFERENCES
ROM as TRA, Multiple Input Shift Register (MISR) can be
used for the same purpose. [1] Mohd Yamani Idna Idris, Mashkuri Yaacob, Zaidi Razak, “A VHDL
All the simulation result presented in our paper shows that the Implementation Of UART Design with BIST capability”
BIST enabled UART is working well. [2] Dr. T.V.S.P. Gupta, Y. Kumari,M.Asok Kumar”UART realization with
BIST architecture using VHDL” International Journal of Engineering
Hardware test by FPGA Tool(Spartan2E) showed the same
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
result as in the simulation result.
Vol. 3, Issue 1, January -February 2013, pp.636-640
The synthesis report that we got from the XILINX tool shows
[3] M.S. Harvey,Generic UART Manual,Silicon Valley,December 1999
that it provides excellent result compared to the previous[4] [4] P. J. Anderson , “The designer’s guide to VHDL” , Morgan Kaufman ,
work. [5] 2nd edition, 2002.
[5] Neil H.E. Weste, Kim Haase, David Harris , A. Banerjee , “CMOS VLSI
Synthesis Report(Design Summary) Design: A circuits and Systems Perspective”, Pearson Education.
TIMING Constraints: [6] [6] K. Zarrineh, and S. J. Upadhyaya, “On programmable memory built-in
Speed Grade: -4 [7] self test architectures”, Design, Automation and Test in Europe
[8] Conference and Exhibition 1999. Proceedings , 1999, pp. 708 -713.
Minimum period: 5.384ns (Max Frequency: 185.736MHz)