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Operational Amplifier

> Lecture 1

> Lecture 2

> Lecture 3 Analog Circuits

> Lecture 4

> Lecture 5

> Lecture 6

> Lecture 7

> Lecture 8

> Lecture 9 Prof. Pramod Agarwal

>Lecture 10

OPAMP Apllications

>Lecture 11 Department of Electrical Engineering

> Lecture 12

> Lecture 13

> Lecture 14

> Lecture 15 Indian Institute of Technology

> Lecture 16

> Lecture 17

> Lecture 18

> Lecture 19

> Lecture 20

Oscillator

> Lecture 21

> Lecture 22

> Lecture 23

> Lecture 24

> Lecture 25

> Lecture 26

Voltage Regulator

> Lecture 27

> Lecture 28

> Lecture 29

> Lecture 30

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Lecture 1

Operational Amplifiers:

The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over 1MH Z to which feedback is added to

control its overall response characteristic i.e. gain and bandwidth. The op-amp exhibits the gain down to zero frequency.

Such direct coupled (dc) amplifiers do not use blocking (coupling and by pass) capacitors since these would reduce the

amplification to zero at zero frequency. Large by pass capacitors may be used but it is not possible to fabricate large capacitors

on a IC chip. The capacitors fabricated are usually less than 20 pf. Transistor, diodes and resistors are also fabricated on the

same chip.

Differential Amplifiers:

Differential amplifier is a basic building block of an op-amp. The function of a differential amplifier is to amplify the difference

between two input signals.

How the differential amplifier is developed? Let us consider two emitter-biased circuits as shown in fig. 1.

Fig. 1

The two transistors Q 1 and Q 2 have identical characteristics. The resistances of the circuits are equal, i.e. RE1 = R E2 , RC1 = R

C2 and the magnitude of +V CC is equal to the magnitude of –V EE . These voltages are measured with respect to ground.

To make a differential amplifier, the two circuits are connected as shown in fig. 1. The two +V CC and –V EE supply terminals are

made common because they are same. The two emitters are also connected and the parallel combination of RE1 and RE2 is

replaced by a resistance RE. The two input signals v1 & v2 are applied at the base of Q 1 and at the base of Q 2 . The output

voltage is taken between two collectors. The collector resistances are equal and therefore denoted by RC = RC1 = RC2.

Ideally, the output voltage is zero when the two inputs are equal. When v1 is greater then v2 the output voltage with the polarity

shown appears. When v1 is less than v2 , the output voltage has the opposite polarity.

2. Dual input, unbalanced output differential amplifier.

3. Single input balanced output differential amplifier.

4. Single input unbalanced output differential amplifier.

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Lecture 1

Fig. 2

These configurations are shown in fig. 2, and are defined by number of input signals used and the way an output voltage is

measured. If use two input signals, the configuration is said to be dual input, otherwise it is a single input configuration. On the

other hand, if the output voltage is measured between two collectors, it is referred to as a balanced output because both the

collectors are at the same dc potential w.r.t. ground. If the output is measured at one of the collectors w.r.t. ground, the

configuration is called an unbalanced output.

A multistage amplifier with a desired gain can be obtained using direct connection between successive stages of differential

amplifiers. The advantage of direct coupling is that it removes the lower cut off frequency imposed by the coupling capacitors, and

they are therefore, capable of amplifying dc as well as ac input signals.

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Lecture 1

The circuit is shown in fig. 1, v1 and v2 are the two inputs, applied to the bases of Q 1 and Q 2 transistors. The output voltage is

measured between the two collectors C1 and C2 , which are at same dc potentials.

D.C. Analysis:

To obtain the operating point (I CC and V CEQ) for differential amplifier dc equivalent circuit is drawn by reducing the input voltages

v1 and v2 to zero as shown in fig. 3.

Fig. 3

The internal resistances of the input signals are denoted by RS because RS1 = RS2 . Since both emitter biased sections of the

different amplifier are symmetrical in all respects, therefore, the operating point for only one section need to be determined. The

same values of I CQ and V CEQ can be used for second transistor Q 2 .

The value of RE sets up the emitter current in transistors Q 1 and Q 2 for a given value of V EE . The emitter current in Q 1 and Q 2

are independent of collector resistance RC .

The voltage at the emitter of Q 1 is approximately equal to -V BE if the voltage drop across R is negligible. Knowing the value of I C

the voltage at the collector V C is given by

V C =V CC – I C RC

and V CE = V C – V E

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Lecture 1

= V CC – I C RC + V BE

V CE = V CC + V BE – I C RC (E-2)

From the two equations V CEQ and I CQ can be determined. This dc analysis applicable for all types of differential amplifier.

Example - 1

The following specifications are given for the dual input, balanced-output differential amplifier of fig.1:

RC = 2.2 kΩ, RB = 4.7 kΩ, Rin 1 = Rin 2 = 50 Ω , +V CC = 10V, -V EE = -10 V, βdc =100 and V BE = 0.715V.

Determine the operating points (I CQ and V CEQ) of the two transistors.

Solution:

The values of I CQ and V CEQ are same for both the transistors.

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Lecture 2

The circuit is shown in fig. 1 v1 and v2 are the two inputs, applied to the bases of Q 1 and Q 2 transistors. The output voltage is

measured between the two collectors C1 and C2 , which are at same dc potentials.

Fig. 1

A.C. Analysis :

In previous lecture dc analysis has been done to obtain the operatiing point of the two transistors.

To find the voltage gain A d and the input resistance Ri of the differential amplifier, the ac equivalent circuit is drawn using r-

parameters as shown in fig. 2. The dc voltages are reduced to zero and the ac equivalent of CE configuration is used.

Fig. 2

Since the two dc emitter currents are equal. Therefore, resistance r' e1 and r' e2 are also equal and designated by r' e . This voltage

across each collector resistance is shown 180° out of phase with respect to the input voltages v1 and v2 . This is same as in CE

configuration. The polarity of the output voltage is shown in Figure. The collector C2 is assumed to be more positive with respect

to collector C1 even though both are negative with respect to to ground.

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Lecture 2

Again, assuming RS1 / b and RS2 / b are very small in comparison with RE and re ' and therefore neglecting these terms,

V O = V C2 - V C1

Thus a differential amplifier amplifies the difference between two input signals. Defining the difference of input signals as vd = v1 –

v2 the voltage gain of the dual input balanced output differential amplifier can be given by

(E-2)

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Lecture 2

Differential input resistance is defined as the equivalent resistance that would be measured at either input terminal with the other

terminal grounded. This means that the input resistance Ri1 seen from the input signal source v1 is determined with the signal

source v2 set at zero. Similarly, the input signal v1 is set at zero to determine the input resistance Ri2 seen from the input signal

source v2 . Resistance RS1 and RS2 are ignored because they are very small.

Substituting ie1 ,

Similarly,

To get very high input impedance with differential amplifier is to use Darlington transistors. Another ways is to use FET.

Output Resistance:

Output resistance is defined as the equivalent resistance that would be measured at output terminal with respect to ground.

Therefore, the output resistance RO1 measured between collector C1 and ground is equal to that of the collector resistance RC .

Similarly the output resistance RO2 measured at C2 with respect to ground is equal to that of the collector resistor RC .

The current gain of the differential amplifier is undefined. Like CE amplifier the differential amplifier is a small signal amplifier. It is

generally used as a voltage amplifier and not as current or power amplifier.

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Lecture 2

Example - 1

The following specifications are given for the dual input, balanced-output differential amplifier: RC = 2.2 kΩ, RB = 4.7 kΩ, Rin 1 =

Rin 2 = 50Ω, +V CC = 10V, -V EE = -10 V, βdc =100 and V BE = 0.715V.

b. Determine the input resistance

c. Determine the output resistance.

Solution:

(a). The parameters of the amplifiers are same as discussed in example-1 of lecture-1. The operating point of the two transistors

obtained in lecture-1 are given below

I CQ = 0.988 mA

V CEQ=8.54V

Therefore, substituting the known values in voltage gain equation (E-2), we obtain

b). The input resistance seen from each input source is given by (E-3) and (E-4):

(c) The output resistance seen looking back into the circuit from each of the two output terminals is given by (E-5)

Example - 2

a. Determine the output voltage (vo ) if vin 1 = 50mV peak to peak (pp) at 1 kHz and vin 2 = 20 mV pp at 1 kHz.

b. What is the maximum peal to peak output voltage without clipping?

Solution:

(a) In Example-1 we have determined the voltage gain of the dual input, balanced output differential amplifier. Substituting this

voltage gain (Ad = 86.96) and given values of input voltages in (E-1), we get

(b) Note that in case of dual input, balanced output difference amplifier, the output voltage vo is measured across the collector.

Therefore, to calculate the maximum peak to peak output voltage, we need to determine the voltage drop across each collector

resistor:

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Lecture 2

This means that the maximum change in voltage across each collector resistor is ± 2.17 (ideally) or 4.34 V PP . In other words, the

maximum peak to peak output voltage with out clipping is (2) (4.34) = 8.68 V PP .

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Lecture 3

Fig. 1

V O = A d (v1 – v2 )

When v2 = 0, vO = A d v1

& when v1 = 0, vO = - A d v2

Therefore the input voltage v1 is called the non inventing input because a positive voltage v1 acting alone produces a positive

output voltage vO. Similarly, the positive voltage v2 acting alone produces a negative output voltage hence v2 is called inverting

input. Consequently B 1 is called noninverting input terminal and B 2 is called inverting input terminal.

A common mode signal is one that drives both inputs of a differential amplifier equally. The common mode signal is interference,

static and other kinds of undesirable pickup etc.

The connecting wires on the input bases act like small antennas. If a differential amplifier is operating in an environment with lot

of electromagnetic interference, each base picks up an unwanted interference voltage. If both the transistors were matched in all

respects then the balanced output would be theoretically zero. This is the important characteristic of a differential amplifier. It

discriminates against common mode input signals. In other words, it refuses to amplify the common mode signals.

The practical effectiveness of rejecting the common signal depends on the degree of matching between the two CE stages

forming the differential amplifier. In other words, more closely are the currents in the input transistors, the better is the common

mode signal rejection e.g. If v1 and v2 are the two input signals, then the output of a practical op-amp cannot be described by

simply

v0 = A d (v1 – v2 )

In practical differential amplifier, the output depends not only on difference signal but also upon the common mode signal

(average).

vd = (v1 – vd )

and vC = ½ (v1 + v2 )

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Lecture 3

vO = A 1 v1 + A 2 v2

Where A 1 & A 2 are the voltage amplification from input 1(2) to output under the condition that input 2 (1) is grounded.

The voltage gain for the difference signal is A d and for the common mode signal is A C .

The ability of a differential amplifier to reject a common mode signal is expressed by its common mode rejection ratio (CMRR). It

is the ratio of differential gain A d to the common mode gain A C .

Therefore, the differential amplifier should be designed so that r is large compared with the ratio of the common mode signal to

the difference signal. If r = 1000, vC = 1mV, vd = 1 m V, then

It is equal to first term. Hence for an amplifier with r = 1000, a 1m V difference of potential between two inputs gives the same

output as 1mV signal applied with the same polarity to both inputs.

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Lecture 3

In this case, two input signals are given however the output is measured at only one of the two-collector w.r.t. ground as shown in

fig. 2. The output is referred to as an unbalanced output because the collector at which the output voltage is measured is at some

finite dc potential with respect to ground..

Fig. 2

In other words, there is some dc voltage at the output terminal without any input signal applied. DC analysis is exactly same as

that of first case.

AC Analysis:

The voltage gain is half the gain of the dual input, balanced output differential amplifier. Since at the output there is a dc error

voltage, therefore, to reduce the voltage to zero, this configuration is normally followed by a level translator circuit.

By using external resistors R'E in series with each emitter, the dependence of voltage gain on variations of r' e can be reduced. It

also increases the linearity range of the differential amplifier.

Fig. 3, shows the differential amplifier with swamping resistor R'E. The value of R'E is usually large enough to swamp the effect

of r' e .

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Lecture 3

Fig. 3

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Lecture 3

Example-1

Consider example-1 of lecture-2. The specifications are given again for the dual input, unbalanced-output differential amplifier:

RC = 2.2 kΩ, RB= 4.7 kΩ, Rin1 = Rin2 = 50Ω, +V CC = 10V, -V EE = -10 V, βdc =100 and V BE = 0.715V.

Determine the voltage gain, input resistance and the output resistance.

Solution:

Since the component values remain unchanged and the biasing arrangement is same, the I CQ and V CEQ values as well as input

and output resistance values for the dual input, unbalanced output configuration must be the same as those for the dual input,

balanced output configuration.

Thus, I CQ = 0.988 mA

V CEQ = 8.54 V

Ri1 = Ri2 = 5.06 kΩ

Ro = 2.2 kΩ

The voltage gain of the dual input, unbalanced output differential amplifier is given by

Example-2

Solution:

Because the same biasing arrangement and same component values are used in both configurations, the results obtained in

Example-1 for the dual input, balanced output configuration are also valid for the single input, balanced output configuration.

That is,

I CQ= 0.988 mA

V CEQ = 8.54 V

V d = 86.96

Ri = 5.06 kΩ

Ro1 = Ro2 = 2.2 kΩ

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Lecture 4

In the dc analysis of differential amplifier, we have seen that the emitter current I E depends upon the value of bdc . To make

operating point stable I E current should be constant irrespective value of bdc .

For constant I E, RE should be very large. This also increases the value of CMRR but if RE value is increased to very large value,

I E (quiescent operating current) decreases. To maintain same value of I E, the emitter supply V EE must be increased. To get very

high value of resistance RE and constant I E, current, current bias is used.

Figure 5.1

Fig. 1, shows the dual input balanced output differential amplifier using a constant current bias. The resistance RE is replace by

constant current transistor Q 3 . The dc collector current in Q 3 is established by R1 , R2 , & RE.

Because the two halves of the differential amplifiers are symmetrical, each has half of the current I C3.

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Lecture 4

The collector current, I C3 in transistor Q 3 is fixed because no signal is injected into either the emitter or the base of Q 3 .

Besides supplying constant emitter current, the constant current bias also provides a very high source resistance since the ac

equivalent or the dc source is ideally an open circuit. Therefore, all the performance equations obtained for differential amplifier

using emitter bias are also valid.

As seen in I E expressions, the current depends upon V BE3. If temperature changes, V BE changes and current I E also changes.

To improve thermal stability, a diode is placed in series with resistance R1 as shown in fig. 2.

Fig. 2

This helps to hold the current I E3 constant even though the temperature changes. Applying KVL to the base circuit of Q 3 .

Therefore, the current I E3 is constant and independent of temperature because of the added diode D. Without D the current

would vary with temperature because V BE3 decreases approximately by 2mV/° C. The diode has same temperature dependence

and hence the two variations cancel each other and I E3 does not vary appreciably with temperature. Since the cut – in voltage

V D of diode approximately the same value as the base to emitter voltage V BE3 of a transistor the above condition cannot be

satisfied with one diode. Hence two diodes are used in series for V D . In this case the common mode gain reduces to zero.

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Lecture 4

Some times zener diode may be used in place of diodes and resistance as shown

in fig. 3. Zeners are available over a wide range of voltages and can have

matching temperature coefficient

Fig. 3

The value of R2 is selected so that I 2 » 1.2 I Z(min) where I Z is the minimum current required to cause the zener diode to conduct

in the reverse region, that is to block the rated voltage V Z .

Current Mirror:

The circuit in which the output current is forced to equal the input current is said to be a current mirror circuit. Thus in a current

mirror circuit, the output current is a mirror image of the input current. The current mirror circuit is shown in fig. 4.

Fig. 4

Once the current I 2 is set up, the current I C3 is automatically established to be nearly equal to I 2 . The current mirror is a special

case of constant current bias and the current mirror bias requires of constant current bias and therefore can be used to set up

currents in differential amplifier stages. The current mirror bias requires fewer components than constant current bias circuits.

Since Q3 and Q4 are identical transistors the current and voltage are approximately same

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Lecture 4

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Lecture 4

Example - 1

5 according to the following specifications.

(a). Emitter current -I E = 5 mA

(b). Zener diode with V z = 4.7 V and I z = 53 mA.

(c). βac = βdc = 100, V BE = 0.715V

(d). Supply voltage - V EE = - 9 V.

Solution:

Fig. 5

Practically we use R2 = 68 Ω

The designed component values are:

RE = 860 Ω

R2 = 68 Ω

Fig. 6

Example - 2

Design the dual-input balanced output differential amplifier using the diode constant current bias to meet the following specifications.

1. supply voltage = ± 12 V.

2. Emitter current I E in each differential amplifier transistor = 1.5 mA.

3. Voltage gain ≤ 60.

Solution:

diode D1 and D2 that is V D = V BE3, then

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Lecture 4

Fig. 7

To obtain the differential gain of 60, the required value of the collector

resistor is

The following fig. 7 shows the dual input, balanced output differential

amplifier with the designed component values as RC = 1K, RE = 240

Ω, and R2 = 3.6KΩ.

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Lecture 5

An operational amplifier is a direct coupled high gain amplifier consisting of one or more differential (OPAMP) amplifiers and

followed by a level translator and an output stage. An operational amplifier is available as a single integrated circuit package.

Fig. 1

The input stage is a dual input balanced output differential amplifier. This stage provides most of the voltage gain of the amplifier

and also establishes the input resistance of the OPAMP.The intermediate stage of OPAMP is another differential amplifier which

is driven by the output of the first stage. This is usually dual input unbalanced output.

Because direct coupling is used, the dc voltage level at the output of intermediate stage is well above ground potential. Therefore

level shifting circuit is used to shift the dc level at the output downward to zero with respect to ground. The output stage is

generally a push pull complementary amplifier. The output stage increases the output voltage swing and raises the current

supplying capability of the OPAMP. It also provides low output resistance.

Level Translator:

Because of the direct coupling the dc level at the emitter rises from

stages to stage. This increase in dc level tends to shift the operating

point of the succeeding stages and therefore limits the output voltage

swing and may even distort the output signal.

To shift the output dc level to zero, level translator circuits are used.

An emitter follower with voltage divider is the simplest form of level

translator as shown in fig. 2.

Thus a dc voltage at the base of Q produces 0V dc at the output. It is

decided by R1 and R2 . Instead of voltage divider emitter follower

either with diode current bias or current mirror bias as shown in fig. 3

may be used to get better results.

In this case, level shifter, which is common collector amplifier, shifts

the level by 0.7V. If this shift is not sufficient, the output may be taken Fig. 2

at the junction of two resistors in the emitter leg.

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Lecture 5

Fig. 3

Fig. 4, shows a complete OPAMP circuit having input different amplifiers with balanced output, intermediate stage with

unbalanced output, level shifter and an output amplifier.

Fig. 4

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Lecture 5

Example-1:

The collector current and collector to emitter voltage for each transistor.

The overall voltage gain.

The input resistance.

The output resistance.

Assume that for the transistors used hFE = 100 and V BE = 0.715V

Fig. 5

Solution:

(a). To determine the collector current and collector to emitter voltage of transistors Q 1 and Q 2 , we assume that the inverting and

non-inverting inputs are grounded. The collector currents (I C ≈ I E) in Q 1 and Q 2 are obtained as below:

Now, we can calculate the voltage between collector and emitter for Q 1 and Q 2 using the collector current as follows:

Next, we will determine the collector current in Q 3 and Q 4 by writing the Kirchhoff's voltage equation for the base emitter loop of

the transistor Q 3 :

10 – (2.2kΩ) (0.988mA) - 0.715 - (100) (I E3 ) – (30kΩ) I E3 + 10=0

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Lecture 5

= 9.32 V

Therefore,

I CQ = 0.988 mA

V CEQ = 8.545 V

and for Q 3 and Q 4 :

I CQ = 0.569 mA

V CEQ = 2.2 V

[Note that the output terminal (VC4) is at 9.32 V and not at zero volts.]

(b). First, we calculate the ac emitter resistance r' e of each stage and then its voltage gain.

The first stage is a dual input, balanced output differential amplifier, therefore, its voltage gain is

Where

The second stage is dual input, unbalanced output differential amplifier with swamping resistor R'E, the voltage gain of which is

Thus we can obtain a higher voltage gain by cascading differential amplifier stages.

(c).The input resistance of the cascaded differential amplifier is the same as the input resistance of the first stage, that is

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Lecture 5

(d). The output resistance of the cascaded differential amplifier is the same as the output resistance of the last stage. Hence,

RO = RC = 1.2 kΩ

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Lecture 5

Example-2:

For the circuit show in fig. 6, it is given that β =100, V BE =0715V. Determine

The overall voltage gain

The maximum peak to peak output voltage swing.

Fig. 6

Solution:

(a). The base currents of transistors are neglected and V BE drops of all transistors are assumed same.

and

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Lecture 5

(c). The maximum peak to peak output votage swing = Vopp = 2 (VC7 - V E7 )

= 2 x (5.52 - 3.325)

= 4.39 V

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Lecture 6

741c is most commonly used OPAMP available in IC package. It is an 8-pin DIP chip.

Parameters of OPAMP:

that must be applied between the two input

terminals of an OPAMP to null or zero the

output fig. 2, shows that two dc voltages are

applied to input terminals to make the output

zero.

V io = V dc1 – V dc2

represents the source resistance. V io is the

difference of V dc1 and V dc2 . It may be positive

or negative. For a 741C OPAMP the maximum

value of V io is 6mV. It means a voltage ± 6 mV

is required to one of the input to reduce the Fig. 2

output offset voltage to zero. The smaller the

input offset voltage the better the differential

amplifier, because its transistors are more

closely matched.

The input offset current I io is the difference between the currents into inverting and non-inverting terminals of a

balanced amplifier.

I io = | I B1 – I B2 |

The I io for the 741C is 200nA maximum. As the matching between two input terminals is improved, the difference

between I B1 and I B2 becomes smaller, i.e. the I io value decreases further.For a precision OPAMP 741C, I io is 6

nA

The input bias current I B is the average of the current entering the input terminals of a balanced amplifier i.e.

I B = (I B1 + I B2 ) / 2

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Lecture 6

Ri is the equivalent resistance that can be measured at either the inverting or non-inverting input terminal with the

other terminal grounded. For the 741C the input resistance is relatively high 2 MΩ. For some OPAMP it may be up

to 1000 G ohm.

Ci is the equivalent capacitance that can be measured at either the inverting and noninverting terminal with the

other terminal connected to ground. A typical value of Ci is 1.4 pf for the 741C.

741 OPAMP have offset voltage null capability. Pins 1 and 5 are marked offset null for this purpose. It can be done

by connecting 10 K ohm pot between 1 and 5 as shown in fig. 3.

Fig. 3

By varying the potentiometer, output offset voltage (with inputs grounded) can be reduced to zero volts. Thus the offset voltage

adjustment range is the range through which the input offset voltage can be adjusted by varying 10 K pot. For the 741C the offset

voltage adjustment range is ± 15 mV.

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Lecture - 6: Practical Operational Amplifier

Parameters of OPAMP:

7. Input Voltage Range :

Input voltage range is the range of a common mode input signal for which a differential amplifier remains linear. It is used to determine the degree of

matching between the inverting and noninverting input terminals. For the 741C, the range of the input common mode voltage is ± 13V maximum.

This means that the common mode voltage applied at both input terminals can be as high as +13V or as low as –13V.

CMRR is defined as the ratio of the differential voltage gain Ad to the common mode voltage gain ACM

CMRR = Ad / ACM.

For the 741C, CMRR is 90 dB typically. The higher the value of CMRR the better is the matching between two input terminals and the smaller is the

output common mode voltage.

SVRR is the ratio of the change in the input offset voltage to the corresponding change in power supply voltages. This is expressed in m V / V or in

decibels, SVRR can be defined as

SVRR = D Vio / D V

Where D V is the change in the input supply voltage and D Vio is the corresponding change in the offset voltage.

For 741C, SVRR is measured for both supply magnitudes increasing or decreasing simultaneously, with R3 £ 10K. For same OPAMPS, SVRR is

separately specified as positive SVRR and negative SVRR.

Since the OPAMP amplifies difference voltage between two input terminals, the voltage gain of the amplifier is defined as

Because output signal amplitude is much large than the input signal the voltage gain is commonly called large signal voltage gain. For 741C is

voltage gain is 200,000 typically.

The ac output compliance PP is the maximum unclipped peak to peak output voltage that an OPAMP can produce. Since the quiescent output is

ideally zero, the ac output voltage can swing positive or negative. This also indicates the values of positive and negative saturation voltages of the

OPAMP. The output voltage never exceeds these limits for a given supply voltages +VCC and –VEE. For a 741C it is ± 13 V.

RO is the equivalent resistance that can be measured between the output terminal of the OPAMP and the ground. It is 75 ohm for the 741C OPAMP.

Example - 1

Determine the output voltage in each of the following cases for the open loop differential amplifier of fig. 4:

b. vin 1 = 10 mV rms, vin 2= 20 mV rms

Fig. 4

Specifications of the OPAMP are given below:

A= 200,000, Ri = 2 M Ω , R O = 75Ω, + VCC = + 15 V, - VEE = - 15 V, and output voltage swing = ± 14V.

Solution:

(a). The output voltage of an OPAMP is given by

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Remember that vo = 2.4 V dc with the assumption that the dc output voltage is zero when the input signals are zero.

(b). The output voltage equation is valid for both ac and dc input signals. The output voltage is given by

Thus the theoretical value of output voltage vo = -2000 V rms. However, the OPAMP saturates at ± 14 V. Therefore, the actual output waveform will be clipped as

shown fig. 5. This non-sinusoidal waveform is unacceptable in amplifier applications.

Fig. 5

13. Output Short circuit Current :

In some applications, an OPAMP may drive a load resistance that is approximately zero. Even its output impedance is 75 ohm but cannot supply

large currents. Since OPAMP is low power device and so its output current is limited. The 741C can supply a maximum short circuit output current of

only 25mA.

IS is the current drawn by the OPAMP from the supply. For the 741C OPAMP the supply current is 2.8 m A.

Power consumption (PC) is the amount of quiescent power (vin= 0V) that must be consumed by the OPAMP in order to operate properly. The amount

of power consumed by the 741C is 85 m W.

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Lecture - 6: Practical Operational Amplifier

Parameters of OPAMP:

16. Gain Bandwidth Product:

The gain bandwidth product is the bandwidth of the OPAMP when the open loop voltage gain is reduced to 1. From open loop gain vs frequency

graph At 1 MHz shown in. fig. 6, It can be found 1 MHz for the 741C OPAMP frequency the gain reduces to 1. The mid band voltage gain is 100, 000

and cut off frequency is 10Hz.

Fig. 6

17. Slew Rate:

Slew rate is defined as the maximum rate of change of output voltage per unit of time under large signal conditions and is expressed in volts / m

secs.

Fig. 6

If 'i' is more, capacitor charges quickly. If 'i' is limited to Imax, then rate of change is also limited.

Slew rate indicates how rapidly the output of an OPAMP can change in response to changes in the input frequency with input amplitude constant. The

slew rate changes with change in voltage gain and is normally specified at unity gain.

If the slope requirement is greater than the slew rate, then distortion occurs. For the 741C the slew rate is low 0.5 V / m S. which limits its use in

higher frequency applications.

It is also called average temperature coefficient of input offset voltage or input offset current. The input offset voltage drift is the ratio of the change in

input offset voltage to change in temperature and expressed in m V /° C. Input offset voltage drift = ( D Vio / D T).

Similarly, input offset current drift is the ratio of the change in input offset current to the change in temperature. Input offset current drift = ( D Iio / D T).

For 741C,

D Vio / D T = 0.5 m V / C.

D Iio/ D T = 12 pA/ C.

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Lecture 7

Example - 1

A 100 PF capacitor has a maximum charging current of 150 µA. What is the slew rate?

Solution:

I = 150 µA = 150 x 10 -6 A

Example - 2

An operational amplifier has a slew rate of 2 V / µs. If the peak output is 12 V, what is the power bandwidth?

Solution:

As for output free of distribution, the slews determines the maximum frequency of operation fmax for a desired output swing.

so

Example - 3

For the given circuit in fig. 1. I in(off) = 20 nA. If V in(off) = 0, what is the differential input voltage?. If A = 10 5 , what does the output

offset voltage equal?

Fig. 1

Solutin:

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Lecture 7

I in(off) = 20 nA

V in(off) = 0

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Lecture - 7: Parameters of an OPAMP

Example - 4

R1 = 100Ω, Rf = 8.2 k, RC = 10 k. Assume that the amplifier is nulled at 25°C. If Vin is 20 mV peak sine wave at 100 Hz. Calculate Er, and Vo values at 45°C for the

circuit shown in fig. 2.

Fig. 2

Solution:

Output voltage is 1640 mV peak ac signal which rides either on a +51.44 mV or -51.44 mV dc level.

Example - 5

Design an input offset voltage compensating network for the operational amplifier µA715 for the circuit shown in fig. 3. Draw the complete circuit diagram.

Fig. 3

Solution:

From data sheet we get vin = 5 mV for the operational amplifier µA715.

V = | VCC | = | - VEE | = 15 V

Now,

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If we select RC = 10Ω, the value of Rb should be

Rb = (3000) RC = 30000Ω = 304Ω

Since R > Rmax, let RS = 10 Rmax where Rmax = Ra / 4. Therefore,

If a 124Ω potentiometer is not available, we may prefer to use to the next lower value avilable, such as 104Ω, so that the value of Ra will be larger than Rb by a factor

of 10. If we select a 10 kΩ potentiometer a s the Ra value, Rb is 12 times larger than Ra, Thus

Ra = 10 kΩ potentiometer

Rb = 30 kΩ

Rc = 10Ω.

The final circuit, which also includes the pin connections for the µA715, shown in fig. 4.

Fig. 4

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Lecture -7: Parameters of an OPAMP

An ideal OPAMP would exhibit the following electrical characteristic.

2. Infinite input resistance Ri, so that almost any signal source can drive it and there is no loading of the input source.

3. Zero output resistance RO, so that output can drive an infinite number of other devices.

4. Zero output voltage when input voltage is zero.

5. Infinite bandwidth so that any frequency signal from 0 to infinite Hz can be amplified without attenuation.

6. Infinite common mode rejection ratio so that the output common mode noise voltage is zero.

7. Infinite slew rate, so that output voltage changes occur simultaneously with input voltage changes.

There are practical OPAMPs that can be made to approximate some of these characters using a negative feedback arrangement.

Fig. 5, shows an equivalent circuit of an OPAMP. v1 and v2are the two input voltage voltages. Ri is the input impedance of OPAMP. Ad Vd is an equivalent Thevenin

voltage source and RO is the Thevenin equivalent impedance looking back into the terminal of an OPAMP.

Fig. 5

This equivalent circuit is useful in analyzing the basic operating principles of OPAMP and in observing the effects of standard feedback arrangements

This equation indicates that the output voltage vO is directly proportional to the algebraic difference between the two input voltages. In other words the OPAMP

amplifies the difference between the two input voltages. It does not amplify the input voltages themselves. The polarity of the output voltage depends on the polarity

of the difference voltage vd.

The graphic representation of the output equation is shown in fig. 6 in which the output voltage vO is plotted against differential input voltage vd, keeping gain Ad

constant.

Fig. 6

The output voltage cannot exceed the positive and negative saturation voltages. These saturation voltages are specified for given values of supply voltages. This

means that the output voltage is directly proportional to the input difference voltage only until it reaches the saturation voltages and thereafter the output voltage

remains constant.

Thus curve is called an ideal voltage transfer curve, ideal because output offset voltage is assumed to be zero. If the curve is drawn to scale, the curve would be

almost vertical because of very large values of Ad.

GOTO >> 1 || 2 || 3 || Home

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Lecture - 8: Open loop OPAMP Configuration

In the case of amplifiers the term open loop indicates that no connection, exists between input and output terminals of any type. That is, the output signal is not

fedback in any form as part of the input signal.

In open loop configuration, The OPAMP functions as a high gain amplifier. There are three open loop OPAMP configurations.

Fig. 1, shows the open loop differential amplifier in which input signals vin1 and vin2 are applied to the positive and negative input terminals.

Fig. 1

Since the OPAMP amplifies the difference the between the two input signals, this configuration is called the differential amplifier. The OPAMP amplifies both ac and

dc input signals. The source resistance Rin1 and Rin2 are normally negligible compared to the input resistance Ri. Therefore voltage drop across these

resistances can be assumed to be zero.

Therefore

vo = Ad (vin1 – vin2 )

If the input is applied to only inverting terminal and non-inverting terminal is grounded then it is called inverting amplifier.This configuration is shown in fig. 2.

v1= 0, v2 = vin.

vo = -Ad vin

Fig. 2

The negative sign indicates that the output voltage is out of phase with respect to input 180 ° or is of opposite polarity. Thus the input signal is amplified and

inverted also.

In this configuration, the input voltage is applied to non-inverting terminals and inverting terminal is ground as shown in fig. 3.

v1 = +vin v2 = 0

vo = +Ad vin

This means that the input voltage is amplified byAd and there is no phase reversal at the output.

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Fig. 3

In all there configurations any input signal slightly greater than zero drive the output to saturation level. This is because of very high gain. Thus when operated in

open-loop, the output of the OPAMP is either negative or positive saturation or switches between positive and negative saturation levels. Therefore open loop op-

amp is not used in linear applications.

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Lecture - 8: Open loop OPAMP Configuration

The gain of the OPAMP can be controlled if fedback is introduced in the circuit. That is, an output signal is fedback to the input either directly or via another network.

If the signal fedback is of opposite or out phase by 180° with respect to the input signal, the feedback is called negative fedback.

An amplifier with negative fedback has a self-correcting ability of change in output voltage caused by changes in environmental conditions. It is also known as

degenerative fedback because it reduces the output voltage and,in tern,reduces the voltage gain.

If the signal is fedback in phase with the input signal, the feedback is called positive feedback. In positive feedback the feedback signal aids the input signal. It is

also known as regenerative feedback. Positive feedback is necessary in oscillator circuits.

The negative fedback stabilizes the gain, increases the bandwidth and changes, the input and output resistances. Other benefits are reduced distortion and

reduced offset output voltage. It also reduces the effect of temperature and supply voltage variation on the output of an op-amp.

A closed loop amplifier can be represented by two blocks one for an OPAMP and other for a feedback circuits. There are four following ways to connect these

blocks. These connections are shown in fig. 4.

These connections are classified according to whether the voltage or current is feedback to the input in series or in parallel:

Voltage – shunt feedback

Current – series feedback

Current – shunt feedback

Fig. 4

In all these circuits of fig. 4, the signal direction is from input to output for OPAMP and output to input for feedback circuit. Only first two, feedback in circuits are

important.

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Lecture - 8: Open loop OPAMP Configuration

Voltage series feedback:

It is also called non-inverting voltage feedback circuit. With this type of feedback, the input signal drives the non-inverting input of an amplifier; a fraction of the output

voltage is then fed back to the inverting input. The op-amp is represented by its symbol including its large signal voltage gain Ad or A, and the feedback circuit is

composed of two resistors R1 and Rf. as shown in fig. 5

Fig. 5

The feedback voltage always opposes the input voltage, (or is out of phase by 180° with respect to input voltage), hence the feedback is said to be negative.

The closed loop voltage gain is given by

The product Aand B is called loop gain. The gain loop gain is very large such that AB >> 1

This shows that overall voltage gain of the circuit equals the reciprocal of B, the feedback gain. It means that closed loop gain is no longer dependent on the gain of

the op-amp, but depends on the feedback of the voltage divider. The feedback gain B can be precisely controlled and it is independent of the amplifier.

Physically, what is happening in the circuit? The gain is approximately constant, even though differential voltage gain may change. Suppose A increases for some

reasons (temperature change). Then the output voltage will try to increase. This means that more voltage is fedback to the inverting input, causing vd voltage to

decrease. This almost completely offset the attempted increases in output voltage.

Similarly, if A decreases, The output voltage decreases. It reduces the feedback voltage vf and hence, vd voltage increases. Thus the output voltage increases

almost to same level.

Again considering the voltage equation,

vO = Ad vd

or vd = vO / Ad

Since Ad is very large (ideally infinite)

\ vd » 0.

and v1 = v2 (ideal).

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This says, that the voltage at non-inverting input terminal of an op-amp is approximately equal to that at the inverting input terminal provided that Ad is very large.

This concept is useful in the analysis of closed loop OPAMP circuits. For example, ideal closed loop voltage again can be obtained using the results

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Lecture - 9: Closed Loop Amplifier

fig. 1, shows a voltage series feedback with the OPAMP equivalent circuit.

Fig. 1

In this circuit Ri is the input resistance (open loop) of the OPAMP and Rif is the input resistance of the feedback amplifier. The input resistance with feedback is

defined as

Since AB is much larger than 1, which means that Rif is much larger that Ri. Thus Rif approaches infinity and therefore, this amplifier approximates an ideal voltage

amplifier.

Output resistance is the resistance determined looking back into the feedback amplifier from the output terminal. To find output resistance with feedback Rf, input

vin is reduced to zero, an external voltage Vo is applied as shown in fig. 2.

Fig. 2

The output resistance (Rof ) is defined as

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This shows that the output resistance of the voltage series feedback amplifier is ( 1 / 1+AB ) times the output resistance Ro of the op-amp. It is very small because

(1+AB) is very large. It approaches to zero for an ideal voltage amplifier.

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Lecture - 9: Closed Loop Amplifier

The final stage of an OPAMP has non-linear distortion when the signal swings over most of the ac load line. Large swings in current cause the r'e of a transistor to

change during the cycle. In other words, the open loop gain varies throughout the cycle of when a large signal is being applied. It is this changing voltage gain that

is a source of the non-linear distortion.

Noninverting voltage feedback reduces non-linear distortion because the feedback stabilizes the closed loop voltage gain, making it almost independent of the

changes in open loop voltage gain. As long as loop gain, is much greater than 1, the output voltage equals 1/B times the input voltage. This implies that output will

be a more faithful reproduction of the input .

Consider, under large signal conditions, the open loop OPAMP circuit produces a distortion voltage, designated vdist. It can be represented by connecting a source

vdist in series with Avd. Without negative feedback all the distortion voltage vdist appears at the output. But with negative feedback, a fraction of vdist is feedback to

inverting input. This is amplified and arrives at the output with inverted phase almost completely canceling the original distortion produced by the output stage.

The first term is the amplified output voltage. The second term in the distortion that appears at the final output. The distortion voltage is very much, reduced because

AB>>1

The bandwidth of an amplifier is defined as the band of frequencies for which the gain remains constant. Fig. 3, shows the open loop gain vs frequency curve of

741C OPAMP. From this curve for a gain of 2 x 105 the bandwidth is approximately 5Hz. On the other hand, the bandwidth is approximately 1MHz when the gain is

unity.

Fig. 3

The frequency at which gain equals 1 is known as the unity gain bandwidth. It is the maximum frequency the OPAMP can be used for.

Furthermore, the gain bandwidth product obtained from the open loop gain vs frequency curve is equal to the unity gain bandwidth of the OPAMP.

Since the gain bandwidth product is constant obviously the higher the gain the smaller the bandwidth and vice versa. If negative feedback is used gain decrease

from Ato A/ (1+AB). Therefore the closed loop bandwidth increases by (1+AB).

ff= fo (1+AB)

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Lecture - 9: Closed Loop Amplifier

In an OPAMP even if the input voltage is zero an output voltage can exist. There

are three cause of this unwanted offset voltage.

2. Input bias voltage.

3. Input offset current.

series with the open loop output AVd. The actual output offset voltage with

negative feedback is smaller. The reasoning is similar to that given for

distortion. Some of the output offset voltage is fed back to the inverting input.

After amplification an out of phase voltage arrives at the output canceling most

of the original output offset voltage.

When loop gain AB is much greater than 1, the closed loop output offset

voltage is much smaller than the open loop output offset voltage.

Fig. 4

Voltage Follower:

The lowest gain that can be obtained from a non-inverting amplifier with feedback is 1. When the non-inverting amplifier gives unity gain, it is called voltage follower

because the output voltage is equal to the input voltage and in phase with the input voltage. In other words the output voltage follows the input voltage.

To obtain voltage follower, R1 is open circuited and Rf is shorted in a negative feedback amplifier of fig. 4. The resultant circuit is shown in fig. 5.

v1 = vin

v2 =vout

v1 = v2 if A>> 1

vout = vin.

Af = 1 / B = 1

Fig. 5

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Lecture - 10: Voltage Shunt Feedback

Fig. 1, shows the voltage shunt feedback amplifier using OPAMP.

Fig. 1

The input voltage drives the inverting terminal, and the amplified as well as inverted output signal is also applied to the inverting input via the feedback resistor Rf.

This arrangement forms a negative feedback because any increase in the output signal results in a feedback signal into the inverting input signal causing a

decrease in the output signal. The non-inverting terminal is grounded. Resistor R1 is connected in series with the source.

The closed loop voltage gain can be obtained by, writing Kirchoff's current equation at the input node V2.

The negative sign in equation indicates that the input and output signals are out of phase by 180. Therefore it is called inverting amplifier. The gain can be selected

by selecting Rf and R1 (even < 1).

In the fig. 1, shown earlier, the noninverting terminal is grounded and the- input signal is applied to the inverting terminal via resistor R1. The difference input

voltage vd is ideally zero, (vd= vO/ A) is the voltage at the inverting terminals (v2) is approximately equal to that of the noninverting terminal (v1). In other words, the

inverting terminal voltage (v1) is approximately at ground potential. Therefore, it is said to be at virtual ground.

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Lecture - 10: Voltage Shunt Feedback

To find the input resistance Miller equivalent of the feedback resistor Rf,

is obtained, i.e. Rf is splitted into its two Miller components as shown

in fig. 2. Therefore, input resistance with feedback Rif is then

Fig. 2

The output resistance with feedback Rof is the resistance measured at the

output terminal of the feedback amplifier. The output resistance can be

obtained using Thevenin's equivalent circuit,shown in fig. 3.

iO = ia + ib

Therefore,i.e. iO= ia

vO = RO iO + Avd.

vd= vi – v2 = 0 - B vO

Fig. 3

Similarly, the bandwidth increases by (1+ AB) and total output offset voltage

reduces by (1+AB).

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Lecture - 10: Voltage Shunt Feedback

Example - 1

(a).An inverting amplifier is implemented with R1 = 1K and Rf = 100 K. Find the percentge change in the closed loop gain Ais the open loop gain a changes

from 2 x 105 V / V to 5 x 104 V/V.

(b) Repeat, but for a non-inverting amplifier with R1 = 1K at Rf = 99 K.

Solution: (a). Inverting amplifier

Here Rf = 100 K

R1 = 1K

When,

Here Rf = 99 K

R1 = 1K

Example - 2

An inverting amplifier shown in fig. 4 with R1 = 10Ω and R2 = 1MΩ is driven by a source v1 = 0.1 V. Find the closed loop gain A, the percentage division of Afrom the

ideal value - R2 / R1, and the inverting input voltage VN for the cases A= 100 V/V, 10 5 and 105 V/V.

Solution:

we have

when A= 103,

Fig. 4

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Example - 3

Find VN, V1 and VO for the circuit shown in fig. 5.

Solution:

Applying KCL at N

or 2VN + VN = VO.

VO - VN = 6 V

Therefore, VO = VN + 6 V

Fig. 5

Therefore, VN = Vi = 3 V.

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Lecture 11

The circuit of analog inverter is shown in fig. 1. It is same as inverting voltage amplifier.

voltage is zero.

i.e. vd = 0

Therefore, v1 = v2 = 0

zero. OPAMP do not sink any current.

\ iin= if

vin / R = - vO / Rf

vo = - (Rf / R) vin

Fig. 1

If Rf / R = K (a constant) then the circuit is called inverting

amplifier or scale changer voltages.

Inverting summer:

The configuration is shown in fig. 2. With three input voltages va , vb & vc. Depending upon the value of Rf and the input resistors

Ra , Rb , Rc the circuit can be used as a summing amplifier, scaling amplifier, or averaging amplifier.

drawn by OPAMP is zero. Thus, applying KCL at v2

node

negative sum of all the inputs times the gain of the

circuit Rf/ R; hence the circuit is called a summing

amplifier. When Rf= R then the output voltage is equal

Fig. 2

to the negative sum of all inputs.

vo = -(v a+ vb + vc)

If each input voltage is amplified by a different factor in other words weighted differently at the output, the circuit is called then

scaling amplifier.

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Lecture 11

The circuit can be used as an averaging circuit, in which the output voltage is equal to the average of all the input voltages.

vo = -(va + vb + vc) / 3

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Lecture 11

Noninverting configuration:

If the input voltages are connected to noninverting input through resistors, then the circuit can be used as a summing or

averaging amplifier through proper selection of R1 , R2 , R3 and Rf. as shown in fig. 3.

superposition theorem, the voltage v1 at the noninverting terminal is

given by

Fig. 3

This shows that the output is equal to the average of all input voltages times the gain of the circuit (1+ Rf / R1 ), hence the name

averaging amplifier.

If (1+R f/ R1 ) is made equal to 3 then the output voltage becomes sum of all three input voltages.

vo = v a + vb + vc

Example - 1

Solution:

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Lecture 11

Fig. 4

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Lecture 11

Example - 2

Fig. 5

Solution:

Let's consider of V 1 (singly) by shorting the others i.e. the circuit then looks like as shown in fig. 6.

of

circuit looks like as shown in fig. 7. Fig. 6

Now V O is given by

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Lecture 11

So V O = V 2 + V 4 + V 6 - V 1 - V 3 - V 5 .

Fig. 7

Example - 3

2. Specify resistance not larger than 100 K to achieve A = -200 V / V and Ri = 100 K.

Fig. 8

Solution:

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Lecture 11

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Lecture 12

Differential Amplifier:

Fig. 1

Since there are two inputs superposition theorem can be used to find the output voltage. When V b = 0, then the circuit becomes

inverting amplifier, hence the output due to V a only is

V o(a) = -(Rf / R1 ) V a

Similarly when, V a = 0, the configuration is a inverting amplifier having a voltage divided network at the noninverting input

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Lecture 12

Example - 1

Find vout and iout for the circuit shown in fig. 2. The input voltage is sinusoidal with amplitude of 0.5 V.

Fig. 2

Solution:

We begin by writing the KCL equations at both the + and – terminals of the op-amp.

Therefore,

15 v- = vout

This yields two equations in three unknowns, vout, v+ and v- . The third equation is the relationship between v+ and v- for the ideal

OPAMP,

v+ = v-

Since 2 kΩ resistor forms the load of the op-amp, then the current iout is given by

Example - 2

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Lecture 12

Fig. 3

Solution:

v1 = vx

and v2 = vy

The input impedance of OPAMP is very large and, therefore, the input current of OPAMP is negligible.

Thus

And

or

or

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Lecture 12

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Lecture 12

Integrator:

A circuit in which the output voltage waveform is the integral of the input voltage waveform is called integrator. Fig. 4, shows an

integrator circuit using OPAMP.

Fig. 4

Here, the feedback element is a capacitor. The current drawn by OPAMP is zero and also the V 2 is virtually grounded.

Therefore, i1 = if and v2 = v1 = 0

The output voltage is directly proportional to the negative integral of the input voltage and inversely proportional to the time

constant RC.

If the input is a sine wave the output will be cosine wave. If the input is a square wave, the output will be a triangular wave. For

accurate integration, the time period of the input signal T must be longer than or equal to RC.

Fig. 5, shows the output of integrator for square and sinusoidal inputs.

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Lecture 12

Fig. 5

Example - 3

Solution:

because different input voltage is negligible.

vB = V O / 2

Fig. 6

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Lecture 13

Differentator:

A circuit in which the output voltage waveform is the differentiation of input voltage is called differentiator.as shown in fig. 1.

Fig. 1

The expression for the output voltage can be obtained from the Kirchoff's current equation written at node v2 .

instantaneous rate of change of the input voltage vin with time.

A cosine wave input produces sine output. fig. 1 also shows

the output waveform for different input voltages.

T of the input signal is larger than or equal to Rf C.

T ³ Rf C

frequencies the circuit is highly susceptible at high frequency

noise and noise gets amplified. Both the high frequency noise

and problem can be corrected by additing, few components. as

shown in fig. 2. Fig. 2

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Lecture 13

Fig. 3, shows a voltage to current converter in which load resistor RL is floating (not connected to ground).

The input voltage is applied to the non-inverting input terminal and the feedback voltage across R drives the inverting input

terminal. This circuit is also called a current series negative feedback, amplifier because the feedback voltage across R depends

on the output current iL and is in series with the input difference voltage vd .

vin = vd + vf

vin = vf

vin = R iin

iin = v in / R.

iL = iin = vin ./ R

equation. Therefore, the output current is independent

of the value of load resistance. Thus the input voltage

is converted into current, the source must be capable

of supplying this load current. Fig. 3

Grounded Load:

If the load has to be grounded, then the above circuit cannot be used. The modified circuit is shown in fig. 4.

Since the collector and emitter currents are equal to a close approximation

and the input impedance of OPAMP is very high,the load current also flows

through the feedback resistor R. On account of this, there is still current

feedback, which means that the load current is stabilized.

Since vd = 0

\ v2 = v1 = vin

\ iout = (vCC – vin ) / R

Thus the load current becomes nearly equal to iout. There is a limit to the

output current that the circuit can supply. The base current in the transistor

equals iout / bdc . Since the op-amp has to supply this base current iout /

bdc must be less than I out (max) of the op-amp, typically 10 to 15mA.

increases, the load voltage increases and then the transistor goes into

saturation. Since the emitter is at V in w. r. t. ground, the maximum load

voltage is slightly less than V in.

Fig. 4

In this circuit, because of negative feedback V BE is automatically adjusted. For instance, if the load resistance decreases the load

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Lecture 13

current tries to increase. This means that more voltage is feedback to the inverting input, which decreases V BE just enough to al

most completely nullify the attempted increase in load current. From the output current expression it is clear that as V in increases

the load current decreases.

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Lecture 13

i = vin / R

R = vCC – vin

second op-amp. The inverting voltage is vCC - vin to a

close approximation. This implies that the voltage

across the final R is

iout = vin / R

condition,that I out/ bdc must be less than the I out(max)

of the OPAMP. Furthermore, the load voltage cannot

exceed vCC - vin because of transistor saturation,

therefore I out R must be less than vCC - vin.This current

source produces unidirectional load current. fig. 6,

shows a Howland current source, that can produce a bi- Fig. 5

directional load current.

Fig. 6

positive or negative.

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Lecture 13

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Lecture 14

Fig. 1

Due to virtual ground the current through R is zero and the input current flows through Rf. Therefore,

The lower limit on current measure with this circuit is set by the bias current of the inverting input.

Example –1:

Fig. 2

Solution:

The current through R1 can be obtained from the current divider circuit.

Since, the input impedance of OPAMP is very large, the input current of OPAMP is negligible.

Thus,

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Lecture 14

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Lecture 14

Example - 2

(a). Verify that the circuit shown in fig. 3 has input impedance.

(b). If Z is a capacitor, show that the system behaves as an inductor.

(c). Find the value of C in order to obtain a 1H inductance if R1 = R2 = 1K.

Fig. 3

Solution:

Let the output of OPAMP (1) be v and the output of OPAMP (2) be vo . Since the differential input voltage of the OPAMP is

negligible, therefore, the voltage at the inverting terminal of OPAMP (1)will be vi .

or,

If Z is a capacitor, then Z = 1 / ωC

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Lecture 14

Let L = C R1 R2

(c). Given R1 = R2 = 1 K, L = 1 H

Example - 3

Show that the circuit of fig. 4 is a current divider with io = ii / ( 1 + R2 + R1 ) regardless of the load.

Fig. 4

Solution:

Therefore, V 1 = V L .

Now current is

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Lecture 14

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Lecture 14

Example - 4

Solution:

Here

Fig. 5

(b).

Example - 3

Obtain an expression of the type iO = V i / R - V O / RO for the circuit shown in fig. 6. Hence verify that if R4 / R3 = R2 / R1 the

circuit is a V-I converter with RO =∞ and R = R1 R5 / R2 .

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Lecture 14

Fig. 6

Solution:

Here

where

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Lecture 14

So when

then,

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Lecture 15

Filters:

A filter is a frequency selective circuit that, passes a specified band of frequencies and blocks or attenuates signals of

frequencies out side this band. Filter may be classified on a number of ways.

1. Analog or digital

2. Passive or active

3. Audio or radio frequency

Analog filters are designed to process only signals while digital filters process analog signals using digital technique. Depending

on the type of elements used in their consideration, filters may be classified as passive or active.

Elements used in passive filters are resistors, capacitors and inductors. Active filters, on the other hand, employ transistors or

OPAMPs, in addition to the resistor and capacitors. Depending upon the elements the frequency range is decided.

RC filters are used for audio or low frequency operation. LC filters are employed at RF or high frequencies.

2. High pass filter

3. Band pass filter

4. Band reject filter.

5. All pass filter

Fig. 1, shows the frequency response characteristics of the five types of filter. The ideal response is shown by dashed line. While

the solid lines indicates the practical filter response.

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Lecture 15

Fig. 1

A low pass filter has a constant gain from 0 Hz to a high cutoff frequency f H . Therefore, the bandwidth is f H . At f H the gain is

down by 3db. After that the gain decreases as frequency increases. The frequency range 0 to f H Hz is called pass band and

beyond f H is called stop band.

Similarly, a high pass filter has a constant gain from very high frequency to a low cutoff frequency f L . below f L the gain decreases

as frequency decreases. At f L the gain is down by 3db. The frequency range f L Hz to ∞ is called pass band and bleow f L is called

stop band.

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Lecture 15

Fig. 2, shows a first order low pass Butter-worth filter that uses an RC network for filtering, opamp is used in non-inverting

configuration, R1 and Rf decides the gain of the filter.

According to voltage divider rule, the voltage at the non-inverting terminal is:

Fig. 2

Thus the low pass filter has a nearly constant gain A f from 0 Hz to high cut off frequency f H . At f H the gain is 0.707 A f and after

f H it decreases at a constant rate with an increases in frequency. f H is called cutoff frequency because the gain of filter at this

frequency is reduced by 3dB from 0Hz.

Filter Design:

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Lecture 15

2. Select a value of C less than or equal to 1 µF.

Example - 1

Design a low pass filter at a cutoff frequency of 1 kH z with a pass band gain of 2.

Solution:

Since the pass band gain is 2, R1 and RF must be equal. Let R1 = R2 = 10 kΩ.

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Lecture 15

One advantage of active filter is that it is often quite simple to vary parameter values. As an example, a first-order low-pass filter

with adjustable corner frequency is shown in fig. 3.

Fig. 3

where

Note that we use upper case letters for the voltages since these are functions of s. K is the fraction of V 1 sent to the integrator.

That is, it is the potentiometer ratio, which is a number between 0 and 1.

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Lecture 15

The corner frequency is at KA 2 / RC. Thus, the frequency is adjustable and is proportional to K. Without use of the opamp, we

would normally have a corner frequency which is inversely propostional to the resistor value. With a frequency proportional to K,

we can use a linear taper potentiometer. The frequency is then linearly proportional to the setting of the potentiometer.

Example - 2

Design a first order adjustable low-pass filter with a dc gain of 10 and a corner frequency adjustable from near 0 t0 1 KHz.

Solution:

There are six unknowns in this problems (RA, RF, R1, R2, R and C) and only three equations (gain, frequency and bias balance).

This leaves three parameters open to choice. Suppose we choose the following values:

C = 0.1 µF

R = 10 KΩ

R1 = 10KΩ

The ratio of R2 to R1 is the dc gain, so with a given value of R1 = 10KΩ, R2 must be 100 kΩ. We solve for A 1 and A 2 in the order

to find the ratio, RF / RA.

The maximum corner frequency occurs at K = 1, so this frequency is set to 2π x 1000. Since R and C are known, we find A 2 =

6.28. Since A 2 and A 1 are related by the dc gain, we determine A 1 / A 2 = 10 and A 1 = 62.8. Now, substituting the expression for

A 2 , we find

and since

we find RF / RA = 68. RA is chosen to achieve bias balance. The impedance attached to the non-inverting input is 10 KΩ || 100

KΩ = 10 KΩ.

Fig. 4

If we assume that RF is large compared with RA ( we can check this assumption after solving for these resistors), the parallel

combination will be close to the value of RA. We therefore can choose RA = 10 KΩ. With this choice of RA, RF is found to be

680KΩ and bias balance is achieved. The complete filter is shwn in fig. 4.

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Lecture 16

A stop-band response having a 40-dB/decade at the cut-off frequency is obtained with the second-order low-pass filter. A first

order low-pass filter can be converted into a second-order low-pass filter by using an additional RC network as shown in fig. 1.

Fig. 1 Fig. 2

The gain of the second order filter is set by R1 and RF , while the high cut-ff frequency f H is determined by R2 , C2 , R3 and C3 as

follows:

Furthermore, for a second-order low pass Butterworth response, the voltage gain magnitude is given by

where,

Except for having the different cut off frequency, the frequency response of the second order low pass filter is identical to that of

the first order type as shown in fig. 2.

Filter Design:

The design steps of the second order filter are identical to those of the first order filter as given bellow:

2. To simplify the design calculations, set R2 = R3 = R and C2 = C3 = C. Then choose a value of C less than 1 µF.

4. Finally, because of the equal resistor (R2 = R3 ) and capacitor (C2 = C3 ) values, the pass band voltage gain A F has to be

equal to 1.586. This gain is necessary to guarantee Butterworth response. Therefore, RF = 0.586 R1 . Hence choose a

value of R1 = 100 kΩ and calculate the value of RF .

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Lecture 16

Fig. 3, shows the circuit of first order high pass filter.This is formed by interchanging R and C in low pass filter.

The lower cut off frequency is f L . This is the frequency at which the magnitude of the gain is 0.707 times its pass band value. All

frequencies higher than f L are pass band frequencies with the highest frequency determined by the closed loop bandwidth of the

OPAMP.

Fig. 3

If the two filters (high and low) band pass are connected in series it becomes wide band filter whose gain frequency response is

shown in fig. 4.

Fig. 4

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Lecture 16

Precision Diodes:

If a sinusoid whose peak value is less than the threshold or cut in voltage V d (-0.6V) is applied to the conventional half-wave

rectifier circuit, output will remain zero. In order to be able to rectify small signals (mV), it is necessary to reduce V d . By placing a

diode in the feedback loop of an OPAMP, the cut in voltage is divided by the open loop gain A of the amplifier. Fig. 5, shows an

active diode circuit.

Fig. 5

Hence V D is virtually eliminated and the diode approaches the ideal rectifying element. If the input V in goes positive by at least

V D /A, then the output voltage (=A vd ) exceeds V D and D conducts and thus, provides a negative feedback. Because of the

virtual connection between the two inputs vO= vin-vd =v in- v D / A » vin. Therefore, the circuit acts as voltage follower for positive

signals (above 60 mV=0.6 / 1*105 ) when V in swing negatively, D is OFF and no current is delivered to the external load.

Active Clippers:

By slightly modifying the circuit, an active diode ideal clipper circuit is obtained. Fig. 6, shows an active clipper which clips the

input voltage below vR .

Fig. 6

When vin < V R , then v' is positive and D conducts. Under these conditions, the OPAMP works as a buffer and the output voltage

equals the voltage at non-inverting terminal

V out = V R .

If vin > V R , then v' is negative and D is OFF and vO = vin RL / (RL + R) » V i if R << RL Thus, output follows input for vin > V R and

vO is clamped to V R if vin < V R by about 60 mV. Fig. 7, shows the output waveform of clipper circuit.When D is reverse biased a

large differential voltage may appear between inputs and the OPAMP must be capable to withstand this voltage.

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Lecture 16

Fig. 7

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Lecture 16

Fig. 8 Fig. 9

If vin is positive then output of the OPAMP becomes negative (the non inverting terminal is grounded). Thus diode D2 conducts and provides a

negative feedback. Because of the feedback through D2 a virtual ground exists at the input. Thus diode D1 acts as open circuit. The output

voltage under this condition is given by

vo = v - = 0.

If vin goes negative, then output of the OPAMP becomes positive. Thus D1 is conducting and D2 is off. Thus, the circuit behaves as an

inverting amplifier. The output of the circuit is given by

The resultant output voltage will be positive. If v in is a sinusoid, the circuit performs half wave rectification. The transfer characteristic of the

half wave active rectifier is shown in fig. 9. The output does not depend upon the diode forward voltage (vd ). Thus, because of the high open

loop gain of the OPAMP, the feedback acts to cancel the diode turn-on (forward) voltage. This leads to improved performance since the diode

more closely approximates the ideal device.

The half wave rectified output waveform can be shifted along the vin axis. This is done by using a reference voltage added to the input voltage

of the rectifier as shown in fig. 10. This termed axis shifting. It adds or subtracts a fixed dc voltage to the input signal. This process shifts the

diode turn-on voltage point. If a negative reference voltage, V REF, is applied to the circuit, the diode turns on when the input voltage is still

positive. This shifts the vout/ vin transfer characteristic to the right. If a positive reference voltage is applied, the vout/ vin transfer characteristic

shifts to the left. These shifted characteristics are shown in fig. 10.

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Lecture 16

Fig. 10 Fig. 11

The input-output voltage characteristics can also be shifted up or down. This is termed level shifting and is accomplished by adding a second

OPAMP with a reference voltage added to the negative input terminal as shown in fig. 11.

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Lecture 17

Method 1:

A full wave rectifier, or magnitude operator, produces an output which is the absolute value, or magnitude, of the input signal

waveform. One method of accomplishing full wave rectification is to use two half wave rectifiers. One of these operates on the

positive portion of the input and the second operates on the negative portion. The outputs are summed with proper polarites. Fig.

1 illustrates one such configuration. Note that the resistive network attached to the ouput summing opamp is composed of

resistors of higher value than those attached to the opamp that generates v1 . This is necessary since for negative vin, v2 follows

the curve shown above the node labled v2 . That is, as the input increases in a negative direction, v2 increases in a positive

direction. Since the input impedance to the non-inverting terminal of the summing opamp is high, the voltage, v+ is simply one

half of v2 (i.e., the two 100KΩ resistors form a voltage divider). The voltage at the negative summing terminal, v-, is the same as

v+, and therefore is equal to v2 / 2. Now when vin is negative, D2 is open, and the node v1 is connected to the inverting input of

the first opamp through a 5 KΩ resistor. The inverting input is a virtual ground since the non-inverting input is tied to ground

through a resistor. The result is that the voltage divider formed by the 100 KΩ and 5KΩ resistors. In order to achive a

characteristic resembling that shown in the figure, this voltage divider must have a small ratio, on the order of 1 to 20.

Fig. 1

Method 2:

The method of full wave rectification discussed above requires three separate amplifiers. One simpler circuit or active full wave

rectifier, which makes use of only two OPAMPs, is shown in fig. 2. It rectifies the input with a gain of R / R1 , controllable by one

resistor R1 .

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Lecture 17

Fig. 2

When v in is positive then v' = negative, D1 is ON and D2 is virtual ground at the input to (l). Because D2 is non-conducting, and

since there is no current in the R which is connected to the non-inverting input to (2), therefore, V 1 =0.

Hence, the system consists of two OPAMP in cascade with the gain of A 1 equal to (-R / R1 ) and the gain of A 2 equal to (-R / R)

= -1.

Consider now next half cycle when v in is negative. The v' is positive D1 is OFF and D2 is ON. Because of the virtually ground at

the input to (2) V 2 = V 1 = V

Since the input terminals of (2) are at the same (ground) potential, the current coming to the inverting terminal of (1) is as

indicated in fig. 2.

The output voltage is vo = i R + v where i = v / 2R (because input impedance of OPAMP is very high).

The sign of vo is again positive because vin is negative in this half cycle. Therefore, outputs during two half cycles are same; and

full wave rectified output voltage is obtained also shown in fig. 2.

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Lecture 17

Clampers:

Fig. 3

The first negative half cycle produces a positive OPAMP output, which turns ON the diode. This capacitor charges to the peak of

the input with the polarity shown in fig. 3. Just beyond the negative peak the diode turns off, the feedback loop opens, and the

virtual ground is lost. Therefore,

vout = vin + V P

Since V P is being added to a sinusoidal voltage, the final output waveform is shifted positively through V P volts. The output wave

form swing from 0 to 2VP as shows in fig. 4. Again the reduction of the diode-offset voltage allows clamping with low-level inputs.

During most of the cycle, the OPAMP operates in negative saturation. Right at the negative input peak, the OPAMP produces a

sharp positive going pulse that replaces any change lost by the clamping capacitor between negative input peaks.

Fig. 4

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Lecture 17

Comparators:

An analog comparator has two inputs one is usually a constant reference voltage V R and other is a time varying signal vi and one

output vO. The basic circuit of a comparator is shown in fig. 5.

When the noninverting voltage is larger than the inverting voltage the comparator produces a high output voltage (+V sat ). When

the non-inverting output is less than the inverting input the output is low (-V sat ). Fig. 5, also shows the output of a comparator for

a sinusoidal.

Fig. 5

vO = -V sat if vi > V R

If V R = 0, then slightest input voltage (in mV) is enough to saturate the OPAMP and the circuit acts as zero crossing detector as

shown in fig. 6. If the supply voltages are ±15V, then the output compliance is from approximate – 13V to +13V. The more the

open loop gain of OPAMP, the smaller the voltage required to saturate the output. If vd required is very small then the

characteristic is a vertical line as shown in fig. 6.

Fig. 6

If we want to limit the output voltage of the comparator two voltages (one positive and other negative) then a resistor R and two

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Lecture 17

zener diodes are added to clamp the output of the comparator. The circuit of such comparator is shown in fig. 7, The transfer

characteristics of the circuit is also shown in fig. 7.

Fig. 7

The resistance is chosen so that the zener operates in zener region. When V R = 0 then the output changes rapidly from one state

to other very rapidly every time that the input passes through zero as shown in fig. 8.

Fig. 8

Such a configuration is called zero crossing detector. If we want pulses at zero crossing then a differentiator and a series diode is

connected at the output. It produces single pulses at the zero crossing point in every cycle.

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Lecture 18

Schmitt Trigger:

If the input to a comparator contains noise, the output may be erractive when vin is near a trip point. For instance, with a zero

crossing, the output is low when vin is positive and high when vin is negative. If the input contains a noise voltage with a peak of

1mV or more, then the comparator will detect the zero crossing produced by the noise. Fig. 1, shows the output of zero crossing

detection if the input contains noise.

This can be avoided by using a Schmitt trigger, circuit which is basically a comparator with positive feedback. Fig. 2, shows an

inverting Schmitt trigger circuit using OPAMP.

Because of the voltage divider circuit, there is a positive feedback voltage. When OPAMP is positively saturated, a positive

voltage is feedback to the non-inverting input, this positive voltage holds the output in high stage. (vin< vf). When the output

voltage is negatively saturated, a negative voltage feedback to the inverting input, holding the output in low state.

When input vin exceeds V ref = +V sat the output switches from +V sat to –V sat . Then the reference voltage is given by

Fig. 3 Fig. 4

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Lecture 18

If vin < V ref i.e. vin becomes more negative than –V sat then again output switches to +V sat and so on. The transfer characteristic

of Schmitt trigger circuit is shown in fig. 3. The output is also shown in fig. 4 for a sinusoidal wave. If the input is different than

sine even then the output will be determined in a same way.

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Lecture 18

Positive feedback has an unusual effect on the circuit. It forces the reference voltage to have the same polarity as the output

voltage, The reference. voltage is positive when the output voltage is high (+v sat ) and negative when the output is low (–vsat ).

In a Schmitt trigger, the voltages at which the output switches from +v sat to –vsat or vice versa are called upper trigger point

(UTP) and lower trigger point (LTP). the difference between the two trip points is called hysteresis.

Fig. 5

The hysteresis loop can be shifted to either side of zero point by connecting a voltage source as shown in fig. 5.

If V R is positive the loop is shifted to right side; if V R is negative, the loop is shifted to left side. The hysteresis voltage V hys

remains the same.

In this case, again the feedback is given at non-inverting terminal. The inverting terminal is grounded and the input voltage is

connected to non-inverting input. Fig. 6, shows an non-inverting schmitt trigger circuit.

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Lecture 18

Fig. 6

To analyze the circuit behaviour, let us assume the output is negatively saturated. Then the feedback voltage is also negative (-

V sat ). Then the feedback voltage is also negative. This feedback voltage will hold the output in negative saturation until the input

voltage becomes positive enough to make voltage positive.

When vin becomes positive and its magnitude is greater than (R2 / R1 ) V sat , then the output switches to +V sat . Therefore, the

UTP at which the output switches to +V sat , is given by

Simillarly, when the output is in positive saturation, feedback voltage is positive. To switch output states, the input voltage has to

become negative enough to make. When it happens, the output changes to the negative state from positive saturation to negative

saturation voltage negative.

When vin becomes negative and its magnitude is greater than R2 / R1 vsat , then the output switches to -vsat . Therefore,

The difference of UTP and LTP gives the hysteresis of the Schmitt trigger.

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Lecture 18

Example - 1

Design a voltage level detector with noise immunity that indicates when an input signal crosses the nominal threshold of – 2.5 V.

The output is to switch from high to low when the signal crosses the threshold in the positive direction, and vice versa. Noise level

expected is 0.2 V PP , maximum. Assume the output levels are V H = 10 V and V L = 0V.

Solution:

For the triggering action required an inverting configuration is required. Let the hysteresis voltage be 20% larger that the

maximum pp noise voltage, that is, V hys = 0.24V.

Thus, the upper and lower trigger level voltages are -2.5 ± 0.12, or

Since the output levels are V H and V L instead of +V sat and –V sat , therefore, hysteresis voltage is given by

or

and

We can select any values for R2 and R1 that satisfy the ratio of 40.7. It is a good practice to have more than 100 kΩ for the sum

of R1 and R2 and 1 kΩ to 3kΩ for the pull up resistor on the output. The circuit shown in fig. 7 shows a possible final design. The

potentiometer serves as a fine adjustment for V R , while the voltage follower makes V R to appear as an almost ideal voltage

source.

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Lecture 18

Fig. 7

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Lecture 19

Example - 1

The Schmitt trigger circuit of fig. 1 uses 6V zener diodes with V D = 0.7 V. if the threshold voltage V 1 is zero and the hysteresis is

V H = 0.2V. Calculate R1 / R2 and V R .

Fig. 1

Solution:

Where, V O = V Z + V D

= 6.7 V

Let the output voltage be +V O. The voltage V 1 can be obtained from the voltage divider circuit consisting of R1 and R2 .

Therefore, upper trigger point voltage will be given by,

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Lecture 19

Therefore,

Relaxation Oscillator:

With positive feedback it is also possible to build relaxation oscillator which produces rectangular wave. The circuit is shown in

fig. 2.

Fig. 2

In this circuit a fraction R2 / (R1 +R2 ) = b of the output is feedback to the non-inverting input terminal. The operation of the circuit

can be explained as follows:

Assume that the output voltage is +V sat . The capacitor will charge exponentially toward +V sat . The feedback voltage is +bV sat .

When capacitor voltage exceeds +bV sat the output switches from +V sat to -V sat . The feedback voltage becomes -V sat and the

output will remain –Vsat . Now the capacitor charges in the reverse direction. When capacitor voltage decreases below –bV sat

(more negative than –bV sat ) the output again switches to +V sat .This process continues and it produces a square wave. Under

steady state conditions, the output voltage and capacitor voltage are shown in fig. 2. The frequency of the output can be obtained

as follows:

The capacitor charges from -β V sat to +β V sat during time period T/2. The capacitor charging voltage expression is given by

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Lecture 19

This square wave generator is useful in the frequency range of 10Hz to 10KHz. At higher frequencies, the slew rate of the

OPAMP limits the slope of the output square wave.

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Lecture 19

The duty cycle of the output wave can be changed replacing the resistance R by another circuit consisting of variable resistance

and two diodes D1 and D2 as shown in fig. 3.

Fig. 3 Fig. 4

When the output is positive then D2 conducts and D1 is OFF. The total feedback resistance becomes Rb +R and charging voltage

is reduced by V D . During the interval when the output is negative then D1 conducts and D2 is OFF. The charging resistance

becomes R+R a . The total charging and reverse charging period is decided by total resistance (2 R + Ra + Rb ) = constant.

Therefore frequency will remain constant but duty cycle changes. The capacitor voltage and output voltage of the oscillator are

shown in fig. 4.

By varying Ra and Rb the duty cycle can be charged keeping frequency constant.

Example - 2

Characterize the astable mulitvibrator shown in fig. 5. Establish the frequency range.

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Lecture 19

Fig. 5

Solution:

By observing the way the output section is connected, we conclude that the output voltage oscillates between V L = - 5V and V H

= + 5V.

To calculate the oscillation frequency range, two extreme values for R1 and R2 are used. Thus, when the wiper of the

potentiometer is at its leftmost position, R1 = 120 kΩ and R2 = 10 kΩ. At the other extreme, R1 = 20 kΩ and R2 =110 kΩ.

Substituting the values of R1 and R2 in the expression of T, we obtain the two extreme values of T, i.e., T min and T max

Therefore,

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Lecture 20

In the relaxation oscillator discussed in the previous lecture, capacitor voltage V C has a near triangular wave shape but the sides

of the triangles are exponentials rather than straight line. To linear size the triangles, it is required that C be charged with a

constant current rather that the exponential current through R. The improved circuit is shown in fig. 1.

Figure 21.1

In this circuit an OPAMP integrator is used to supply a constant current to C so that the output is linear. Because of inversion

through the integrator, this voltage is fedback to the non-inverting terminal of the comparator rather than to the inverting terminal.

The inverter behaves as a non-inverting schmitt trigger. The voltage vR is used to shift the dc level of the triangular wave and

voltage vs is used to change the slopes of the triangular wave form is shown in fig. 2.

Fig. 2

To find the maximum value of the triangular waveform assume that the square wave voltage vOis at its negative value = -V sat .

With a negative input, the output v (t) of the integrator is an increasing ramp. The voltage at the non-inverting comparator input v1

is given by

When v1 rises to V R , the comparator changes state from - V sat to +V sat and v(t) starts decreasing linearly similarly, when v1 falls

below vR the comparator output changes from +v sat to -vsat . Hence the minimum value of triangular vmin occurs for v1 = vR .

Hence the peak value V max of the triangular waveform occurs for v1 = V R .

Therefore,

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Lecture 20

If V R = 0, the waveform extends between -V sat (R2 / R1 ) and +V sat (R2 /R1 ).

The sweep times T 1 and T 2 for V s = 0 can be calculated as follows:

The capacitor charging current is given by

When the output voltage of first OPAMP is +V sat , then, the voltage v1 is given by

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Lecture 20

As triangular voltage increases the voltage v1 also increases. At t = T 1 , when the voltage vout becomes V max, the voltage v1

becomes equal to V R and switching takes place. Therefore,

As triangular voltage decreases the voltage v1 also decreases. At t = T 2 , when the voltage vout becomes V min , the voltage v1

becomes equal to V R and switching takes place. Therefore,

Therefore,

The frequency f is independent of V O, maximum frequency is limited either by slew rate or its maximum output current which

determines the charging rate of C. Slowest speed is limited by the bias current of OPAMP.

If unequal sweep intervals T 1 ≠ T 2 are desired, then V S can be changed. The positive sweep speed is given by (Vsat + V S) / RC

and the negative sweep speed is given by (Vsat -V S)/ RC. The peak-to-peak triangular amplitude is unaffected by the voltage V S.

Therefore,

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Lecture 20

Therfore,

Therefore,

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Lecture 20

Example-1:

1. Consider the pulse generator shown in fig. 3. In the quiescent state (before a trigger pulse is applied), find V 2 , V O and V 1 .

2. At t = 0, a narrow, positive triggering pulse v whose magnitude exceeds V R is applied. At t = 0+, find V O and V 1 .

3. Verify that the pulse width T = RC ln (2 V O) / V R .

Fig. 3

Solution:

(a). Before a trigger pulse is applied, the circuit is in stable stage with the output at vO = +V O ( ≈ V Z + 0.7). The capacitor C is

charged with the polarity shown in fig. 3.

Thus, v1 ≈ 0.7V

and v2 = -V R

(b). At t = 0, a narrow positive triggering pulse of higher magnitude is applied. The capacitor C voltage can not charge

instantaneously. Therefore, v2 becomes positive and greater than v1 (≈ 0.7 V). The comparator output changes.

v1 = 2 V O

(c). The input trigger pulse is of very short duration therefore, after the short duration pulse the voltage v2 returns to (-V R ). But the

output remains –VO because v1 is at – 2VO.

The capacitor now starts charging exponentially with a time constant t = RC through R towards –V O, because diode is reverse

biased.

V C = (-V O – V O) ( 1 – e-t / RC ) - V O

V 1 = - V O – vc

= - V O + 2 V O (1 – e-t / RC ) - V O

= - 2 V O e-t / RC – t / RC

When v1 voltage becomes more than V R , the comparator output switches back to +V O. Let at t = T, the voltage v1 becomes –

VR

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Lecture 20

The capacitor now starts charging towards +V O through R until vc reaches +V O and v1 becomes 0.7 V. The waveforms at

different points are shown in fig. 4.

Fig. 4

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