A Grid Synchronization Method for Droop
Controlled Distributed Energy Resources Converters
Chia-Tse Lee, IEEE Student Member, Rui-Pei Jiang, and Po-Tai Cheng, IEEE Senior Member
Abstract—The microgrid is a very effective way of inte-
grating various distributed generation resources into the AC
power system. To provide electric power of high reliability, the
converters in the microgrid often rely on autonomous droop
control methods to reduce their dependency on communication,
and need to operate in both the islanded mode or the grid-
connected mode. In this paper, a grid synchronization method for
a multi-converter distributed generation system is proposed. The
proposed grid synchronization method allows multiple droop-
controlled converters to adjust the frequency, phase, and am-
plitude of their output voltages to prepare for grid connection.
The entire synchronization process can be executed with very
limited communication requirement. This paper provides detailed
explanation on the proposed grid synchronization method. Ex-
perimental test results are presented to validate the effectiveness
of the proposed method.
Index Terms—Distributed generation systems, droop control,
grid synchronization, Microgrid.
I. I NTRODUCTION
In the pursuit of low carbon emissions, renewable en-
ergy resources, such as solar power, and wind power, have
been widely adopted in recent years. Other alternative en-
ergy resources have also become significant research topics.
Considering their generation scale and characteristics, the
most effective way to utilize these alternative resources is to
integrate them into a distributed generation system (DGS). The
microgrid, for example, has demonstrated this concept very
successfully [1], [2], [3].
The control of distributed energy resources converters
(DERCs) in DGS have been explored over the years. The
main approaches include the master-slave control [4], [5] and
autonomous droop control [6], [7], [8], [9], [10]. In the master-
slave framework, one converter in the DGS is assigned to be
the master, and it operates as a voltage stiff while the other
converters in this system are controlled as current sources.
This master converter acts as a virtual inertia [2], and will
pick up most dynamic power flows within the DGS. Therefore,
this master converter must be sufficiently large in its power
capacity and sufficiently fast in its control bandwidth in order
to absorb all the transients in this system. A sophisticated
communication network is also required to coordinate the
operations of all converters. On the other hand, the droop
control method allows multiple DERCs to proportionally share
C. -T Lee and P. -T. Cheng are with the Center for Adavanced
Power Technologies, Department of Electrical Engineering, National Ts-
ing Hua University, Hsinchu, 30013, TAIWAN (email: atonis5@gmail.com;
ptcheng@ieee.org). R. -P. Jiang is with the Taiwan Army (email:
g9761586@oz.nthu.edu.tw).
the transient and steady state power flow without any commu-
nication. This is a significant advantage in terms of system
reliability.
Traditionally, the real power-frequency droop (P −ω droop)
control and the reactive power-voltage droop (Q − V droop)
are generally adopted in the droop controlled DGS [6], [7],
[8]. The P − ω droop control can achieve accurate real power
sharing results. However, the Q − V droop control is highly
dependent on the line impedances seen from the converters
[9], [10]. Therefore, the Q − V̇ droop control method has
been proposed to overcome the impedance mismatch among
converters and achieve better proportional sharing of reactive
power [11].
To ensure the uninterrupted operation of its critical loads,
the microgrid must be capable of operating in both the grid-
connected mode and the islanded mode, and offer a smooth
transition between these two modes. Thus the grid synchro-
nization, which prepares islanded microgrid for grid connec-
tion, is a critical procedure of the entire operation. The grid
synchronization method has been elaborately discussed for
single grid-connected converter [5], [12], [13], [14]. However,
it is not often explored for multi-converter oriented systems or
droop controlled DGS. Droop controllers are adopted in [15],
[16] during their islanded operation. However, during the grid
synchronization, the droop controllers are restrained and the
power flow of converters are altered from their droop control
operating point in order to accommodate their synchronization
design.
This paper proposes a grid synchronization method based on
the frequency restoration and voltage restoration mechanism
of the P − ω and Q − V̇ droop controls [11]. The frequency,
the phase angle, and the magnitude of DERCs’ output voltages
are smoothly adjusted so that the proportional sharing of active
power and reactive power among DERCs, an important feature
of the droop controls, are not disturbed. To maintain the
autonomous nature of the droop controls, a low bandwidth
communication is required only during the synchronization
process. A similar synchronization design had been presented
in [17] for a P − ω, Q − V droop controlled microgrid. A
center-controlled frequency and voltage restoration mechanism
is required for its grid synchronization and for its islanded
mode operation, thus its dependency on the communication
increases. Test results are provided to illustrate the operation
of the proposed grid synchronization method under low band-
width communication.
 Distributed Generation System
PWM
gate V1 θ1
Autonomous signal
controller 1 Lf1
Cf1
i1,abc
v1,abc
DERC1
PWM
gate V2 θ2
Autonomous signal
controller 2 Lf2
Cf2
i2,abc
v2,abc
DERC2
Fig. 1. Distributed generation system structure.
II. C ONTROLS OF DERC S
DERCs are installed in the DGS as illustrated in Fig. 1.
R1 + jX1 , R2 + jX2 , and etc. represents the line impedances,
which may vary from one to the other due to the physical
distances. The bypass switch between the DGS and the utility
grid may close or open depending on whether the DGS
operates in the grid-connected mode or the islanded mode.
The main controller detects the point-of-common-coupling
(PCC) voltage of the DGS and the grid voltage and pass the
information to the central console. The central console collects
information from the main controller and other sources, and
determines whether the DGS should operate in the grid-
connected mode or in the islanded mode. Assuming the DGS
is in the islanded mode, and central console decides that the
system should move towards the grid-connected mode, then
the central console will broadcast required information via a
low bandwidth communication interface to all the autonomous
controllers embedded in DERCs and commence the grid
synchronization process. Details of the autonomous controller,
the main controller, the center console, and their interactions
are explained as follows.
A. Main controller
Fig. 2 shows the detailed control block diagram of the main
controller. The main controller senses the utility grid voltages
vG,abc and the DGS PCC voltages vP CC,abc , and then calculate
the utility grid frequency ω G , the phase angle difference θ dif f ,
and the voltage magnitude difference (V dif f ) between vG,abc
and vP CC,abc .
A conventional phase-locked loop (PLL) design [18] is
applied to track the frequency ω G , and the phase angle θ G
of the utility grid voltage v G,abc , and ωP CC and θP CC of the
DGS PCC voltage vP CC,abc respectively. Since the PLL uses
synchronous reference frame (SRF) transformation as part of
its computation, the SRF component v G,qd and vP CC,qd are
readily available. Therefore θ dif f and Vdif f can be calculated
Bypass Switch Utility Grid
R1+jX1
Sensor feedback
Load Communication signal
R2+jX2 vPCC,abc vG,abc Switch CLOSE/OPEN signal
Main controller
operation
mode control
ωG,θdiff,Vdiff
Central console
as follows:
θdif f = θG − θP CC
 
Vdif f = vGq2 + v2 − vP2 CCq + vP2 CCd
Gd
The information of phase angle difference (θ dif f ) can be
detected by subtracting the phase angle θ P CC from the phase
angle θG .
The synchronous reference frame PLL (SRF-PLL) is a very
conventional PLL structure [18], [19], [20], and its operation
under grid voltage harmonics and unbalance has been dis-
cussed in [19]. Therefore, in the proposed grid synchronization
application, this PLL is adequate to deal with the steady-state
grid disturbances. If severe disturbances, such as ground faults
and phase jumps, occur in the utility grid or in the microgrid,
then such situation may not be suitable for our microgrid to
re-connect with the utility. The resulting distorted output of the
PLL can be used as an alarm of such severe event to override
the grid synchronization process.
B. Autonomous controller
The detailed control block diagram of DERC’s autonomous
controller is given in Fig. 3. The autonomous controller
consists of the voltage and current controller, the droop con-
troller, and the grid synchronization controller. The voltage and
current controller can track the voltage references produced by
the droop controller, and it contains the outer-loop voltage PI
controller and the inner-loop predictive current controller [21].
The droop controller is composed of P − ω droop control and
Q − V̇ droop control [11]. The P − ω droop is expressed as
ωx = ω0x − mx · (P0x − Px ) (1)
where mx is the P − ω droop coefficients, ω 0x is the nominal
frequency and P 0x is the real power set-point. ω x and Px
are the actual operating frequency and output real power of
DERCx. To achieve the proportional real power sharing, the
P − ω droop coefficients in DERCs are set as
m1 · PR1 = m2 · PR2 = · · · = mx · PRx
 Operation
Grid vGq
2 2 VG mode
vGa vGd vGq +vGd control
vG,abc abc vGq
vGb ωG 1 vPCCq Vdiff
to vGd PLL
Switch vGc qd+ s θG vPCCd vPCCq2+vPCCd2 ωG
CLOSE/OPEN
VPCC
Bypass signal θdiff
Switch Voltage magnitude difference calculation θdiff
vPCCa
abc vPCCq
vPCCb ωPCC 1 Bypass switch
to vPCCd PLL control Gate Vdiff
vPCC,abc vPCCc qd+ s θPCC
signal
gate signal
signal
generator

DGS
Frequency and phase angle difference detection Control signals of bypass switch

Main controller

Fig. 2. Control block diagram of main controller.

where PRx is the rated real power capacity. Islanded mode

The Q − V̇ droop is expressed as
V̇x = V̇0x − nx · (Q0x − Qx )
 time
(2)
Vx = V0x + V̇x dt
where nx is the Q − V̇ droop coefficients, V̇0x and V0x
are nominal V̇ and nominal voltage magnitude, Q 0x is the
reactive power set-point. V̇x , Vx , and Qx are the actual
voltage magnitude derivatives, actual voltage magnitude, and
reactive power output respectively of DERCx. To accomplish
the proportional reactive power sharing, the Q − V̇ droop
coefficients in DERCs are set as
n1 · QR1 = n2 · QR2 = · · · = nx · QRx
where QRx is the rated reactive power capacity.
This paper is to address the grid synchronization issue for
this multi-converter oriented and P −ω, Q− V̇ droop controlled
DGS, thus the grid synchronization control is implemented in
the autonomous controller. The proposed grid synchronization
method regulates P 0x and Q0x of P − ω and Q − V̇ droop
controller to achieve the operation of grid synchronization. The
details about grid synchronization operation will be explained
in the following section.
C. Central console
To minimize the transients at the instant of grid connection,
the frequencies, the phase angles, and the magnitudes of v P CC
and vG are closely matched by the proposed grid synchroniza-
tion method. The central console first commences the grid
synchronization process through the operation mode control.
Once the synchronization is confirmed by all autonomous
controllers and the main controller, the central console can
decide to go for grid connection by commanding the main
controller to close the bypass switch. Fig. 4 shows the flow of
operation mode control signals and the sequence of the grid
synchronization process.
III. G RID S YNCHRONIZATION M ETHOD
This paper proposes a grid synchronization method based on
the existing P − ω and Q − V̇ droop controls and their restora-
tion controls for all DERCs in the DGS. The proposed grid
Grid-connected
P ω Frequency
Voltage
Phase angle mode
magnitude
Q V restoration synchronization
equalization
FR=1 VS=1 PS=1
Grid synchronization starts Bypass switch closes
Fig. 4. Relationships between control signals and the operation modes during
grid synchronization process.
synchronization method adjusts DERCs’ operation frequencies
and phase angles through the frequency restoration of the
P − ω droop control, and DERCs’ output voltage magnitudes
through the V̇ restoration of Q − V̇ droop control. As a result,
the grid synchronization is accomplished in an autonomous
manner, and the proportional sharing of real power and the
reactive power accomplished by the droop controls can be
maintained with negligible transients in the process.
A. Frequency and phase synchronization based on P − ω
droop controller
Fig. 5 shows the block diagram of frequency restoration
mechanism of the P − ω droop control, and how it can be
utilized for the frequency and phase synchronization. While
in the islanded mode, the nominal frequency (ω 0x ) and the
real power set-point (P 0x ) are set at 2π · 60 rad/sec and the
rated real power capacity (P Rx ) respectively as illustrated
by the droop line of islanded mode in Fig. 6. The loading
within the DGS forces the P − ω droop control to move its
operating frequency ω x until DERCx handles its proportional
share of real power output P x . As the frequency restoration
is commanded by the central console, ie. F R = 1, the P − ω
droop control is re-defined as
ωx = ωG − mx (Px,F R=1 + ΔP0x − Px ) (3)
where Px,F R=1 represents the real power output at the moment
when frequency restoration is initiated, and ΔP 0x comes
from the phase angle synchronization control block. As in
Fig. 6, this new droop line immediately restores the operating
frequency ω x to the grid frequency ω G while the DERCx
produces the same real power P x = Px,F R=1 .
 ωG ωG Frequency restoration and
Vdiff θdiff Phase angle synchronization
θdiff V restoration and
Vdiff Voltage magnitude equalization
Operation mode Operation mode
Grid synchronization control
control control
Px Vx Q0x P0x

ix,abc abc ix,αβ αβ ix,qd ωf Px P-ω ωx

to to vxqixq+vxdixd
αβ qd+ s+ωf droop
Power calculation
Lfx vx,abc abc vx,αβ αβ vx,qd ωf Qx Q-V Vx
Cfx
to to vxqixd -vxdixq
αβ qd+ s+ωf droop
Droop-based power sharing controller
vx,αβ ix,αβ vx,qd
PWM *
Vx
vabc αβ vαβ* Lfx iref,αβ qd+ iref,qd vref,qd Reference
gate PWM to to PI generator
abc T αβ
signal ωx
Current controller Voltage controller

Autonomous controller x
Fig. 3. Control block diagram of autonomous controller.

For the phase angle synchronization, the phase angle dif-

ference (θdif f ) is processed by a proportional-integral (PI)
regulator, and the output ΔP 0x shifts the P − ω droop line ωG FR=1

2π·60 ω0x
horizontally in a dynamic sense. As the loading within the Operation FR=1
FR=0

DGS remains unchanged, this adjustment leads to the change mode control Px,FR=1
Px S/H FR=1
P0x
of operating frequency ω x and the phase angle of DERCx’s PRx FR=0
output voltage. Eventually this PI regulator settles into the Frequency restoration
steady state when θdif f become zero, which means v P CC ΔP0x
and vG are synchronized in both their frequencies and phase θdiff PS=1
PRx kp,Psyn
angles, and DERCx operates based on Equation (3) with 0 PS=0

ΔPx = 0. ki,Psyn 1
s
In the proposed phase angle synchronization control, θ dif f Phase angle synchronization
is first multiplied by PRx before being fed into the PI regulator
for the reason that the adjustment of the real power set- Fig. 5. Frequency restoration and phase angle synchronization controller.
points should be in proportion to their converter’s real power
capacities. This ensures that the same frequency change is
introduced for all the DERCx while their individual droop
lines are shifted. Therefore the relative phase angle differences
among all the DERCs are kept unchanged, and the proportional ω Droop line of islanded mode
After frequency restoration
real power sharing in the islanded mode can also be maintained During phase angle synchronization

during the frequency and phase synchronization operations. ΔP0x

Please note that all DERCs must use the same kp,P syn and ωx
ki,P syn gains in their phase synchronization PI regulator in ωG
order to uphold the proportional real power sharing during the ω0x=2π·60
process.
Px=Px,FR=1 P0x=PRx P
B. Voltage equalization based on the Q − V̇ droop controller
Fig. 6. Illustration of the frequency restoration and phase angle synchro-
Fig. 7 shows the V̇ restoration and the voltage magnitude nization operations.
equalization control. The V̇ restoration is an inalienable part
of Q − V̇ droop control to maintain the voltage magnitude
 1 The capacity of DERC2 is two times of DERC1. The key
Vx s QRx kp,Qres
0 waveforms in the main controller are shown in Fig. 9(a), and
V restoration
Operation
mode control
Vdiff VS=1
QRx kp,Qsyn
0 VS=0
ki,Qsyn
Voltage magnitude equalization
Fig. 7. V̇ restoration and voltage magnitude equalization controller.
V Droop line of islanded mode
After V restoration
During voltage magnitude equalization
ΔQ0x
Vx
V0x=0
Qx Q0x=QRx
Fig. 8. Illustration of the V̇ restoration and voltage magnitude equalization
operations.
while accomplishing the proportional reactive power sharing
in the islanded operation. The V̇ restoration controller adjusts
the reactive power set-point (Q 0x ) by integrating − V̇x , so the
Q− V̇ droop control reaches its steady state at V̇ = 0 to main-
tain a constant output voltage magnitude after V̇ restoration
as illustrated in Fig. 8. The voltage magnitude equalization
is constructed on the top of this restoration mechanism. The
voltage magnitude difference V dif f is processed by an PI
regulator, the resulting ΔQ 0x then shifts the reactive power
droop line in a dynamic sense. As the reactive power con-
sumption within the DGS remains unchanged, this shift leads
to certain nonzero V̇x and drives the DERCx output voltage
magnitude towards the magnitude equalization of V dif f = 0,
which means vP CC and vG are synchronized in their voltage
magnitudes.
QRx is also added before the PI regulator to ensure the same
V̇ change is introduced for all the DERCx while their indi-
vidual droop lines are shifted. The relative voltage magnitude
differences among all the DERCs are thus kept unchanged, and
the proportional reactive power sharing in the islanded mode
can be maintained during the voltage magnitude equalization
operation. Please note that all DERCs use the same k p,Qres ,
kp,Qsyn and ki,Qsyn in their controller in order to uphold the
proportional reactive power sharing during the process.
IV. S IMULATION R ESULTS
The aforementioned grid synchronization method is tested
with computer simulation. A DGS composed of two DERCs
as shown in Fig. 1 is investigated, and their line impedances
are set as the same, R1 + jX1 = R2 + jX2 = 1 + j0.754 Ω.
The parameters used in the simulation are listed in TABLE I.
Fig. 9 shows the simulation results of the proposed grid
synchronization with DERCs of different power capacities.
Q0x
ΔQ0x waveforms in the autonomous controller are shown in Fig. 9(b)
and Fig. 9(c).
Before t = t1 = 30 sec, the DERCs are operated in
1 islanded mode. A step load change from 345 W + j200 VAR
s to 1000 W + j200 VAR is presented at t = 15 sec. As shown
in Fig. 9(b) and Fig. 9(c), the power sharing P 1 = 359 W,
P2 = 719 W, Q1 = 88 VAR, Q2 = 107 VAR is achieved by
P − ω and Q − V̇ droop control. Because of the operation of
the droop controls, the operating frequencies ω 1 and ω2 and
the operating voltage magnitudes V 1 and V2 are deviated from
the nominal frequency and voltage magnitude. This results in
the variation of θ dif f and Vdif f shown as in Fig. 9(a) when
the load is changed.
This frequency difference due to the operation of droop
controls can be solved with the engagement of frequency
Q
restoration at t = t1 = 30 sec, which is activated by
issuing F R = 1 from the central console. As the frequency
restoration is accomplished, ω P CC is restored to be the same
as ωG , and θdif f in Fig. 9(a) no longer varies, and the
power sharing is maintained at P 1 = 361 W, P2 = 718 W,
Q1 = 88 VAR, Q2 = 107 VAR. The voltage magnitude
equalization is initialled by the command (V S = 1) issued
from central console at t = t 2 = 40 sec. The DERCs start to
raise their reactive power set-points Q 01 and Q02 to derive
the positive V̇1 and V̇2 as shown in Fig. 9(c). Thus the
PCC voltage magnitude increases to equalize the grid voltage
magnitude, and then V dif f in Fig. 9(a) is reduced to zero.
The output power of DERCs P 1 = 382 W, P2 = 759 W,
Q1 = 94 VAR, Q2 = 114 VAR are increased because of
the voltage magnitude equalization. At t = t 3 = 50 sec,
the central console begins the phase angle synchronization
(P S = 1). The negative real power set-points P 01 and P02
are generated by the negative θ dif f at this moment, and then
the operating frequencies ω 1 and ω2 are slowed down to match
the PCC voltage phase angle with the grid voltage phase angle.
As the phase angle synchronization is completed, the power
sharing is still maintained at the same level as in the islanded
operation, where P 1 = 382 W, P2 = 759 W, Q1 = 92 VAR,
Q2 = 116 VAR. At t = t4 = 70 sec, the DERCs goes into
the grid-connected mode with some transients power flows.
After the DERCs operate in the grid-connected mode for 20
seconds, the central console commands the DERCs to go back
to the islanded mode operation again. The grid synchronization
process shown in Fig. 9 verify that the operation of P − ω,
Q − V̇ droop controlled DGS can be transferred from islanded
mode to grid-connected mode without affecting the original
power sharing results by the proposed grid synchronization
method.
The power sharing during t 1 and t4 are not affected be-
cause the proposed grid synchronization method takes all the
DERCs’ power capacities into account. Thus the regulation of
P01 , P02 , Q01 , and Q02 shown in Fig. 9(b) and Fig. 9(c) are in
proportion to their DERC’s power capacities, and then ω 1 , ω2 ,
V̇1 , and V̇2 are shifted with the same variation. As a result, the
relative phase angle difference θ 1 − θ2 and the relative voltage
magnitude difference V 1 − V2 between DERC1 and DERC2
are maintained, thus the original proportional power sharing FR = 1 PS = 1 Islanded operation
Step load changes V S = 1 Bypass switch closes
accomplished by the droop controls are not affected. 377.2
t1 t2 t3 t4 t5
ωG

[rad/sec]
377.1
377
376.9
V. E XPERIMENTAL T EST R ESULTS 376.8
0 10 20 30 40 50 60 70 80 90 100
The DGS test bench shown in Fig. 10 is constructed to 377.2 ωP CC

[rad/sec]
377.1
validate the effectiveness of the proposed grid synchronization 377
control method. Two DERCs are installed in the testbench in 376.9
376.8
the same configuration as in Fig. 1. The detailed descriptions 0 10 20 30 40 50 60 70 80 90 100

of this DGS are stated as follows. 0.4

θdif f

[rad]
0.2
• The system voltage is V L−L = 220 Vrms, and the 0
frequency is 60 Hz. The power line impedances are R 1 + −0.2
0 10 20 30 40 50 60 70 80 90 100
jX1 = 1+j0.754 Ω and R2 +jX2 = 1+j0.754 Ω. A total 15 Vdif f
of 1000 W and 200 VAR are made up by resistor loads 10

[V]
5
and an unloaded induction machine. The bypass switch 0
−5
is implemented by anti-parallel connected thyristors. 0 10 20 30 40 50 60 70 80 90 100
Time[sec]
• The DERCs are three-phase, hard-switched PWM con-
verters switching at f switch = 10 kHz. The output filter (a)
inductor is Lf = 2 mH, and the output filter capacitor is FR = 1 PS = 1 Islanded operation
Step load changes V S = 1 Bypass switch closes
Cf = 10 μF. The 400Vdc bus of the DERC is supported t1 t2 t3 t4 t5
1000
by a DC power supply. 750

[W]
500
• The main controller and the autonomous controllers 250
0 P1 P2
are implemented with the digital signal processor 0 10 20 30 40 50 60 70 80 90 100
TMS320F28335 individually, and the sampling frequency 377.2 ω1 ,ω2
[rad/sec]

is programmed at f sample = 20 kHz. The coefficients of 377.1

377
main controller and autonomous controllers are given in 376.9
376.8
TABLE I. 0 10 20 30 40 50 60 70 80 90 100

• The communication interfaces are implemented with RS- 6000

P02
3000
232 to transmit and receive data among the central
[W]

0
−3000
P01
console, main controller, and autonomous controllers. −6000
−9000
0 10 20 30 40 50 60 70 80 90 100
The bandwidth of these communication units are set at x 10
−3
5
approximately 152 Hz. θ1 − θ2
[rad]

0
Fig. 11 shows the experimental test results of the proposed −5

grid synchronization method with two DERCs of the same −10

0 10 20 30 40 50 60 70 80 90 100
Time[sec]
power capacity. Waveforms of key variables of the main
controller are shown in Fig. 11(a), and those of DERC1 and (b)
DERC2 are shown in Fig. 11(b) respectively. Before t = t 0 , FR = 1 PS = 1 Islanded operation
Step load changes V S = 1 Bypass switch closes
DERC1 supports all the load in the DGS while DERC2 is t1 t2 t3 t4 t5
150
starting up. At t = t0 , DERC2 engages its droop control and
[VAR]

100
operate in parallel with DERC1 in the islanded mode opera- 50
Q1 Q2
tion. Load changes are introduced by line-starting an induction 0
0 10 20 30 40 50 60 70 80 90 100
motor and connecting a resistor load bank. P 1 = 472 W, 50
40
[V/sec]

P2 = 560 W, Q1 = 107 VAR, and Q2 = 90 VAR shown in 30 V̇1 ,V̇2

20
Fig. 11(b) indicates that both DERCs share the loading evenly. 10
0
Their P − ω and Q − V̇ droop controls respond to these load −10
0 10 20 30 40 50 60 70 80 90 100

changes by adjusting their operating frequencies and output 12000

Q01 Q02
[VAR]

8000
voltage magnitudes, thus V dif f and θdif f in Fig. 11(a) exhibit 4000
certain variations when the inductive load and the resistive 0
−4000
0 10 20 30 40 50 60 70 80 90 100
load are added.
184
At t = t1 , the central console issues the command of
181
[V]

frequency restoration (F R = 1). The operating frequencies 178

V1 V2
of DERC1 and DERC2 are immediately set to the grid 175
0 10 20 30 40 50 60 70 80 90 100
frequency ω G , Now vP CC and vG have the same frequency, Time[sec]
thus θdif f no longer varies. At the instance of the starting
(c)
of frequency restoration, the power sharing is affected by the
sudden change of P 01 and P02 . However, the power sharing is
Fig. 9. The responses of main controller and DERCs during grid synchro-
still maintained at P1 = 422 W, P2 = 600 W, Q1 = 116 VAR, nization process with the DERCs of different power capacities.
and Q2 = 78 VAR.
 TABLE I
R ELATED PARAMETERS OF MAIN CONTROLLER AND AUTONOMOUS CONTROLLERS IN THE SIMULATION AND THE EXPERIMENTAL TEST

Main controller
PLL kpllp = 0.025 rad/Vsec, kplli = 0.75 rad/Vsecsec

P − ω droop control
Rated real power capacity
Q − V̇ droop control
Rated reactive power capacity
V̇ restoration
Phase angle synchronization
Voltage magnitude equalization
Synchronous voltage PI controller
Predictive current controller
Autonomous controllers
Section IV Section V
m1 = 2 · m2 = −18.85 × 10−6 rad/Wsec m1 = m2 = −18.85 × 10−6 rad/Wsec
2 · PR1 = PR2 = 2.0 kW PR1 = PR2 = 1.0 kW
n1 = 2 · n2 = −8.0 × 10−3 V/VARsec n1 = n2 = −2.0 × 10−3 V/VARsec
2 · QR1 = QR2 = 2.0 kVAR QR1 = QR2 = 1.0 kVAR
kp,Qres = 0.025 V−1
kp,P syn = 20.0 rad−1 , ki,P syn = 15.0 rad−1 sec−1
kp,Qsyn = 1.0 sec/V, ki,Qsyn = 1.0 V−1
kV p = 0.04 A/V, kV i = 6.0 A/Vsec
kC = 30.0 V/A

DERC1
DERC2
Thyristor-based
bypass switch
DC
sources
Line
impedances
Fig. 10. The constructed DGS in the laboratory.
At t = t2 , the central console initiates the voltage equal-
ization (V S = 1). The positive V dif f in Fig. 11(a) raises the
reactive power set-points Q 01 and Q02 in DERC1 and DERC2
respectively. This leads to positive V˙1 and V˙2 in their Q − V̇
droop controls so their output voltage magnitude increases,
and then the PCC voltage magnitude rises to match the
grid voltage magnitude and complete the voltage magnitude
equalization. In the meantime, the output power of DERCs are
increased as P1 = 452 W, P2 = 640 W, Q1 = 123 VAR, and
Q2 = 100 VAR as a result of the raised voltage magnitude.
At t = t3 , the central console starts the phase angle
synchronization (P S = 1). The real power set-points P 01 and
P02 of DERC1 and DERC2 increases as a result of the positive
θdif f at this moment. The operating frequencies of DERCs go
up because of their P − ω droop controls, and the phase angle
of vP CC gradually catches up with the phase angle of v G and
reduce θdif f to zero. As the grid synchronization completes,
the power sharing of DERCs is maintained at P 1 = 496 W,
P2 = 610 W, Q1 = 121 VAR, and Q2 = 95 VAR.
At t = t4 , the central console confirms that the grid
synchronization is accomplished, v P CC and vG are matched
in their frequencies, phase angles, and magnitude. So the
command of grid-connection is issued to the main controller.
The bypass switch is closed and the DGS enters the grid
Autonomous
controller 1 connection mode smoothly with little transients. The system
operates in the grid connection mode for nearly one minute.
Autonomous
At t = t5 , the central console commands the DGS to go back
controller 2
into the islanded mode.
As shown in Fig. 11(b), the grid synchronization process
Central between t1 and t4 does not affect the power sharing accom-
console plished by the droop controls in the islanded operation. This
outcome shows that the proposed grid synchronization method
Main effectively preserve the relative phase angle difference and
controller voltage magnitude difference between DERC1 and DERC2
while adjusting their operation frequencies and output voltage
Load
magnitudes.
Test results in Fig. 11(b) shows errors in the sharing of
real power and reactive power. The finite resolution of the
phase angle look up table (2π × 10 −3 rad) with respect to
the droop slope (m 1 , m2 ) can be one potential cause. The
VAR consumption of the filter capacitor must be removed from
the reactive power calculation before the Q − V̇ controller.
However, it is estimated based on the capacitor name plate
value, thus the reactive power calculation may have certain
errors. The unbalance within the testbench, which comes from
the filter inductors, filter capacitors, and the three-phase line
chokes which emulate the power line impedance, may also
contribute to the power sharing errors.
Note that DERCs’ real power output P 1 , P2 , and reactive
power output Q 1 , Q2 show certain deviations in the grid-
connected mode as shown in Fig. 11(b). A power flow con-
trol [17] at PCC can be implemented in the central console to
adjust the droop control set-points of autonomous controllers
to mitigate such problems.
Fig. 12 compares the line-to-line voltages of the util-
ity grid, PCC, DERC1, and DERC2 at various instances.
After the frequency restoration is accomplished, v G,ab and
vP CC,ab have the same frequency, and v G,ab leads ahead
of vP CC,ab by 85.8◦ . The voltage magnitude difference be-
tween |vG,ab | = 212.6 Vrms and |vP CC,ab | = 206.7 Vrms
is also obvious. After the voltage magnitude equalization is
completed, The magnitude difference is effectively eliminated
and these voltage magnitudes become |v G,ab | = 214.0 Vrms
and |vP CC,ab | = 215.0 Vrms. By commencing the phase
angle synchronization, the phase angle difference driven down
 Voltage magnitude Bypass switch Voltage magnitude Bypass switch
equalization is closed equalization is closed
2 DERCs Frequency Phase angle 2 DERCs Frequency Phase angle
Islanded mode Islanded mode
are connected restoration synchronization are connected restoration synchronization
t0 t1 t2 t3 t4 t5 t0 t1 t2 t3 t4 t5
ωG ωG
377 377
4rad/sec 4rad/sec
θdiff
θdiff
0 0
4rad 4rad
Vdiff
0 Vdiff 0
10V 10V

ωPCC
377 377
ωPCC 20sec
4rad/sec
20sec
4rad/sec

(a) Detected information in the main controller. (ωG , ωP CC : X-axis: (a) Information in the main controller during the grid synchronization
20s/div, Y-axis: 4rad/sec/div; θdif f : X-axis: 20s/div, Y-axis: 4rad/div; process with 91 Hz communication bandwidth.
Vdif f : X-axis: 20s/div, Y-axis: 10V /div) Voltage magnitude Bypass switch
Voltage magnitude Bypass switch equalization is closed
2 DERCs Frequency Phase angle
equalization is closed Islanded mode
are connected restoration synchronization
2 DERCs Frequency Phase angle
are connected restoration synchronization
Islanded mode t0 t1 t2 t3 t4 t5
t0 t1 t2 t3 t4 t5 ωG
377
4rad/sec

0 1kW
0 θdiff
Load change P1 P2 4rad

0
1kVAR Vdiff
0
Load change Q1 Q2 10V

0 ωPCC
50kW
377
P01 P02 4rad/sec
20sec

0
20sec 20kVAR
Q01 Q02
(b) Information in the main controller during the grid synchronization
(b) Responses in the DERCs. (P1 , P2 : X-axis: 20s/div, Y-axis: 1kW/div; process with 65 Hz communication bandwidth.
Q1 , Q2 : X-axis: 20s/div, Y-axis: 1kV AR/div; P01 , P02 : X-axis: 20s/div,
Y-axis: 50kW/div; Q01 , Q02 : X-axis: 20s/div, Y-axis: 20kV AR/div) Fig. 13. Experimental test results with different communication band-
width. (ωG , ωP CC : X-axis: 20s/div, Y-axis: 4rad/sec/div; θdif f : X-axis:
Fig. 11. Experimental test results of grid synchronization process as the 20s/div, Y-axis: 4rad/div; Vdif f : X-axis: 20s/div, Y-axis: 15V /div)
rated power capacities of DERCs are the same.

to zero. At this point, v G,ab and vP CC,ab have the same
frequency, the same phase angle, and the same magnitude,
so their waveforms are closely matched. Finally the bypass
switch is closed and the DGS becomes grid-connected.
The proposed method achieves the grid synchronization by
transmitting the PCC information from the main controller to
the central console, and then to the autonomous controllers
through the RS-232 communication links. Fig. 13 shows the
grid synchronization test results of the proposed method under
slow communication with equivalent bandwidth of 91 Hz
and 65 Hz. Test results show that the proposed method can
accomplish the grid synchronization operation even with the
low-bandwidth communication.
VI. C ONCLUSION
The proposed method maintains the phase angles relation-
ship and voltage magnitude relationship among DERCs during
the synchronization process, therefore the proportional power
sharing accomplished in the islanded operation mode can be
maintained. Laboratory test results show the frequency, the
phase angle and the magnitude of the PCC voltage are matched
to those of the grid voltage without disturbing the real and
reactive power output of DERCs, and then the DGS moves into
the grid- connected mode smoothly. The proposed method is
built upon the foundation of the P − ω and Q − V̇ droop
controls of the autonomous controller within each DERC.
The central console only transmits the frequency, phase angle
and voltage magnitude. Based on these information, the au-
tonomous controller fine-tunes the droop control set-point, and
manipulates the output voltage of its DERC. This architecture
uphold the autonomous nature of the DGS by constraining the

Islanded mode
P-ω, Q-V Frequency Voltage magnitude
droop control restoration equalization
After frequency restoration After voltage magnitude equalization
0
vG,ab vPCC,ab 200V vG,ab vPCC,ab
10msec 10msec
0
vDERC1,ab , vDERC2,ab 0
vDERC1,ab , vDERC2,ab
Fig. 12. The variations of line-to-line voltage of the utility grid, PCC, DERC1, and DERC2 during the grid synchronization process. (VG,ab , VP CC,ab ,
VDERC1,ab , VDERC2,ab : X-axis: 10ms/div, Y-axis: 200V /div)
role of the central console in the synchronization process. Thus
the proposed method can operate with the very low bandwidth
communication.
ACKNOWLEDGMENT
This research is funded by the National Science Council of
Taiwan under grant NSC-98-2221-E-007-121-MY3.
R EFERENCES
[1] R. Lasseter, “Microgrids,” in Proc. IEEE Power Engineering Society
Winter Meeting, 2002, pp. 305–308.
[2] M. Barnes, J. Kondoh, H. Asano, J. Oyarzabal, G. Ventakaramanan,
R. Lasseter, N. Hatziargyriou, and T. Green, “Real-world microgrids-
an overview,” in IEEE International Conference on System of Systems
Engineering, 2007, pp. 1–8.
[3] F. Katiraei, R. Iravani, N. Hatziargyriou, and A. Dimeas, “Microgrids
management,” IEEE Power and Energy Magazine, vol. 6, no. 3, pp.
54–65, May./Jun. 2008.
[4] C. L. Chen, Y. Wang, J. S. Lai, Y. S. Lee, and D. Martin, “Design
of parallel inverters for smooth mode transfer microgrid applications,”
IEEE Transactions on Power Electronics, vol. 25, no. 1, pp. 6–15, Jan.
2010.
[5] J. Rocabert, G. M. S. Azevedo, A. Luna, J. M. Guerrero, J. I. Can-
dela, and P. Rodriguez, “Intelligent connection agent for three-phase
grid-connected microgrids,” IEEE Transactions on Power Electronics,
vol. 26, no. 10, pp. 2993–3005, Oct. 2011.
[6] M. C. Chandrokar, D. M. Divan, and R. Adapa, “Control of parallel
connected inverters in standalone ac supply systems,” IEEE Transactions
on Industry Applications, vol. 29, no. 1, pp. 136–143, Jan./Feb. 1993.
[7] M. C. Chandrokar, D. M. Divan, and B. Banerjee, “Control of distributed
ups systems,” in Proc. IEEE Power Electronics Specialists Conference,
1994, pp. 197–204.
[8] P. Piagi and R. Lasseter, “Autonomous control of microgrids,” in Proc.
IEEE Power Engineering Society General Meeting, 2006, p. 8pp.
[9] J. M. Guerrero, L. G. de Vicuna, J. Matas, M. Castilla, and J. Miret,
“Output impedance design of parallel-connected ups inverters with wire-
less load-sharing control,” IEEE Transactions on Industrial Electronics,
vol. 52, no. 4, pp. 1126–1135, Aug. 2005.
[10] C. K. Sao and P. W. Lehn, “Autonomous load sharing of voltage source
converters,” IEEE Transactions on Power Delivery, vol. 20, no. 2, pp.
1009–1016, Apr. 2005.
[11] C. T. Lee, C. C. Chu, and P. T. Cheng, “A new droop control method
for the autonomous operation of distributed energy resource interface
converters,” in Proc. IEEE Energy Conversion Congress and Exposition
(ECCE), 2010, pp. 702–709.
Bypass switch closes
Phase Grid-connected mode
synchronization
time
After phase angle synchronization After grid connection
200V vG,ab, vPCC,ab 200V vG,ab, vPCC,ab 200V
10msec 10msec
vDERC1,ab , vDERC2,ab vDERC1,ab , vDERC2,ab
[12] F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus, “Overview
of control and grid synchronization for distributed power generation
systems,” IEEE Transactions on Industrial Electronics, vol. 53, no. 5,
pp. 1398–1409, Oct. 2006.
[13] J. Rocabert, M. S. Azevedo, I. Candela, F. Blaabjerg, and P. Rodriguez,
“Connection and disconnection transients for micro-grids under unbal-
ance load condition,” in Proc. IEEE Power Electronics and Applications
(EPE 2011), 2011-14th European Conference, 2011, pp. 1–9.
[14] M. Rizo, E. Bueno, A. Dell’Aquila, M. Liserre, and R. A. Mastromauro,
“Generalized controller for small wind turbines working grid-connected
and stand-alone,” in Proc. IEEE Clean Electrical Power (ICCEP), 2011,
2011, pp. 51–55.
[15] Y. A. I. Mohamed and A. A. Radwan, “Hierarchical control system
for robust microgrid operation and seamless mode transfet in active
distribution systems,” IEEE Transactions on Smart Grid, vol. 2, no. 2,
pp. 352–362, Jun. 2011.
[16] J. Kim, J. M. Guerrero, P. Rodriguez, R. Teodorescu, and K. Nam,
“Mode adaptive droop control with virtual output impedances for an
inverter-based flexible ac microgrid,” IEEE Transactions on Power
Electronics, vol. 26, no. 3, pp. 689–701, Mar. 2011.
[17] J. M. Guerrero, J. C. Vasquez, J. Matas, L. G. de Vicuna, and M. Castilla,
“Hierarchical control of droop-controlled ac and dc microgrids-a general
approach toward standardization,” IEEE Transactions on Industrial
Electronics, vol. 58, no. 1, pp. 158–172, Jan. 2011.
[18] L. N. Arruda, S. M. Silva, and B. J. C. Filho, “Pll structures for utility
connected systems,” in Proc. IEEE Industry Applications Conference,
Thirty-Sixth IAS Annual Meeting, 2001, pp. 2655–2660.
[19] V. Kaura and V. Blasko, “Operation of a phase locked loop system
under distorted utility conditions,” IEEE Transactions on Industry Ap-
plications, vol. 33, no. 1, pp. 58–63, Jan./Feb. 1997.
[20] S. K. Chung, “A phase tracking system for three phase utility interface
inverters,” IEEE Transactions on Industry Applications, vol. 15, no. 3,
pp. 431–438, May 2000.
[21] T. G. Habetler, “A space vector-based rectifier regulator for ac/dc/ac
converters,” IEEE Transactions on Power Electronics, vol. 8, no. 1, pp.
30–36, January 1993.
 Chia-Tse Lee was born in Tainan, Taiwan in 1985.
He received the B.S. degree in electrical engineer-
ing from National Tsing Hua University, Hsinchu,
Taiwan in 2007, where he is currently pursuing the
Ph.D. degree.
His research interests include power electronics on
distributed power systems and applications of power
converter controls.

Ruei-Pei Jiang was born in Taichung, Taiwan in

1985. He received the B.S. degree in electrical engi-
neering from Feng Chia University, Taichung, Tai-
wan in 2008 and M.S. degree in electrical engineer-
ing from National Tsing Hua University, Hsinchu,
Taiwan in 2011 respectively. He is currently with
the Taiwan Army. His military service will end in
September 2012.
His research interests include power electronics on
distributed power systems and applications of power
converter controls.

Po-Tai Cheng (S’96-M’99-SM’09) received the

B.S. degree from National Chiao Tung University,
Hsinchu, Taiwan in 1990 and Ph.D. degree from
the University of Wisconsin, Madison, WI, USA in
1999.
He is currently a Professor in the Department of
Electrical Engineering, National Tsing Hua Univer-
sity, Hsinchu, Taiwan. He is an associate editor for
IEEE Transactions on Power Electronics and IEEE
Transactions on Industry Applications. His research
interests include power quality issues, high power
converters, power electronics technologies for smart grid and microgrid.