School of Electrical Engineering and Computing

Computer Science And Engineering Program

Computer Architecture and Organization (CSE3203)

Assignment 1

SUBMITTED TO INSTRUCTOR SIMEGENEW Y. ALABA

Submission date 26/01/2018

 Acorn RISC Machine (ARM)
The ARM architecture refers to a processor architecture that has evolved from RISC design
principles and is used in embedded systems.
The first RISC microprocessor for commercial use Market-leader and for low-power and
cost-sensitive embedded applications.
The ARM is a Reduced Instruction Set Computer (RISC), as it incorporates these typical
RISC architecture
features:

• a large uniform register file

• a load/store architecture, where data-processing operations only operate on register
contents, not directly on memory contents
• simple addressing modes, with all load/store addresses being determined from register
contents and instruction fields only
• uniform and fixed-length instruction fields, to simplify instruction decode.

1. Register organization
 ARM has 37 registers in total, all of which are 32‐bits long.
– 1 dedicated program counter
– 1 dedicated current program status register
– 5 dedicated saved program status registers
– 30 general purpose registers
 16 visible, R0 – R15
 Others speed up the exception process
 Special roles:
 Hardware
o R14 – Link Register (LR):
 optionally holds return address or branch instructions
 Register 14 is the Link Register (LR). This register holds the
address of the next
 instruction after a Branch and Link (BL or BLX) instruction, which
is the instruction
used to make a subroutine call.
o R15 – Program Counter (PC)
-When the processor is executing in ARM state:
– All instructions are 32 bits in length
– All instructions must be word aligned
– Therefore the PC value is stored in bits [31:2] with bits [1:0] equal to zero (as
instruction cannot be halfword or byte aligned).

 Software
o R13 - Stack Pointer (SP)
R13 is used by the PUSH and POP instructions in T variants, and by the SRS and
RFE instructions from ARMv6.
 o Current Program Status Register (CPSR)
o Saved Program Status Register (SPSR)
o On exception, entering mod mode:

2. ARM instruction set

2.1 Instruction format (Instruction set encoding)
All instructions in the ARM architecture are 32 bits long and follow a regular format (Figure
13.10). The first four bits of an instruction are the condition code. all ARM instructions can
be conditionally executed. The next three bits specify the general type of instruction. For
most instructions other than branch instructions, the next five bits constitute an opcode and/or
modifier bits for the operation. The remaining 20 bits are for operand addressing. The regular
structure of the instruction formats eases the job of the instruction decode units.

2.2 instruction types

We have two instruction sets:
1 ARM (Standard 32-bit instruction set)
2 THUMB
o 16-bit compressed form
o Code density better than most CISC
o Dynamic decompression in pipeline
ARM instruction set
The ARM instruction set can be divided into six broad classes of instruction:
• Branch instructions
• Data-processing instructions
• Status register transfer instructions
 • Load and store instructions
• Coprocessor instructions
• Exception-generating instructions
 Data Processing Instructions
They are move, arithmetic, logical, comparison
and multiply instructions.

 Arithmetic and logical operations

 3-address format:
 Two 32-bit operands
o (op1 is register, op2 is register or immediate)
 32-bit result placed in a register
 Barrel shifter for op2 allows full 32-bit shift
o within instruction cycle
e.g.:
if (z==1) R1=R2+(R3*4)
compiles to EQADDS R1,R2,R3, LSL #2( SINGLE INSTRUCTION ! )
Data Transfer Instructions
 Load/store instructions
 Used to move signed and unsigned
 Word, Half Word and Byte to and from registers
 Can be used to load PC
 (if target address is beyond branch instruction range)
 e.g.:Mov r0,r1 Mov r2,#10
Block Transfer Instructions
 Load/Store Multiple instructions (LDM/STM)
 Whole register bank or a subset copied to memory or restored
with single instruction
Swap Instruction
 Exchanges a word between registers
 Two cycles but single atomic action
 Support for RT semaphores
Modifying the Status Registers
 Only indirectly
 MSR moves contents from CPSR/SPSR to selected GPR
 RS moves contents from selected GPR to CPSR/SPSR
 Only in privileged modes
Multiply Instructions
 Integer multiplication (32-bit result)
 Long integer multiplication (64-bit result)
 Built in Multiply Accumulate Unit (MAC)
 Multiply and accumulate instructions add product to running total
Software Interrupt instruction (SWI )
 Forces CPU into supervisor mode
 Suitable for running privileged code and making OS calls
 Branching Instructions
 Branch (B): jumps forwards/backwards up to 32 MB
 Branch link (BL): same + saves (PC+4) in LR
 Suitable for function call/return
 Condition codes for conditional branches
2.3 Data types
ARM Data Types
• Support data types of 8 (byte), 16 (half word), and 32 (word) bits in length.
• Normally, halfword access should be halfword aligned and word accesses
should be word aligned.
• ARM processor does not provide floating point hardware, which saves
power and area.
• If required it must be implement in software.
• Can be configure to be little Endian or big Endian mode.
For nonaligned access attempts, the architecture supports three alternatives.

1. Default Case
– The address is treated as truncated, with address bits[1:0] treated as zero
for word accesses, and address bit[0] treated as zero for halfword accesses.
2• Alignment checking: When the appropriate control bit is set, a data abort signal indicates
an alignment fault for attempting unaligned access.
3 .Unaligned access: When this option is enabled, the processor uses one or more
memory accesses to generate the required transfer of adjacent bytes transparently to the
programmer.

ENDIAN SUPPORT :A state bit (E-bit) in the system control register is set and cleared under
program control using the SETEND instruction

2.4 Addressing modes

* The ARM architecture departs somewhat from this tradition by providing a relatively
rich set of addressing modes. These modes are most conveniently classified with
respect to the type of instruction.
* Register
• Value is in a register
– Add R4, R3
– Regs[R4] ¬ Regs[R4] + Regs[R3]
* Immediate
• Constant value is in the instruction
– Add R4, #3
– Regs[R4] ¬ Regs[R4] + 3
* Displacement
• Relative addressing for access to local variables
Add R4, 100(R1) Regs[R4] ¬ Regs[R4] + Mem[100+Regs[R1]]

* Indirect or Register deferred

• Address of the operand is in a register
 Add R4, (R1) Regs[R4] ¬ Regs[R4] + Mem[Regs[R1]]
* Indexed
• Base + index addressing; useful in array addressing
Add R3, (R1+R2) Regs[R3] ¬ Regs[R3] + Mem[Regs[R1]+Regs[R2]]
* Direct or Absolute
• Static addressing for access to local variables
Add R1, (1001) Regs[R1] ¬ Regs[R1] + Mem[1001]
* Memory indirect
• The address of the address of the operand is in a register
Add R1, @(R3) Regs[R1] ¬ Regs[R1] + Mem[Mem[Regs[R3]]]
* Auto-increment or Auto-decrement
• Useful for stepping through arrays or accessing stack elements
– Add R1, (R2)+
• Regs[R1] ¬ Regs[R1] + Mem[Regs[R2]]
• Regs[R2] ¬ Regs[R2] + d
– Add R1, -(R2)
• Regs[R2] ¬ Regs[R2] - d
• Regs[R1] ¬ Regs[R1] + Mem[Regs[R2]]
* 3. ARM CACHE ORGANIZATION
The ARM cache organization has evolved with the overall architecture of the ARM
family, reflecting the relentless pursuit of performance that is the driving force for
all microprocessor designers.

All of the ARM designs use a set-associative cache, with the degree of associativity and
the line size varying.
An interesting feature of the ARM architecture is the use of a small first-in first out
(FIFO) write buffer to enhance memory write performance. The write buffer is interposed
between the cache and main memory and consists of a set of addresses and a set of data
words. The write buffer is small compared to the cache,
and may hold up to four independent addresses.