Beruflich Dokumente
Kultur Dokumente
6N135, 6N136
Digital Logic Isolation
Unit: mm
Line Receiver
Power Supply Control
Switching Power Supply
Transistor Inverter
The TOSHIBA 6N135 and 6N136 consists of a high emitting diode and a
one chip photo diode−transistor.
Each unit is 8−lead DIP package.
Pin Configurations
1 8
2 7
3 6
4 5
1 : N.C.
2 : ANODE
3 : CATHODE
4 : N.C.
5 : EMITTER
6 : COLLECTOR
7 : BASE, ANODE
8 : CATHODE
ICC
8 VCC
IF IB
7 VB
VF 2 IO
6 VO
3
5 GND
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if
the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc.).
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Electrical Characteristics
Over Recommended Temperature (Ta = 0°C~70°C unless otherwise noted)
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Switching Specifications
(unless otherwise specified. Ta = 25°C, VCC = 5V, IF = 16mA)
Test
Characteristic Symbol Test Condition Min Typ. Max Unit
Circuit
(Note 8) DC current transfer ratio is defined as the ratio of output collector current, IO, to the forward LED input current,
IF, times 100%.
(Note 9) Device considered a two−terminal device: Pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted
together.
(Note 10) Common mode transient immunity in logic high level is the maximum tolerable (positive) dVCM / dt on the
leading edge of the common mode pulse, VCM, to assure that the output will remain in a logic high state (i.e.,
VO > 2.0V).
Common mode transient immunity in logic low level is the maximum tolerable (negative) dVCM / dt on the
trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state
(i.e., VO < 0.8V).
(Note 11) The frequency at which the AC output voltage is 3dB below the low frequency asymptote.
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Test Circuit 1.
PULSE GEN.
Zo = 50Ω IF
IF tf = 5ns 1 8 5V
10% DUTY
RL
0 5V 2 7
CYCLE
VO 3 6 VO
(*)
1.5V 1.5V IF CL
VOL 4 5
100Ω
MONITOR
tpHL tpLH
Test Circuit 2.
IF 1 8 5V
RL
tr, tf = 8ns 2 7
10V 10% A 3
90% 6 VO
VCM
10% 90% B
0V 4 5
tr tf
VFF VCM
VO 5V
SWITCH AT A : IF = 0mA
PULSE GEN.
VO VOL
SWITCH AT B : IF = 16mA
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IF – V F ΔVF / ΔTa – IF
100 -2.6
Ta = 25°C
10
5 -2.2
IF
3
Forward current
1 -2.0
0.5
0.3
-1.8
0.1
0.05 -1.6
0.03
0.01 -1.4
1.0 1.2 1.4 1.6 1.8 2.0 0.1 0.3 0.5 1 3 5 10 30
IOH (1) – Ta IO - IF
300 10
5
100 3
(mA)
High level output current
50
1
IOH(1) (nA)
30
IO
0.5
Output current
0.3
10
5 0.1
3 VCC = 5V
0.05
VO = 0.4V
0.03
Ta = 25°C
1
0.6 0.01
0 40 80 120 160 0.1 0.3 0.5 1 3 5 10 30 50 100 300
IO / IF - IF IO / IF – Ta
100 1.2
VCC = 5V
VO = 0.4V
50 1.0
Current transfer ratio
30 Ta = -25°C
I O / IF
0.8
IO / IF (%)
25°C
Notmalized
10 0.6
100°C Normalized
TO :
5 0.4 IF = 16mA
3 VCC = 4.5V
0.2 VO = 0.4V
1 0
0.3 0.5 1 3 5 10 30 50 -40 -20 0 20 40 60 80 100
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IO – V O V O – IF
5
30mA VCC = 5V
10 Ta = 25°C IF VCC=5V
25mA
(V )
4
(mA)
8 RL
20mA
VO
VO
IO
3
6 15mA
Output voltage
Output current
Ta = 25℃
2 RL = 2kΩ
10mA
4
3.9Ω
IF = 5mA 10Ω
2 1
0 0
0 1 2 3 4 5 6 7 0 4 8 12 16 20 24
tpHL, tpLH – RL
5
IF = 16mA
3
VCC = 5V
tpLH
Propagation delay time
Ta = 25°C
tpHL, tpLH (μs)
0.5
0.3
tpHL
0.1
1 3 5 10 30 50 100
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