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// Class: CSCI 401 Computer Architecture
// Term: SPR11
// Name(s):
//
// Lab #1: Instruction Fetch Stage

// -*- Mode: Verilog -*-

// Filename : mem.v
// Description : The instruction memory module
// of the IF stage of the pipeline
// Authors : George M. Georgiou and Scott McWilliams
// Created On : 2/06/2003
// Modified On : 4/5/2011
// Modified By : Jason Fredrick and David Sturgeon

module memory (
output reg [31:0] data, // Output of Instruction Memory
input wire [31:0] addr // Input of Instruction Memory
);

// Register Declarations
reg [31:0] MEM[0:127]; // 128 words of 32-bit memory

// Initialize Registers
initial begin
MEM[0] <= 'hA00000AA;
MEM[1] <= 'h10000011;
MEM[2] <= 'h20000022;
MEM[3] <= 'h30000033;
MEM[4] <= 'h40000044;
MEM[5] <= 'h50000055;
MEM[6] <= 'h60000066;
MEM[7] <= 'h70000077;
MEM[8] <= 'h80000088;
MEM[9] <= 'h90000099;
end

always @ (addr) data <= MEM[addr];

endmodule // memory
// `timescale 1us / 1us
// `include "registerfile.v"

// Note: each memory location should be initialized to have value of its

address

module mem_test;
wire [31:0] data_out;

reg [31:0] address;

reg [31:0] data;
reg mem_read, mem_write;

initial
begin
// $dumpfile("reg_test.vcd");
// $dumpvars(0, reg_test);

mem_read = 1;
mem_write = 0;
address = 32'b00000001;

#1 mem_read = 0;
mem_write = 1;
address = 32'b00000001;
data = ~address;

#1 mem_read = 1;
mem_write = 0;
address = 32'b00000010;

#1 mem_read = 1;
mem_write = 1;
address = 32'b00000010;
data = ~address;

#1 mem_read = 1;
mem_write = 0;
address = 32'b00000100;

#1 mem_read = 0;
mem_write = 1;
address = 32'b00000100;
data = ~address;

#1 mem_read = 1;
mem_write = 0;
address = 32'b00001000;

#1 mem_read = 1;
 mem_write = 1;
address = 32'b00001000;
data = ~address;

#1 $finish;
end

memory data_mem(.address(address), .write_data(write_data),

.mem_read(mem_read), .mem_write(mem_write),
.data_out(data_out));
Endmodule
`timescale 1ns / 1ps

module pipeline();

// IFETCH
wire [31:0] IF_ID_instrout, IF_ID_npcout;
wire MEM_PCSrc;
wire [31:0] EX_MEM_NPC;

IFETCH IFETCH1 (.MEM_PCSrc(MEM_PCSrc),

.EX_MEM_NPC(EX_MEM_NPC),
.IF_ID_instr(IF_ID_instrout),
.IF_ID_npc(IF_ID_npcout));

initial begin
#24 $stop;
end

// IDECODE
wire [4:0] MEM_WB_rd;
wire MEM_WB_regwrite;
wire [31:0] WB_mux5_writedata;
wire [1:0] wb_ctlout;
wire [2:0] m_ctlout;
wire regdst, alusrc;
wire [1:0] aluop;
wire [31:0] npcout, rdata1out, rdata2out, s_extendout;
wire [4:0] instrout_2016, instrout_1511;

IDECODE IDECODE2 (.IF_ID_instrout(IF_ID_instrout),

.IF_ID_npcout(IF_ID_npcout),
.MEM_WB_rd(MEM_WB_rd),

.MEM_WB_regwrite(MEM_WB_regwrite),

.WB_mux5_writedata(WB_mux5_writedata),
.wb_ctlout(wb_ctlout),
.m_ctlout(m_ctlout),
.regdst(regdst),
.aluop(aluop),
.alusrc(alusrc),
.npcout(npcout),
.rdata1out(rdata1out),
.rdata2out(rdata2out),

.s_extendout(s_extendout),

.instrout_2016(instrout_2016),

.instrout_1511(instrout_1511));

// EXECUTE
wire [1:0] wb_ctlout_pipe;
wire branch, memread, memwrite;
wire zero;
 wire [31:0] alu_result, rdata2out_pipe;
wire [4:0] five_bit_muxout;

//Instantiate Execute Unit Here

// MEMORY
wire MEM_WB_memtoreg;
wire [31:0] read_data, mem_alu_result;

//Instantiate Memory Unit Here

// WRITEBACK

//Instantiate Write Back Unit Here

endmodule // pipeline
module reg_test;
wire [31:0] data_rs, data_rt;

reg [4:0] addr_rs, addr_rt, write_addr;

reg [31:0] write_data;
reg regWrite;

initial
begin
addr_rs = 0;
addr_rt = 1;
regWrite = 0;

#1 addr_rs = 2;
addr_rt = 3;
write_addr = 3;
write_data = 100;

#1 addr_rs = 4;
addr_rt = 5;
regWrite = 1;

#1 regWrite = 0;
addr_rt = 3;

#1 addr_rs = 6;
regWrite = 1;
write_addr = 6;
write_data = 100;

#1 $finish;
end

registerfile regfile(.data_rs_out(data_rs), .data_rt_out(data_rt),

.rs_in(addr_rs), .rt_in(addr_rt),
.write_addr_in(write_addr),
.write_data_in(write_data), .regWrite_in(regWrite));

endmodule
// `include "alu.v"

module alu_test;
reg [31:0] a, b;
reg [2:0] control;

wire [31:0] alu_out;

wire zero;

parameter ADD = 3'b010;

parameter SUB = 3'b110;
parameter AND = 3'b000;
parameter OR = 3'b001;
parameter SOL = 3'b111;

initial
begin
// $dumpfile("alu_test.vcd");
// $dumpvars(0, alu_test);
a <= 32'h00ff00ff;
b <= 32'h11111111;
control <= ADD;

#1 control <= SUB;

a <= 0;
b <= 1;

#1 control <= AND;

a <= 32'h0f0f0f0f;
b <= 32'hffffffff;

#1 control <= OR;

a <= 32'h0f0f0f0f;
b <= 32'hf0f0f0f0;

#1 control <= SOL;

a <= 32'hffffffff;
b <= 32'h0fffffff;

#1 b <= 32'hffffffff;
a <= 32'h0fffffff;

#1 control <= 3'bxxx;

#1 $finish;
end

alu alu_unit(.a_in(a), .b_in(b), .control(control),

.result_out(alu_out), .zero_out(zero));

endmodule