36 Elsevier-ARM Sy

LPC2148 - Interrupts
Dr.R.Sundaramurthy
Department of EIE
Pondicherry Engineering College
sundar@pec.edu
Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Interrupts , IRQs , ISRs
• Interrupt : “An interrupt is a signal sent to the CPU which indicates
that a system event has a occurred which needs immediate
attention“.
• Interrupt ReQuest (IRQ) can be thought of as a special request to

the CPU to execute a function(small piece of code) when an
interrupt occurs.
• ISR : This function or ‘small piece of code’ is technically called an

‘Interrupt Service Routine‘ or ‘ISR‘.
• So when an IRQ arrives to the CPU , it stops executing the code

current code and start executing the ISR. After the ISR execution
has finished the CPU gets back to where it had stopped.

How We classify them ?
We Classify them as 2 types :
• Fast IRQs or FIQs
• Normal IRQs or IRQs which can be further
classified as :
– Vectored IRQ
– Non-Vectored IRQ.
FIQ Vectored IRQ

Interrupts
Normal IRQ Non Vectored IRQ

Types of Interrupts in LPC2148
Interrupts are Handled by Vectored Interrupt Controller(VIC)
Types of Interrupts in LPC2148
• Fast Interrupt Request i.e FIQ : which has highest priority
• Vectored Interrupt Request i.e Vectored IRQ : which has

‘middle’ or priority between FIQ and Non-Vectored IRQ.
• Non-Vectored IRQ : which has the lowest priority.

What does Vectored mean ?
• ‘Vectored‘ means that the CPU is aware of the address of
the ISR when the interrupt occurs
• Non-Vectored means that CPU doesn’t know the address

of the ISR (nor) the source of the IRQ when the interrupt
occurs.
• For Non – Vectored interrupts , CPU needs to be supplied

by the ISR address.
• For the Vectored interrupts , the System internally

maintains a table called IVT or Interrupt Vector Table which
contains the information about Interrupts sources and their
corresponding ISR address.
How Non-Vectored Interrupts are
handled?
• Non-Vectored ISRs doesn’t point to a unique ISR
• The CPU needs to be supplied with the address of the

‘default’ or a ‘common’ ISR that needs to be executed
when the interrupt occurs.
• In LPC2148 this is facilitated by a register called

‘VICDefVectAddr‘.
• The user must assign the address of the default ISR to

this register for handling Non-Vectored IRQs.

In a Nut Shell
• Vectored IRQ(VIRQ) has dedicated IRQ service
routine for each interrupt source
• Non-Vectored IRQ(NVIRQ) has the same IRQ

service routine for all Non-Vectored
Interrupts.

How Many Possible Interrupt Sources are there ?
• There are 22 Interrupt Sources in LPC2148
• But there are only 16 Slots in in the Vectored
Interrupt Controller (VIC) 0 to 15.
• These 22 possible sources have to be shared by using
Slots 0 to 15 of VIC
• Slot 0 Highest Priority
• Slot 15 Lowest Priority

SFRs Involved
• VICIntSelect (R/W) 0 = IRQ, 1 = FIQ
• VICIntEnable (R/W) Enable Selective Interrupt Source
• VICIntEnClr (R/W) Disable Selective Interrupt Source
• VICIRQStatus (R) to know the status of enabled interrupt
• VICFIQStatus (R) to know the status of enabled FIQ
• VICSoftInt to trigger a software interrupt
• VICSoftIntClear to clear software interrupt
• VICVectCntl0 to VICVectCntl15 Assign interrupt source
• VICVectAddr0 to VICVectAddr15 Assign interrupt address
• VICVectAddr Holds the address of currently active interrupt
• VICDefVectAddr Holds the addressof Non-Vectored ISR

VICIntSelect (R/W)
• This register is used to select an interrupt as IRQ or as
FIQ.
• Writing a 0 at a given bit location will make the
corresponding interrupt as IRQ
• Writing a 1 will make it FIQ.
• For e.g if you make Bit 4 as 0 then the corresponding
interrupt source i.e TIMER0 will be IRQ else if you make
Bit 4 as 1 it will be FIQ instead.
• By default all interrupts are selected as IRQ. Note that
here IRQ applies for both Vectored and Non-Vectored
IRQs.

VICIntEnable (R/W)
• This is used to enable interrupts.
• Writing a 1 at a given bit location will make
the corresponding interrupt Enabled.
• If this register is read then 1′s will indicated
enabled interrupts and 0′s as disabled
interrupts.
• Writing 0′s has no effect.

VICIntEnClr (R/W)
• This register is used to disable interrupts.
• This is similar to VICIntEnable expect writing a
1 here will disabled the corresponding
Interrupt.
• This has an effect on VICIntEnable since
writing at bit given location will clear the
corresponding bit in the VICIntEnable Register.
• Writing 0′s has no effect

VICIRQStatus (R)
• This register is used for reading the current

status of the enabled IRQ interrupts.
• If a bit location is read as 1 then it means that
the corresponding interrupt is enabled and
active.

VICFIQStatus (R)
• This register is used for reading the current
status of the enabled FIQ interrupts.
• If a bit location is read as 1 then it means that

the corresponding interrupt is enabled and
active.

VICSoftInt
• This register is used to generate interrupts
using software i.e manually generating
interrupts using code
• If you write a 1 at any bit location then the
correspoding interrupt is triggered i.e. it forces
the interrupt to occur.
• Writing 0 here has no effect.

VICSoftIntClear
• This register is used to clear the interrupt
request that was triggered(forced) using
VICSoftInt.
• Writing a 1 will release(or clear) the forcing of
the corresponding interrupt.

VICVectCntl0 to VICVectCntl15
• These are the Vector Control registers.

• These are used to assign a particular interrupt source
to a particular slot.
• As mentioned before slot 0 i.e VICVectCntl0 has highest
priority and VICVectCntl15 has the lowest.
• Each of this registers can be divided into 3 parts : {Bit0
to bit4} , {Bit 5} , {and rest of the bits}.
• The first 5 bits i.e Bit 0 to Bit 4 contain the number of
the interrupt request which is assigned to this slot. The
interrupt source numbers are given in the table below :
• The 5th bit is used to enable the vectored IRQ slot by
writing a 1 31 . . . 6 EN N4 N3 N2 N1 N0

Important Note
• Note that if the vectored IRQ slot is disabled it will not disable
the interrupt but will change the corresponding interrupt to
Non-Vectored IRQ.
• Enabling the slot here means that it can generate the address
of the ‘dedicated Interrupt handling function (ISR)’
• Disabling it will generate the address of the ‘common/default

Interrupt handling function (ISR)’ which is for Non-Vectored
ISR.
• In simple words if the slot is enabled it points to ‘specific and

dedicated interrupt handling function’ and if its disable it will
point to the ‘default function’.
VICVectAddr0 to VICVectAddr15
(16 registers in all)
• For Vectored IRQs these register store the
address of the function that must be called
when an interrupt occurs.
• Note – If you assign slot 3 for TIMER0 IRQ then
care must be taken that you assign the
address of the interrupt function to
corresponding address register .. i.e
VICVectAddr3 in this example.

VICVectAddr
• This must not be confused with the above set of
16 VICVecAddrX registers.
• When an interrupt is Triggered this register holds
the address of the associated ISR i.e the one
which is currently active.
• Writing a value i.e dummy write to this register
indicates to the VIC that current Interrupt has
finished execution.
• The only place we’ll use this register .. is at
the end of the ISR to signal end of ISR execution.

VICDefVectAddr
• This register stores the address of the

“default/common” ISR that must be called
when a Non-Vectored IRQ occurs.

How to Write an ISR
Method – 1 Method – 2
__irq void myISR (void) void myISR (void) __irq
{ {
... ...
} }
For 8051
void myISR (void) interrupt 1
{
...
}

A Simple 3 Step Process to Enable a
Vectored IRQ
• Step – 1 : Enable the IRQ by setting the
appropriate bit of VICIntEnable to ’1′.
• Step-2 : Identify the interrupt source number

and assign it to VICVectCntlX.
• Step-3 : Assign the address of the related ISR

to VICVectAddrX.

Example – Enabling Timer0 Interrupt
• First we need to enable the TIMER0 IRQ itself!
Hence , from Table we get the bit number
to Enable TIMER0 Interrupt which is Bit number
4. Hence we must make bit 4 in VICIntEnable to
’1′.
• Next , from Table we get the interrupt source
number for TIMER0 which is decimal 4 and OR it
with (1<<5) [i.e 5th bit=1 which enables the slot]
and assign it to VICVectCntlX.
• Next assign the address of the related ISR to
VICVectAddrX.

Template Code
VICIntEnable |= (1<<Y) ;
VICVectCntlX = (1<<5) | Y ;
VICVectAddrX = (unsigned) myISR;

Assigning TIMER0 Interrupt to Slot0
VICIntEnable |= (1<<4) ; // Enable TIMER0 IRQ
VICVectCntl0 = (1<<5) | 4 ; //5th bit must 1 to

enable the slot
VICVectAddr0 = (unsigned) myISR;

//Vectored-IRQ for TIMER0 has been configured

ISR
• First when we have only one ‘internal’ source of interrupt in
TIMER0 i.e an MR0 match event which raises an IRQ.
__irq void myISR(void)

{
long int regVal;
regVal = T0IR; // read the current value in T0's Interrupt
Register
//... MR0 match event has occured .. do something here
T0IR = regval; // write back to clear the interrupt flag
VICVectAddr = 0x0; // The ISR has finished!
}

Important Note
• Each Peripheral in lpc2148 has only 1 IRQ associated with it.
• But inside each device there may be different sources which can raise
an interrupt
• Like the TIMER0 peripheral has 4 match + 4 capture registers and any
one or more of them can be configured to trigger an interrupt.
• Hence such devices have a dedicated interrupt register which contains
a flag bit for each of these source(For Timer block its ‘T0IR‘).
• So , when the ISR is called first we need to identify the actual source of
the interrupt using the Interrupt Register and then proceed
accordingly.
• Also just before , when the main ISR code is finished we also need to
acknowledge or signal that the ISR has finished executing for the
current IRQ which triggered it.
• This is done by clearing the flag(i.e the particular bit) in the device’s
interrupt register and then by writing a zero to VICVectAddr register
which signifies that interrupt has ISR has finished execution
successfully.
Interrupt Examples

Timer0 Match Interrupts

Interrupt Enable register
(VICIntEnable)

Vector Control registers
(VICVectCntl0)

T0IR

T0MCR

Problem-1
• Design a LPC2148 based system to perform
the following tasks.
• Task1 Blink an LED at P1.31 using software
delay.
• Task2 Generate a square wave at 1KHz @
P1.25 using Timer0 Match Interrupt

Timer – Match0 Interrupt
C1
1
33pF U1
X1 62
XTAL1 P0.0/TxD0/PWM1
19
61 21
C2 XTAL2 P0.1/RxD0/PWM3/EINT0
22
P0.2/SCL0/CAP0.0
2
3 26
RTXC1 P0.3/SDA0/MAT0..0/EINT1
5 27
RTXC2 P0.4/SCK0/CAP0.1/AD0.6
33pF 29
P0.5/MISO0/MAT0.1/AD0.7
57 30
C3 RST P0.6/MOSI0/CAP0.2/AD1.0
31
P0.7/SSEL0/PWM2/EINT2
33
P0.8/TxD1/PWM4/AD1.1
34
1
P0.9/RxD1/PWM6/EINT3
22pF 35
P0.10/RTS1/CAP1.0/AD1.2
X2 P0.11/CTS1/CAP1.1/SCL1
37
38
C4 P0.12/DSR1/MAT1.0/AD1.3
39
P0.13/DTR1/MAT1.1/AD1.4
2
41
P0.14/DCD1/EINT1/SDA1
45
P0.15/RI1/EINT2/AD1.5
22pF
46
+3.3V P0.16/EINT0/MAT0.2/CAP0.2
47
P0.17/CAP1.2/SCK1/MAT1.2
53
P0.18/CAP1.3/MISO1/MAT1.3
54
P0.19/MAT1.2/MOSI1/CAP1.2
55
P0.20/MAT1.3/SSEL1/EINT3
1
P0.21/PWM5/AD1.6/CAP1.3
R1 P0.22/AD1.7/CAP0.0/MAT0.0
2
1K 58
P0.23
9
P0.25/AD0.4/AOUT
10
P0.26/AD0.5
11
P0.27/AD0.0/CAP0.1/MAT0.1
13
P0.28/AD0.1/CAP0.2/MAT0.2
C5 P0.29/AD0.2/CAP0.3/MAT0.3
14
100pF 15
P0.30/AD0.3/EINT3/CAP0.0
17
+3.3V P0.31
A
16
P1.16/TRACEPKT0
12
P1.17/TRACEPKT1 B
49 8
VBAT P1.18/TRACEPKT2
4
P1.19/TRACEPKT3 C
63 48
VREF P1.20/TRACESYNC
7 44
V3A P1.21/PIPESTAT0 D
51 40
V3 P1.22/PIPESTAT1
43 36
V3 P1.23/PIPESTAT2
23 32
V3 P1.24/TRACECLK
28
P1.25/EXTIN0
59 24
VSSA P1.26/RTCK
50 64
VSS P1.27/TDO
42 60
VSS P1.28/TDI
25 56
18
VSS P1.29/TCK
52
LAMP
VSS P1.30/TMS
6 20
VSS P1.31/TRST
LPC2138 LED-YELLOW

void initInterrupt(void)
{
VICVectCntl0 = (0x01 << 5) | 4 ;

//(i.e bit5 = 1) -> to enable Vectored
IRQ slot
VICVectAddr0 = (unsigned) T0ISR;
//Pointer Interrupt Function (ISR)
VICIntEnable = 0x01 << 4; //Enable

timer0 int
}

void initTimer0(void)
{ Method -1
T0PR = 60-1; Reset Timer after Match
// Pclk = 60MHz, ft = 1MHz ,

// Div = 60x10^6/1x10^6 = 60
T0CTCR = 0x00; // Configure as Timer
T0TCR = 0x02; // Clear TC and PC
T0MR0 = 500-1; // 500us
T0MCR |= 0x03 ; // Reset after Match

//Set bit0 & Bit1 to High which is
//Interrupt on MR0, & RESET ON MR0
T0TCR = 0x01; // Enable TC

}
void T0ISR(void) __irq
{
long int temp;
temp = T0IR ;
if (temp & 0x01) // MR0 Interrupt

{
Squarewave = ~( Squarewave);
writepin(25, Squarewave);
}
T0IR = temp; // Clear T0IR

VICVectAddr = 0x00; // Dummy Write
}

{ Method -2
T0PR = 60-1; Don’t Reset Timer after Match
// Pclk = 60MHz, ft = 1MHz ,
// Div = 60x10^6/1x10^6 = 60
T0MR0 = 500-1; // 500us
T0MCR |= 0x01 ; //No Reset.

//Set bit0 & Bit1 to High which is
//Interrupt on MR0,

}
{
long int temp;
temp = T0IR ;

{
T0MR0 = T0MR0 + 500;// Increment!
Squarewave = ~( Squarewave);
writepin(25, Squarewave);
}
T0IR = temp; // Clear T0IR

VICVectAddr = 0x00; // Dummy Write
}

#include<lpc214x.h>
#include "GPIO.h"
#include "timer.h"
#include "UART.h"
#include "timerinterrupt.h"
int main(void)
{
initPLL(); // 60 MHz Pclk
initInterrupt();
initTimer0();
while(1)
{
writepin(31,1); // Background Task
delay();
writepin(31,0);
delay();
}
}
Problem-2
• Design a LPC2148 based system to perform the
following tasks.
• Task1 Blink an LED at P1.31 using software delay.
• Task2 Generate a square wave at 500Hz @ P1.25
using Timer0 Match Interrupt
• Task3 Generate a square wave at 1KHz @ P1.26

Schematic
C1
1
33pF U1
X1 62
19
61 21
22
P0.2/SCL0/CAP0.0
2
3 26
5 27
33pF 29
57 30
31
33
34
1
22pF 35
P0.10/RTS1/CAP1.0/AD1.2
37
38
C4 P0.12/DSR1/MAT1.0/AD1.3
39
P0.13/DTR1/MAT1.1/AD1.4
2
41
45
22pF
46
+3.3V P0.16/EINT0/MAT0.2/CAP0.2
47
53
54
55
1
P0.21/PW M5/AD1.6/CAP1.3
R1 P0.22/AD1.7/CAP0.0/MAT0.0
2
1K 58
P0.23
9
P0.25/AD0.4/AOUT
10
P0.26/AD0.5
11
P0.27/AD0.0/CAP0.1/MAT0.1
13
P0.28/AD0.1/CAP0.2/MAT0.2
C5 P0.29/AD0.2/CAP0.3/MAT0.3
14
100pF 15
17
+3.3V P0.31
A
16
P1.16/TRACEPKT0
12
P1.17/TRACEPKT1 B
49 8
VBAT P1.18/TRACEPKT2
4
P1.19/TRACEPKT3 C
63 48
7 44
V3A P1.21/PIPESTAT0 D
51 40
V3 P1.22/PIPESTAT1
43 36
V3 P1.23/PIPESTAT2
23 32
V3 P1.24/TRACECLK
28
P1.25/EXTIN0
59 24
VSSA P1.26/RTCK
50 64
VSS P1.27/TDO
42 60
VSS P1.28/TDI
25 56
18
VSS P1.29/TCK
52
LAMP
VSS P1.30/TMS
6 20
VSS P1.31/TRST
LPC2138 LED-YELLOW

Output

{
T0PR = 60-1;// Pclk = 60MHz, ft = 1MHz , Div =

60x10^6/1x10^6 = 60
T0MR0 = 1000-1; // 2000us = 500 HZ

T0MR1 = 500-1; // 1000us = 1KHz
T0MR2 = 250-1; // 500us = 2KHz
T0MR3 = 125-1; // 250us = 4KHz
T0MCR |= (0x01 << 0)|

(0x01 << 3)|
(0x01 << 6)|
(0x01 << 9) ;
//Set bit0 High which is to : Interrupt on
MR0,MR1,MR2,MR3
}
{
long int temp;
temp = T0IR ;

{
T0MR0 = T0MR0 + 1000;
sq500hz = ~(sq500hz);
writepin(25,sq500hz);
}

{
T0MR1 = T0MR1 + 500;
sq1kz = ~(sq1kz);
writepin(26,sq1kz);
}

{
T0MR2 = T0MR2 + 250;
sq2kz = ~(sq2kz);
writepin(27,sq2kz);
}

{
T0MR3 = T0MR3 + 125;
sq4kz = ~(sq4kz);
writepin(28,sq4kz);
}
T0IR = temp;
VICVectAddr = 0x00;
Department
}
of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu
External Interrupts

External Interrupt Mode register
(EXTMODE)

External Interrupt Polarity register
(EXTPOLAR)

External Interrupt Flag register
(EXTINT)

Pin function Select register 1
(PINSEL1)

Problem-3
delay.
• Task2 Read a switch @ EINT0 and Turn a
Load @ P1.25 when count exceeds 10.

Schematic
C1
1
33pF U1
X1 62
19
61 21
22
P0.2/SCL0/CAP0.0
2
3 26
5 27
33pF 29
57 30
31
P0.7/SSEL0/PW M2/EINT2
33
34
1
22pF 35
P0.10/RTS1/CAP1.0/AD1.2
37
+3.3V
38
C4 P0.12/DSR1/MAT1.0/AD1.3
39
P0.13/DTR1/MAT1.1/AD1.4
2
41
45
22pF
+3.3V P0.16/EINT0/MAT0.2/CAP0.2
46 R2
47 10k
53
54
55
1
P0.21/PWM5/AD1.6/CAP1.3
R1 P0.22/AD1.7/CAP0.0/MAT0.0
2
1K 58
P0.23
9
P0.25/AD0.4/AOUT
10
P0.26/AD0.5
11
P0.27/AD0.0/CAP0.1/MAT0.1
13
P0.28/AD0.1/CAP0.2/MAT0.2
C5 P0.29/AD0.2/CAP0.3/MAT0.3
14
100pF 15
17
+3.3V P0.31
LOAD
16
P1.16/TRACEPKT0
12
P1.17/TRACEPKT1
49 8
VBAT P1.18/TRACEPKT2 LED-YELLOW
4
P1.19/TRACEPKT3
63 48
7 44
V3A P1.21/PIPESTAT0
51 40
V3 P1.22/PIPESTAT1
43 36
V3 P1.23/PIPESTAT2
23 32
V3 P1.24/TRACECLK
28
P1.25/EXTIN0
59 24
VSSA P1.26/RTCK
50 64
VSS P1.27/TDO
42 60
VSS P1.28/TDI
25 56
18
VSS P1.29/TCK
52
LAMP
VSS P1.30/TMS
6 20
VSS P1.31/TRST
LPC2138 LED-YELLOW

{
VICVectCntl0 = (0x01 << 5) | 14 ;

// (bit5 = 1) -> to enable Vectored IRQ slot
VICVectAddr0 = (unsigned) INT0ISR;
VICIntEnable = 0x01 << 14;
//0x10; //Enable EINT0 interrupt
// INT0 SPECIFIC
PINSEL1 |= 0x01 ;// P0.16 = INT0
EXTMODE |= 0x01 ;// INT0 = Edge Sensitive
EXTPOLAR |= 0x00 ; // INT0 = Falling Edge

void INT0ISR(void) __irq
{
long int temp;
temp = EXTINT ;
if (temp & 0x01) // EINT0

{
if (mycount > 10)
writepin(25,1); // Load ON
else
{
mycount ++;
writepin(25,0); // Load OFF
}
}
EXTINT = temp; // clear interrupt

VICVectAddr = 0x00;
}
#include<lpc214x.h>
#include "GPIO.h"
#include "timer.h"
#include "UART.h"
#include "extinterrupt.h"
int main(void)
{
initInterrupt();
while(1)
{
writepin(31,1);
delay();
writepin(31,0);
delay();
}
}
Problem-4
delay.
• Task2 Read a switch @ EINT0 and Turn a
Load @ P1.25 when count exceeds 10.
• Task3 Read a switch @ EINT1 and Toggle a
Load @ P1.26

C1
Schematic
1
33pF U1
X1 62
19
61 21
22
P0.2/SCL0/CAP0.0
2
3 26
5 27
33pF 29
57 30
31
33
34
1
22pF 35
P0.10/RTS1/CAP1.0/AD1.2
37
+3.3V
38 +3.3V
C4 P0.12/DSR1/MAT1.0/AD1.3
39
P0.13/DTR1/MAT1.1/AD1.4
2
41
45
22pF
+3.3V P0.16/EINT0/MAT0.2/CAP0.2
46 R2 R3
47 10k
P0.17/CAP1.2/SCK1/MAT1.2 10k
53
54
55
1
P0.21/PWM5/AD1.6/CAP1.3
R1 P0.22/AD1.7/CAP0.0/MAT0.0
2
1K 58
P0.23
9
P0.25/AD0.4/AOUT
10
P0.26/AD0.5
11
P0.27/AD0.0/CAP0.1/MAT0.1
13
P0.28/AD0.1/CAP0.2/MAT0.2
C5 P0.29/AD0.2/CAP0.3/MAT0.3
14
100pF 15
17
+3.3V P0.31
LOAD
16
P1.16/TRACEPKT0
12
P1.17/TRACEPKT1
49 8
4
63
P1.19/TRACEPKT3
48 D1
7 44
V3A P1.21/PIPESTAT0
51 40
V3 P1.22/PIPESTAT1
43 36 LED-YELLOW
V3 P1.23/PIPESTAT2
23 32
V3 P1.24/TRACECLK
28
P1.25/EXTIN0
59 24
VSSA P1.26/RTCK
50 64
VSS P1.27/TDO
42 60
VSS P1.28/TDI
25 56
18
VSS P1.29/TCK
52 LAMP
VSS P1.30/TMS
6 20
VSS P1.31/TRST
LPC2138 LED-YELLOW

{
// EINT1 15 # EINT0 14 #
VICVectCntl0 = (0x01 << 5) | 14 ; //0x20 (i.e bit5 = 1) -> to enable
Vectored IRQ slot
VICVectAddr0 = (unsigned) INT0ISR; //Pointer Interrupt Function (ISR)
VICIntEnable |= 0x01 << 14; //0x10; //Enable EINT0 int
VICVectCntl1 = (0x01 << 5) | 15 ; //0x20 (i.e bit5 = 1) -> to enable

Vectored IRQ slot
VICVectAddr1 = (unsigned) INT1ISR; //Pointer Interrupt Function (ISR)
VICIntEnable |= 0x01 << 15; //0x10; //Enable EINT1 int
// EINT SPECIFIC
PINSEL1 |= 0x01 << 0 ; // P0.16 = INT0, 1st Altrnate Function(01)
EXTMODE |= 0x01 << 0 ; // INT0 = Edge Sensitive, Bit0
EXTPOLAR |= 0x00 << 0 ; // INT0 = Falling Edge, Bit0
PINSEL0 |= 0x03 << 6 ; // P0.3, 3rd Alternate Function(11)

EXTMODE |= 0x01 << 1 ; // INT1 = Edge Sensitive, Bit1
EXTPOLAR |= 0x00 << 1 ; // INT1 = Falling Edge, Bit0
}
{
long int temp;
temp = EXTINT ;

{
if (mycount > 5)
writepin(25,1); // Load ON
else
{
mycount ++;
writepin(25,0); // Load OFF
}
}

VICVectAddr = 0x00;
}
{
long int temp;
temp = EXTINT ;

{
LED = ~LED;
writepin(26,LED); // Load OFF

VICVectAddr = 0x00;

#include<lpc214x.h>
#include "GPIO.h"
#include "timer.h"
#include "UART.h"
#include "extinterrupt1.h"
int main(void)
{
initInterrupt();
while(1)
{
writepin(31,1);
delay();
writepin(31,0);
delay();
}
}

UART Interrupt

Problem-5
• Design a LPC2148 based system to perform the
following tasks.
• Task1 Blink an LED at P1.31 using software delay.
• Task2 Receive commands from PC at 9600 Baud and
control 2 Loads for the following commands.
• A Load1 ON
• B Load 1 Off
• C Load 2 ON
• D Load 2 OFF

Pin Function Select Register 0
(PINSEL0)
01
01

UART0 Line Control Register
(U0LCR)

UART0 Line Status Register (U0LSR)

UART0 Line Status Register (U0LSR)

UART0 Interrupt Enable Register(U0IER)

UART0 Interrupt Identification
Register (U0IIR)

Schematic
C6
1uF
C1 1 3 U2
1
U1 C1+ C1-
33pF
X1 62
19 11
T1IN T1OUT
14
RXD
61 21 12 13 VT52, VT100, ANSI
C2 XTAL2 P0.1/RxD0/PWM3/EINT0 R1OUT R1IN
22 10 7
P0.2/SCL0/CAP0.0 T2IN T2OUT TXD
2
3 26 9 8
RTXC1 P0.3/SDA0/MAT0..0/EINT1 R2OUT R2IN
5 27
RTXC2 P0.4/SCK0/CAP0.1/AD0.6 RTS
33pF 29 2
P0.5/MISO0/MAT0.1/AD0.7 VS+ Xmodem, Ymodem, Zmodem
57 30 6
C3 RST P0.6/MOSI0/CAP0.2/AD1.0 VS- CTS
31
P0.7/SSEL0/PW M2/EINT2
33
C2+ C2- C9
34 C8
1
P0.9/RxD1/PWM6/EINT3 1uF
22pF 35 1uF
P0.10/RTS1/CAP1.0/AD1.2 C7
X2 37 4 5 MAX232
P0.11/CTS1/CAP1.1/SCL1
38
C4 P0.12/DSR1/MAT1.0/AD1.3
39
P0.13/DTR1/MAT1.1/AD1.4
2
41 1uF
45
22pF
46
+3.3V P0.16/EINT0/MAT0.2/CAP0.2
47
53
54
55
1 D1
P0.21/PW M5/AD1.6/CAP1.3
R1 P0.22/AD1.7/CAP0.0/MAT0.0
2
1K 58
P0.23
LED-YELLOW
9
P0.25/AD0.4/AOUT
10
P0.26/AD0.5
11
P0.27/AD0.0/CAP0.1/MAT0.1
13
P0.28/AD0.1/CAP0.2/MAT0.2
C5 P0.29/AD0.2/CAP0.3/MAT0.3
14
100pF 15
17
+3.3V P0.31
D2
16
P1.16/TRACEPKT0
12
P1.17/TRACEPKT1
49 8
4
P1.19/TRACEPKT3
63 48
7 44
V3A P1.21/PIPESTAT0
51 40
V3 P1.22/PIPESTAT1
43 36
V3 P1.23/PIPESTAT2
23 32
V3 P1.24/TRACECLK
28
P1.25/EXTIN0
59 24
VSSA P1.26/RTCK
50 64
VSS P1.27/TDO
42 60
VSS P1.28/TDI
25 56
18
VSS P1.29/TCK
52
LAMP
VSS P1.30/TMS
6 20
VSS P1.31/TRST
LPC2138 LED-YELLOW

#include<lpc214x.h>
#include "GPIO.h"
#include "timer.h"
#include "UART.h"
#include "UARTInterrupt.h"
int main(void)
{
initInterrupt();
initserial();
while(1)
{
writepin(31,1);
delay();
writepin(31,0);
delay();
}
}

void initserial(void)
{
PINSEL0 =0X05; // P0.0 = TxD , P0.1 = RxD
U0LCR = 0X83; // DLAB(7) = 1 , 8 Bit UART (1,0) = 1,
U0DLL = 0X87;
// = 60 x 10^6 / (9600 x 16) = 391 = 0x0187
U0DLM = 0X01; // 9600 Baud
U0LCR = 0X03; // DLAB(7) = 0,8 Bit UART (1,0) = 1,
}

{
/
// UART0 06 #
VICVectCntl0 = (0x01 << 5) | 6 ;

//0x20 (i.e bit5 = 1) -> to enable Vectored IRQ slot
VICVectAddr0 = (unsigned) UART0ISR;
VICIntEnable = 0x01 << 6;
//0x10; //Enable UART0 interrupt
// UART SPECIFIC
U0IER = 0X01 ;
// Enables the Receive Data Available interrupt
}

void UART0ISR(void) __irq
{
long int temp;
temp = U0IIR ; // Reading Clears this Register
if (temp & 0x04) // Receive Data Available (RDA) = "0100"

{
mydata = U0RBR ;
if (mydata == 'A')
writepin(25,1);
else if (mydata == 'B')
writepin(25,0);
else if (mydata == 'C')
writepin(26,1);
else if (mydata == 'D')
writepin(26,0);
else
{
writepin(25,0);
writepin(26,0);
}
}
VICVectAddr = 0x00;
}

End of Session
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LPC2148 - Interrupts

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

• Interrupt ReQuest (IRQ) can be thought of as a special request to

• ISR : This function or ‘small piece of code’ is technically called an

• So when an IRQ arrives to the CPU , it stops executing the code

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

FIQ Vectored IRQ

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Types of Interrupts in LPC2148

• Fast Interrupt Request i.e FIQ : which has highest priority

• Vectored Interrupt Request i.e Vectored IRQ : which has

• Non-Vectored IRQ : which has the lowest priority.

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

• Non-Vectored means that CPU doesn’t know the address

• For Non – Vectored interrupts , CPU needs to be supplied

• For the Vectored interrupts , the System internally

• The CPU needs to be supplied with the address of the

• In LPC2148 this is facilitated by a register called

• The user must assign the address of the default ISR to

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

• Non-Vectored IRQ(NVIRQ) has the same IRQ

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

• This register is used for reading the current

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

• If a bit location is read as 1 then it means that

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

• These are the Vector Control registers.

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

• Disabling it will generate the address of the ‘common/default

• In simple words if the slot is enabled it points to ‘specific and

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

• This register stores the address of the

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

• Step-2 : Identify the interrupt source number

• Step-3 : Assign the address of the related ISR

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

VICVectCntl0 = (1<<5) | 4 ; //5th bit must 1 to

VICVectAddr0 = (unsigned) myISR;

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

__irq void myISR(void)

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

VICVectCntl0 = (0x01 << 5) | 4 ;

VICIntEnable = 0x01 << 4; //Enable

Department of EIE / PEC Dr.R.Sundaramurthy.,M.E.,Ph.D., sundar@pec.edu

T0PR = 60-1; Reset Timer after Match