DATASHEET

CA3162 FN1080
A/D Converters for 3-Digit Display Rev.3.00
Apr 2002

Features Description
• Dual Slope A/D Conversion The CA3162E and CA3162AE are I2L monolithic A/D
• Multiplexed BCD Display converters that provide a 3 digit multiplexed BCD output.
They are used with the CA3161E BCD-to-Seven-Segment
• Ultra Stable Internal Band Gap Voltage Reference Decoder/Driver and a minimum of external parts to imple-
• Capable of Reading 99mV Below Ground with Single ment a complete 3-digit display. The CA3162AE is identical
Supply to the CA3162E except for an extended operating tempera-
• Differential Input ture range.

• Internal Timing - No External Clock Required The CA3161E is described in the Display Drivers section of
this data book.
• Choice of Low Speed (4Hz) or High Speed (96Hz)
Conversion Rate
Ordering Information
• “Hold” Inhibits Conversion but Maintains Delay
• Overrange Indication TEMP. PKG.
- “EEE” for Reading Greater than +999mV, “-” for PART NUMBER RANGE (oC) PACKAGE NO.
Reading More Negative than -99mV When Used With CA3162E 0 to 70 16 Ld PDIP E16.3
CA3161E

Pinout
CA3162 (PDIP)
TOP VIEW

21 1 16 23
BCD BCD
OUTPUTS 15 22 OUTPUTS
20 2

NSD 3 14 V+
DIGIT
SELECT MSD 4 13 GAIN ADJ
OUTPUTS INTEGRATING
LSD 5 12
CAP
HOLD/
6 11 HIGH INPUT
BYPASS
GND 7 10 LOW INPUT

ZERO ADJ 8 9 ZERO ADJ

Functional Block Diagram

FN1080 Rev.3.00 Page 1 of 8

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CA3162

V+ V+
BCD OUTPUTS
ZERO
INTEGRATING
ADJ
CAP 21 20 22 23 V+

8 9 12 1 2 15 16 14

3
CONTROL LOGIC DIGIT DIGIT SELECT
COUNTERS AND MULTIPLEX 4
DRIVE OUTPUTS †
5
4 = MSD

THRESHOLD 5 = LSD
HIGH INPUT 11 V/I DET.
3 = NSD

LOW INPUT 10 CONVERTER 2048 96

REFERENCE HOLD/
BAND GAP CONVERSION
CURRENT OSC BYPASS 6
REFERENCE CONTROL
GENERATOR GATES

13 7 GND
† MSD = MOST SIGNIFICANT DIGIT
NSD = NEXT SIGNIFICANT DIGIT
LSD = LEAST SIGNIFICANT DIGIT

GAIN
ADJ

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CA3162

Absolute Maximum Ratings Thermal Information

DC Supply Voltage (Between Pins 7 and 14) . . . . . . . . . . . . . . .+7V Thermal Resistance (Typical, Note 1) JA (oC/W)
Input Voltage (Pin 10 or 11 to Ground) . . . . . . . . . . . . . . . . . . 15V PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Operating Conditions Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Temperature Range Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CA3162E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 75oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details..

Electrical Specifications TA = 25oC, V+ = 5V, Zero Pot Centered, Gain Pot = 2.4k, Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Operating Supply Voltage Range, V+ 4.5 5 5.5 V

Supply Current, I+ 100k to V+ on Pins 3, 4, 5 - - 17 mA

Input Impedance, ZI - 100 - M

Input Bias Current, IIB Pins 10 and 11 - -80 - nA

Unadjusted Zero Offset V11-V10 = 0V, Read Decoded Output -12 - +12 mV

Unadjusted Gain V11-V10 = 900mV, Read Decoded Output 846 - 954 mV

Linearity Notes 1 and 2 -1 - +1 Count

Conversion Rate
Slow Mode Pin 6 = Open or GND - 4 - Hz

Fast Mode Pin 6 = 5V - 96 - Hz

Conversion Control Voltage (Hold Mode) 0.8 1.2 1.6 V

at Pin 6

Common Mode Input Voltage Range, VICR Notes 3, 4 -0.2 - +0.2 V

BCD Sink Current at Pins 1, 2, 15, 16 VBCD  0.5V, at Logic Zero State 0.4 1.6 - mA

Digit Select Sink Current at Pins 3, 4, 5 VDIGIT Select = 4V at Logic Zero State 1.6 2.5 - mA

Zero Temperature Coefficient VI = 0V, Zero Pot Centered - 10 - V/oV

Gain Temperature Coefficient VI = 900mV, Gain Pot = 2.4k - 0.005 - %/oC

NOTES:
1. Apply 0V across V11 to V10 . Adjust zero potentiometer to give 000mV reading. Apply 900mV to input and adjust gain potentiometer to give
900mV reading.
2. Linearity is measured as a difference from a straight line drawn through zero and positive full scale. Limits do not include 0.5 count bit digitizing
error.
3. For applications where low input pin 10 is not operated at pin 7 potential, a return path of not more than 100k resistance must be provided for
input bias currents.
4. The common mode input voltage above ground cannot exceed +0.2V if the full input signal range of 999mV is required at pin 11. That is, pin 11
may not operate higher than 1.2V positive with respect to ground or 0.2V negative with respect to ground. If the maximum input signal is less
than 999mV, the common mode input voltage may be raised accordingly.

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CA3162

Timing Diagram current source of opposite polarity is connected. The number of

clock counts that elapse before the charge is restored to its orig-
inal value is a direct measure of the signal induced current. The
12 200mV restoration is sensed by the comparator, which in turn latches
the counter. The count is then multiplexed to the BCD outputs.
5 (LSD)
500mV
The timing for the CA3162E is supplied by a 786Hz ring
PIN NUMBER

oscillator, and the input at pin 6 determines the sampling rate. A

4 (MSD)
500mV
5V input provides a high speed sampling rate (96Hz), and
grounding or floating pin 6 provides a low speed (4Hz) sampling
rate. When pin 6 is fixed at +1.2V (by placing a 12K resistor
3 (NSD) between pin 6 and the +5V supply) a “hold” feature is available.
500mV
While the CA3162E is in the hold mode, sampling continues at
4Hz but the display data are latched to the last reading prior to
2ms/DIV. the application of the 1.2V. Removal of the 1.2V restores contin-
uous display changes. Note, however, that the sampling rate
FIGURE 1. HIGH SPEED MODE
remains at 4Hz.
Figure 1 shows the timing of sampling and digit select pulses
Detailed Description for the high speed mode. Note that the basic A/D conversion
The Functional Block Diagram of the CA3162E shows the V/I process requires approximately 5ms in both modes.
converter and reference current generator, which is the heart of The “EEE” or “---” displays indicate that the range of the system
the system. The V/I converter converts the input voltage applied has been exceeded in the positive or negative direction, respec-
between pins 10 and 11 to a current that charges the integrating tively. Negative voltages to -99mV are displayed with the minus
capacitor on pin 12 for a predetermined time interval. At the end sign in the MSD. The BCD code is 1010 for a negative overrange
of the charging interval, the V/I converter is disconnected from (---) and 1011 for a positive overrange (EEE).
the integrating capacitor, and a band gap reference constant

NOTE 2 +5V
NOTE 1

0.27F 0.1
F COMMON POWER
ANODE LED 2N2907, 2N3906
DISPLAYS OR EQUIV.
NORMAL 8 9 12 14 16 MSD NSD LSD
LOW SPEED MODE:
V6 = GROUND OR
OPEN a a a
5 f b f b f b
HOLD: g g g
V6 = 1.2V 6 3
e c e c e c
4 d d d
HIGH SPEED MODE:
V6 = 5V
DIGIT 13
CA3162E DRIVERS CA3161E
12
BCD
OUTPUTS 11
11 16 6 10
HIGH
15 2 9
INPUTS
1 1 15
LOW
10 2 7 14
R1 R2 R3
13 7 8 3 150 150 150
10 CA3162E CA3162E
GAIN k PINS PINS
ADJ 3, 4, 5 1, 2, 15, 16

NOTES: 1k 75

1. The capacitor used here must be a low dielectric absorption type
such as a polyester or polystyrene type. DIGIT BCD SEGMENT
2. This capacitor should be placed as close as possible to the power DRIVER DRIVERS
and ground Pins of the CA3161E.

FIGURE 2. BASIC DIGITAL READOUT SYSTEM USING THE CA3162E AND THE CA3161E

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CA3162

CA3162E Liquid Crystal Display (LCD) Application
Figure 3 shows the CA3162E in a typical LCD application.
LCDs may be used in favor of LED displays in applications
requiring lower power dissipation, such as battery-operated
equipment, or when visibility in high-ambient-light conditions is
desired.
Multiplexing of LCD digits is not practical, since LCDs must be
driven by an AC signal and the average voltage across each
segment is zero. Three CD4056B liquid-crystal decoder/drivers
are therefore used. Each CD4056B contains an input latch so
that the BCD data for each digit may be latched into the
decoder using the inverted digit-select outputs of the CA3162E
as strobes.
The capacitors on the outputs of inverters G3 and G4 filter out
the decode spikes on the MSD and NSD signals. The capaci-
tors and pull-up resistors connected to the MSD, NSD and LSD
outputs are there to shorten the digit drive signal thereby pro-
viding proper timing for the CD4056B latches.
Inverters G1 and G2 are used as an astable multivibrator to
provide the AC drive to the LCD backplane. Inverters G3, G4
and G5 are the digit-select inverters and require pull-up resis-
tors to interface the open-collector outputs of the CA3162E to
CMOS logic. The BCD outputs of the CA3162E may be con-
nected directly to the corresponding CD4056B inputs (using
pull-up resistors). In this arrangement, the CD4056B decodes
the negative sign (-) as an “L” and the positive overload indica-
tor (E) as an “H”.
The circuit as shown in Figure 3 using G7, G8 and G9 will
decode the negative sign (-) as a negative sign (-), and the
positive overload indicator (E) as “H”.

+5V
0.047F
1 16
G3
0.047F 6
4 TO MSD
+5V CD4056B OF LCD
2
3
5 7 8
6x
10k
0.27F
ZERO +5V
MSD 0.047
8 14 12 4 F
50k NSD 16
3 G4 1
LSD 0.047F 0.047 6
9 5
23 F
16 4 TO NSD
CA3162E 22 CD4056B OF LCD
15 2
“HOLD” 21
1 3
20
VIN+ 11 2 5 7 8
VIN- 10 13 7 4x
100k
GAIN +5V
10k G5
1 16
+5V 6
4
CD4056B TO LSD
G7 G9 2 OF LCD

G1 - G6: CD4049UB 3
HEX INVERTER 5 7
G7, G8, G9: CD4023B 8
TRIPLE 3 INPUT NAND GATE
TO LCD
G8 BACKPLANE

15k

100k 0.63F

FIGURE 3. TYPICAL LCD APPLICATION

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CA3162

CA3162E Common-Cathode, LED Display Application The additional logic shown within the dotted area of Figure 4
restores the negative sign (-), allowing the display of negative
Figure 4 shows the CA3162E connected to a CD4511B
numbers as low as -99mV. Negative overrange is indicated by
decode/driver to operate a common-cathode LED display.
a negative sign (-) in the MSD position. The rest of the display
Unlike the CA3161E, the CD4511B remains blank for all BCD
is blanked. During a positive overrange, only segment b of the
codes greater than nine. After 999mV the display blanks rather
MSD is displayed. One inverter from the CD4049B is used to
than displaying EEE, as with the CA3161E. When displaying
operate the decimal points. By connecting the inverter input to
negative voltage, the first digit remains blank, instead of (-),
either the MSD or NSD line either DP1 or DP2 will be dis-
and during a negative or positive overrange the display blanks.
played.

V+
DP1 100k 22k

1/
DP2 3
1/ CD4049UB CD4049UB
6

CD4012B

1/
3
CD4049UB

1/ CD4049UB
6

V+
1 B V+ 16
CD4511B 1.8k
HP5082-7433
2 C f 15
1.2k OR EQUIVALENT
3 LT g 14
100k 100k 1.8k
4 BL a 13
1.2k
V+
5 LE/STROBE b 12
1.8k
100k 100k 6 D c 11 12 11 10 9 8 7
1.8k
7 A d 10 f a g b c3
1.8k
8 GND e 9
V+
DP1 DP2
1 B D 16 c1 e d c2 c dP
100 100 100 CA3162E
1 2 3 4 5 6
k k k 2 A C 15

3 NSD V+ 14 V+

4 MSD GAIN 13
0.27F
10k
5 LSD INT 12
GAIN
6 HOLD HIGH 11

7 GND LOW 10
6 BUFFERS
8 ZERO ZERO 9 (1 CD4050B)
V+
INPUT

50k

FIGURE 4. TYPICAL COMMON-CATHODE LED APPLICATION

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CA3162

Die Characteristics
DIE DIMENSIONS: PASSIVATION:
101 mils x 124 mils x 20 mils 1 mil Type: 3% PSG
Thickness: 13kÅ 2.5kÅ
METALLIZATION:
Type: Al
Thickness: 17.5kÅ 2.5kÅ

Metallization Mask Layout

CA3162
LOW INPUT

ZERO ADJ

ZERO ADJ

GND
HIGH INPUT

INTEGRATING CAP HOLD/BYPASS

LSD

MSD

GAIN ADJ
21

20
V+

22

23

NSD

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CA3162

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FN1080 Rev.3.00 Page 8 of 8

Apr 2002