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LMS ACTIVITY
Submitted by:
Atienza, Marvin James A.
Submitted to:
Engr. Aileen F. Villamonte, ECE
A. With X, Y, and Z as the inputs and F as the output, generate the Truth Table.
X Y Z F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
B. By means of Truth Table, find the following Boolean function of a 3-input Majority
Gate
1. canonical SOP
F(x,y,z) = x’y’z’ + x’y’z + x’yz’ + xy’z’
2. canonical POS
F(x,y,z) = (x+y’+z’)(x’+y+z’)(x’+y’+z)(x’+y’+z’)
C. simplify the Boolean function using
1. K-Map
Canonical SOP
F(x,y,z) = x’y’z’ + x’y’z + x’yz’ + xy’z’
x 0 1
yz
00 1 1
01 1
11
10 1
x 0 1
yz
00
01 0
11 0 0
10 0 0
F(x,y,z) = (y’+z’)(x’+y’)(x’+z’)
2. Tabulation (Quine-McClusky) method
Canonical SOP
Dec xyz Group Dec xyz
0 000 0 0 000 ✔
1 001 1 1 001 ✔
2 010
2 010 ✔
4 100
4 100 ✔
xyz
0,1 00_ *
0,2 0_0 *
0,4 _00 *
3 011 2 3 011 ✔
5 101 5 101 ✔
6 110 6 110 ✔
7 111 3 7 111 ✔
xyz
3,7 _11 *
5,7 1_1 *
6,7 11_ *
F(x,y,z) = (x’+y’)(x’+z’)(y’+z’)
D. Generate and compile the VHDL code of your design using quartus II and give the
following:
SOP
1. VHDL code
library ieee;
use ieee.std_logic_1164.all;
entity LMS is
port( x: IN std_logic;
y: IN std_logic;
z: IN std_logic;
F : OUT std_logic);
end LMS;
end simplify;
2. Summary Report
3. RTL view
POS
1. VHDL code
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LMS_POS is
port( x: IN std_logic;
y: IN std_logic;
z: IN std_logic;
F : OUT std_logic);
end LMS_POS;
begin
F <= not ((y or z) and (x or z) and (x or y));
end LMS;
2. Summary Report
3. RTL view