DLD - EEE 241 Chapter 03 PDF

Tuesday, 16 February, 2016
Digital Logic Design

EEE241
Gate Level Minimization
Tuesday, 16 February, 2016 1
Gate-Level Minimization
 Outline
 The Map method
 Multi-variable maps
 Product-of-Sums simplification
 Don’t-Care conditions
 NAND and NOR implementation
 X-OR function

Gate-Level Minimization
 Find an optimal gate-level implementation of

the given Boolean functions
 Difficult task to execute manually
 Different techniques are used including

 Boolean algebra
 Map methods
The Karnaugh Map (K-map) Method
 Recall: a given function has

 A unique representation using a truth table
 A unique representation as a sum of minterms
 Several equivalent representations as algebraic
expressions
 Boolean minimization is a bit awkward

 Solution: Karnaugh map method minimization

K-map Method
 An alternate approach to representing a Boolean

function
 Graphical representation of a Boolean function
 Minimization is performed by visual identification

of logic blocks
 The larger the blocks, the fewer literals in a term
 Representation of minterms of a function
K-map Method
 All rows in a truth table represented with a square

 Each square represents a minterm
 Number of 1’s  Number of minterms
 Example: A 2-variable map

K-map Method
 1’s and 0’s represent function in K-maps

 1 is put where F = 1 in the truth table
 0’s are typically not shown
(a) F1 = xy, (b) F2 = x+y
Rules for K-maps
 We can reduce functions by circling 1’s in the K-

map
 Each circle represents minterm reduction
 Following circling, we can deduce minimized and-or
form
 Rules
 Every cell containing a 1 must be included at least
once
 Enclose the largest possible “power of 2 rectangle”
 The 1’s must be enclosed in the smallest possible
number of rectangles

3-Variable Karnaugh Maps
 Two variables on one side, one on the other

 Gray codes are used to represent blocks
 Only 1 bit changes in adjacent blocks
K-map Blocks
 Identifying blocks in Karnaugh maps

 Neighboring minterms can be combined
 Example
F = x’y’z’ + x’y’z = x’y’
 Resulting expression has 2 literals

K-map Blocks
 Example:
F ( x, y, z )   (2,3,4,5)  xyz   xyz  xyz   xyz
 Corresponding K-map
 2 blocks of size 2  F  x y  x y 
K-map Blocks
 Exercise
 What is the K-map minimized form of the following
expression?
F ( x, y, z )   (3,4,6,7)
 Blocks continue across borders of K-maps (wrap around)

K-map Blocks
 We have learnt how to combine 2 minterms

 Can we combine more than 2?
 Yes
F  xyz   xyz  xyz   xyz  ( x  x). y.( z  z )  y
 Any block of “power of 2 size” can be reduced

 Larger the block, simpler the expression
K-map Blocks
 Can blocks overlap? Yes

 Example:
F ( A, B, C )   (1,2,3,5,7)
 The largest power-2 block may have an overlap

Converting Blocks into Expressions
 Rule of thumb
 Write down the variables that do not change
F(A,B,C) = C+A’B
Convert expression as sum of minterm
 Boolean expression
 F = A’C + A’B + AB’C + BC
 F (A,B,C) = Sum (1,2,3,5, 7)
 F = C + A’B

 Rule of thumb
F(A,B,C) = C+A’B
 Rule of thumb
F(A,B,C) = C+A’B

 Rule of thumb
F(A,B,C) = C+A’B
4-Variable K-maps
 Same principle can be extended to 4-variable

expressions
 Note again the gray code pattern in blocks

4-Variable K-maps
 1 square  One minterm  A term with 4 literals
 2 adjacent squares  A term with 3 literals
 4 adjacent squares  A term with 2 literals
 8 adjacent squares  A term with 1 literal
4-Variable K-maps
 Pair
 Group of 2 adjacent minterms
 Eliminates 1 variable
 Quad
 Eliminates 2 variables
 Octet
 Eliminates 3 variables
 Redundant
 All elements are covered by other groups

4-Variable K-maps
 Example:
F  AC   AB  BCD
4-Variable K-maps
 Example:
F ( w, x, y, z )   (0,1,2,4,5,6,8,9,12,13,14)
F ( w, x, y, z )  y  wz   xz 

Terminology
 Implicant
 Any product term in the SOP form
 A block of 1’s in a K-map
 Prime implicant
 Product term that cannot be further reduced
 Block of 1’s that cannot be further increased
 Essential prime implicant

 Prime implicant that covers a 1 (or minterm) that is not
covered by any other implicant
Essential Prime Implicants
 Example:
F ( A, B, C , D )   (0,2,3,5,7,8,9,10,11,13,15)
 Essential prime implicants: BD and B’D’

 Prime implicants: CD, B’C, AD, AB’

Incompletely Specified Functions
 Sometimes a function is not completely specified

 For instance, when BCD numbers are handled
 A BCD number is represented by 4 bits with 6 values undefined

 What to do with these unused (undefined) values?
 Answer: Use them as don’t care conditions
F ( A, B, C , D)  AD  BCD  BCD  ABC D
Don’t Cares
 Output of function irrelevant for some inputs
 Input might never occur
 Input is invalid
 Function is incompletely specified

 Multiple completely specified functions can implement it
 Karnaugh map is marked with ‘x’ for don’t cares

 Output can be set to 1 or 0 (hence “don’t care”)
 Choose most convenient output
 Maximize block size
 Representation
 d(w,x,y,z) = Σ(0,2,5)`

Don’t Cares (Example)

F ( w, x, y, z )   (1,3,7,11,15) and d ( w, x, y, z )   (0,2,5)
5-Variable K-map
 Becomes a little difficult to understand

5-Variable K-map
 Example:
F ( A, B, C , D, E )   (0,2,4,6,9,13,21,23,25,29,31)
F  ABE   BDE  ACE
Product of Sums Minimization
 How to generate a product of

sums from a Karnaugh map?
 Use duality of Boolean algebra
(DeMorgan’s Law)
 Look for 0s in map instead of 1s

 Generate blocks of 0’s
 Gives inverse of function
 Use duality to generate product of
sums
 Example F   (0,1,2,5,8,9,10)
 ( A  B).(C   D).( B  D)

NAND and NOR Implementation
 Any logic circuit can be built using a single

“universal” gate
 The universal gates are
 NAND
 NOR
 All the gates including NOT, AND, OR can be

implemented using only NAND or only NOR
gates
NAND Implementation
 NOT, AND and OR implementation using NAND

NAND Implementation
 Minimized expressions are AND-OR combinations

 Two ways to represent NAND
 AND-invert
 Invert-OR
 Key observation: two “bubbles” eliminate each other
 How to generate a sum of minterms using NAND?

 Use AND-invert for minterms
 Use invert-OR (OR with inverted inputs) for sum
NAND Implementation
 Sum of minterms
 Replace AND with AND-invert and OR with inverted inputs
 Replace AND-invert and invert-OR with NAND

NAND Implementation
 Exercise: Minimize the following function using NAND gates

F = Σ(1,2,3,4,5,7)
 Karnaugh map
 Implementation
Multilevel NAND Circuits
 Rules
 Convert all AND gates to NAND with AND-invert symbols
 Convert all OR gates to NAND with invert-OR symbols
 Check all bubbles in diagram. For every bubble that is not compensated
by another bubble, insert inverter

Multilevel NAND Circuits
 Example: F=(AB’+A’B)(C+D’)
 With NAND gates
NOR Implementation
 NOT, AND and OR implementation using NOR
 Two representations of NOR

 OR-invert and invert-AND (AND with inverted inputs)

NOR Implementation
 Same rules as for NAND implementation

 Example: F = (AB’+A’B)(C+D’)
 With NOR
Conversion Example
F(A,B,C,D) = Σ(0,2,7,8,10,13)
d(A,B,C,D) = Σ(6,14,15)
 Solution (SOP form): F = BC + B’D’ + ABD
 Homework: Draw NAND and NOR circuits for above functions

Exclusive-OR Function
 Denoted by the symbol 

F  x  y  xy  xy
 Function is 1 when both inputs are different
 Exclusive-NOR is a complement of X-OR

F  ( x  y )  xy  xy
 Function is 1 when inputs are equal
 Properties of X-OR function

1. x  0  x
2. x  1  x
3. x  x  0
4. x  x  1
5 . x  y   x   y  ( x  y )
6. x  y  y  x
7. ( x  y )  z  x  ( y  z)

 Construction of XOR other gates
Odd Function
A  B  C  ( AB  AB ).C   ( AB  AB)C
 ABC   ABC   ABC  ABC
  (1,2,4,7)
 3-variable XOR function is 1 if

 Only 1 variable is 1
 All 3 variables are 1
 Also known as odd function
 Number of 1s can be
determined by looking at the
output of the function

Even Function
 Complement of the odd function

 Equal to 1 when
 Number of 1s is even
Odd and Even Functions
 3-input odd function (2 XOR gates)
 3-input even function (1 XOR and 1 XNOR gate)

Parity Generation and Checking
 XOR functions are useful in error detection

 Parity bit is used to detect transmission errors
 Error is detected if checked parity does not correspond
to the parity transmitted
 Parity generator
 Circuit that generates parity at the transmitter
 Parity checker
 Circuit that checks parity at the receiver

 Parity generator
 Parity checker
Problems with Manual Methods
 Manual methods
 Boolean algebra
 K-maps
 Good for understanding
 Difficult to handle large circuits
 Involving several inputs (variables)
 Can we get help from computer?

 Yes
 How?

Hardware Description Language (HDL)
 Computer based language to describe the hardware of

digital systems in textual form
 Ordinary programming language like C
 Describes a relationship between inputs and outputs of a
circuit
 Language readable for both human and computers
 Can be used to describe

 Truth tables
 Boolean expressions
 Complex abstraction of digital systems
Verilog (an HDL)
 Comprises of around 100 keywords

 module, endmodule, input, output, and, xor, not
 Comments are represented with // or blocks of /*
and */
 Case-sensitive language
 module
 Fundamental descriptive unit in Verilog
 Represented by a block of module and endmodule

Verilog
 Example: Write a Verilog code for the following circuit
Verilog
 Verilog code
module Simple_Circuit (A, B, C, D, E);

output D, E;
input A, B, C;
wire w1;
and G1 (w1, A, B);

not G2 (E, C);
or G3 (D, w1, E);
endmodule

Verilog
 Gate delays
 Propagation delay for transition from input to output
 Specified in terms of (dimensionless) time units,
specified with #
 Example
and #(30) G1 (w1, A, B);
Verilog
 Verilog code
module Simple_Circuit (A, B, C, D, E);

output D, E;
input A, B, C;
wire w1;
and #(30) G1 (w1, A, B);

not #(10) G2 (E, C);
or #(20) G3 (D, w1, E);
endmodule

Verilog
 How to test a module?

 Need to provide a sample output.
 How?
 HDL equivalent to test is known as testbench
 Testbench
 Usually has no input and output
 Generally name of a testbench starts with a prefix t_
 Inputs are defined with keyword reg
 Outputs are defined with keyword wire
Verilog
 Testbench code
module t_Simple_Circuit_prop_delay;
wire D, E;
reg A, B, C;
Simple_Circuit_prop_delay M1(A,B,C,D,E);
initial
begin
A = 1’b0; B = 1’b0; C = 1’b0;
#100 A=1’b1; B=1’b1; C=1’b1;
end
initial #200 $finish;
endmodule

Verilog
 Output waveform
Verilog
 assign keyword is used to express Boolean

expressions
 Operators
 &  AND
 |  OR
 ~  NOT
 Example
assign D = (A & B) | ~C;

Verilog
 Verilog code
module Circuit_Boolean (E, F, A, B, C, D);

output E, F;
input A, B, C, D;
assign E = A | (B & C) | (~B & D);

assign F = (~B & C) | (B & ~C & ~D);
endmodule
Verilog
 User defined primitives (UDP)

 Sometimes you need to define your own
logic/functions
 Implementation of an XOR function using other gates
 Defining a function through a truth table
 primitive…endprimitive
 table…endtable

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Tuesday, 16 February, 2016

Digital Logic Design

Gate Level Minimization

Tuesday, 16 February, 2016 1

Tuesday, 16 February, 2016 2

 Find an optimal gate-level implementation of

 Difficult task to execute manually

 Different techniques are used including

Tuesday, 16 February, 2016 3

The Karnaugh Map (K-map) Method

 Recall: a given function has

 Boolean minimization is a bit awkward

Tuesday, 16 February, 2016 4

 An alternate approach to representing a Boolean

 Minimization is performed by visual identification

 Representation of minterms of a function

Tuesday, 16 February, 2016 5

 All rows in a truth table represented with a square

Tuesday, 16 February, 2016 6

 1’s and 0’s represent function in K-maps

Tuesday, 16 February, 2016 7

Rules for K-maps

 We can reduce functions by circling 1’s in the K-

Tuesday, 16 February, 2016 8

3-Variable Karnaugh Maps

 Two variables on one side, one on the other

Tuesday, 16 February, 2016 9

 Identifying blocks in Karnaugh maps

Tuesday, 16 February, 2016 10

Tuesday, 16 February, 2016 11

 Blocks continue across borders of K-maps (wrap around)

Tuesday, 16 February, 2016 12

 We have learnt how to combine 2 minterms

 Any block of “power of 2 size” can be reduced

Tuesday, 16 February, 2016 13

 Can blocks overlap? Yes

 The largest power-2 block may have an overlap

Tuesday, 16 February, 2016 14

Converting Blocks into Expressions

Tuesday, 16 February, 2016 15

Convert expression as sum of minterm

 F (A,B,C) = Sum (1,2,3,5, 7)

Tuesday, 16 February, 2016 16

Converting Blocks into Expressions

Tuesday, 16 February, 2016 17

Converting Blocks into Expressions

Tuesday, 16 February, 2016 18

Converting Blocks into Expressions

Tuesday, 16 February, 2016 19

 Same principle can be extended to 4-variable

 Note again the gray code pattern in blocks

Tuesday, 16 February, 2016 20

 1 square  One minterm  A term with 4 literals

 2 adjacent squares  A term with 3 literals

 4 adjacent squares  A term with 2 literals

 8 adjacent squares  A term with 1 literal

Tuesday, 16 February, 2016 21

Tuesday, 16 February, 2016 22

Tuesday, 16 February, 2016 23

Tuesday, 16 February, 2016 24

 Essential prime implicant

Tuesday, 16 February, 2016 25

Essential Prime Implicants