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design

Edited by Bill Travis and Anne Watson Swager


ideas
MOSFET switch provides efficient ac/dc conversion
Spehro Pephany, Trexon Inc, Toronto, ON, Canada
ccasionally, you have access to a

O transformer for powering a


dc circuit, but its output volt-
age is much higher than that required for
Figure 1

18V AC D2
D1
1N4004
the dc voltage. The full-wave-rectified SECONDARY WO4M
T1
and filtered output of an ac input voltage + C1 R1
Q1
VX, is VDC41.414VX22VF, where VF is 22 mF/35V 4.7k
STD12NE06
the forward drop in the rectifier (ap-
D5
proximately 0.7V). For example, if you D3 1N4004
require 12V dc to power a small cooling 1N5242B

fan drawing 100 mA and the ac voltage is D4 +


R2 1N5242B
18V, a full-wave rectifier and filter results 10k A 12V FAN
in a 24V-dc output. Although you can Q2
2N4401 2
regulate the voltage down to 12V dc by R3 C2 +
using a simple three-terminal regulator 10k 1000 mF/16V
(such a mA7812), the result is wasted
power of approximately 1.3W. This waste OPTIONAL SHUTDOWN CIRCUIT
means that you must provide for heat re-
moval, somewhat defeating the purpose R4 D6
4.7k 1N4148
of including the cooling fan. If you use a
typical 1002100-mm, 12V-dc fan rated
at 0.45A, the typical heat loss is approxi- Using a MOSFET circuit, you can efficiently convert the too-high voltage of a leftover transformer to
mately 2.5W, increasing to 5W at full a lower dc level.
load. In many applications, this level of
loss is unacceptable, so you’d have to use and diode to effectively draw current from 24 to 0V, Q2 again turns off at ap-
an extra transformer secondary, a dc/dc from the transformer when the voltage proximately 12.7V, allowing Q1 to turn
converter, or a switching regulator. The is close to the desired level of 12V dc. on and provide another pulse of current
circuit in Figure 1 uses a MOSFET switch The full-wave bridge, D2, rectifies the to charge C2. C2 provides power for the
18V-ac signal. The diode, D1, and C1 pro- load between the pulses, which occur at
vide a gate bias voltage of approximately 240 Hz with a 60-Hz input. Thus, power
MOSFET switch provides efficient
24V dc. This voltage drives the gate of Q1 drain from the transformer occurs in
ac/dc conversion..........................................149
through R1, shunted by D4, which main- short pulses, much in the manner of a
Passive circuit monitors AES data............150 tains the gate voltage at a maximum of typical bridge-rectifier/output-filter ar-
mC multiplexes DIP switches 12V relative to the source, even during rangement but at double the frequency.
to I/O port......................................................150 transient conditions. As the bridge-recti- If you want to turn the fan off with a log-
fier output increases from 0V to the peak ic signal, you can add R4 and D6. When
Switched-capacitor IC controls
of approximately 24V each half-cycle, the you apply a logic-high signal to the input,
feedback loop ..............................................154
bias voltage holds the MOSFET on until Q2 conducts, turning the MOSFET off.
Simple circuit disconnects load ................158 the input voltage reaches the breakdown (DI #2484)
Follow the debouncing flip-flops..............160 voltage of D3 (12V) plus the VBE(ON) of Q2,
or approximately 12.7V. At that point, Q2
Inductorless converter provides turns on, turning Q1 off. The output fil-
high efficiency ..............................................162 ter capacitor, C2, charges through D5. As To Vote For This Design,
the rectifier output voltage decreases Circle No. 311

www.ednmag.com February 17, 2000 | edn 149


design
ideas
Passive circuit monitors AES data
Wayne Sward, Bountiful, UT
RED
he circuit in Figure 1 efficiently

T monitors common digital-


audio signals. One format for
such signals is the Audio Engineering So-
Figure 1

270 1 nF
1.2k
2 mA

1N914
ciety (AES) 44.1- or 48-kHz standard.
Typically, the data consists of a serial data
1N914
stream with a data rate of approximate- 1 nF
2
ly 1 Mbps. A lower frequency pulse in-
3
terspersed in the data stream synchro-
nizes data frames every 16 to 20 data bits. THREE-PIN 1 1 nF 15k
AUDIO BNC
The amplitude of the data and sync puls- CONNECTORS 2 TO SCOPE
es is 3 to 12V p-p, with one cycle of an 1k 2.2k 100 pF TRIGGER
3 10 nF
ac wave representing each bit. The signals
are on a two-wire cable that you can iso- 1

late from ground by using signal trans- BNC


TO SCOPE
formers or capacitors. Several other data- CHANNEL A
transmission standards use a similar data
format. An oscilloscope does not reliably A passive circuit gives a good indication of data activity on digital-audio lines.
trigger on such a waveform; thus, trou-
bleshooting and signal tracing such sys- voltage level, so you can easily observe closely inspect the wave shape. The 15-
tems is difficult. The circuit in Figure 1 low or high voltage levels. Intermittent kV resistor and 100-pF capacitor form a
is passive and small and uses no power levels, crosstalk, or interference on the simple but effective filter to detect the
supplies. You can keep it in a toolbox, signal causes the LED to flicker. The LED sync bit in the data stream. You feed this
ready for instant use. circuit is differential and measures the sync bit to the external sync input of the
The two diodes and associated capac- voltage levels between the two signal oscilloscope, resulting in a stable display
itors form a voltage doubler to provide a lines. Common-mode ground noise or of the data frame. The coupling capaci-
bias voltage of approximately 22 to hum do not affect the LED’s display. The tors avoid creating a ground loop be-
210V. The 2-mA LED connects between voltage doubler is an efficient way to in- tween the signal lines and the grounded,
one of the signal lines and this bias volt- crease the sensitivity of the LED without shielded input of the oscilloscope. You
age. Whenever the signal-line voltage ex- an additional power supply. can readily monitor data amplitude,
ceeds approximately 1.5V, the LED turns The two coupling capacitors sample waveshape, and activity of individual bits
on. At a data rate of nearly 1 MHz, the the high-frequency data waveform but with the oscilloscope. (DI #2482)
LED appears to continuously glow when reject any low-frequency common-mode
good data is present. The LED’s intensi- noise or hum. You can display the data To Vote For This Design,
ty is proportional to the peak-to-peak waveform on an oscilloscope to more Circle No. 312

mC multiplexes DIP switches to I/O port


Gregory Willson, ACS Defense Inc, Warrenton, VA
t times, a mC must read a large assign a switch to each one. You can use plexing 32 DIP switches using only 12 I/O

A number of DIP switches, such as for


system identification, bus-address
setup, manual configuration, or other
multiplexer ICs to share one I/O port
with multiple switches, but they compli-
cate the circuit, dissipate additional pow-
pins and eight pullup resistors. Four 8-bit
DIP switches connect in parallel to a sin-
gle 8-bit I/O port. A pullup resistor on
purposes. However, the available number er, and consume precious board real es- each port pin defaults the input to a high
of I/O lines is sometimes not enough to tate. Figure 1 shows a method of multi- state; a switch closure pulls the input to

150 edn | February 17, 2000 www.ednmag.com


design
ideas

Figure 1

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

SWITCH_INPUT (7 TO 0)

5V
R1 TO R8
4.7k
2 0
RA0 21
RB0
3
RA1 22 1
RB1
4
RA2 23 2
5 RB2
RA3
IC1 24 3
RB3
5V PIC16C63 25 4
RB4
20 26 5
VDD RB5
C1 8 27 6
VSS RB6
10 nF
28 7
RB7

Using only 12 I/O pins, a mC can read 32 DIP


switches. LISTING 1—MULTIPLEXING DIP SWITCHES TO SINGLE I/O PORT

a low state. The key to multiplexing the


DIP switches is to ground each set of
eight switches in turn using output pins
from a second I/O port.
To deselect a set of switches, the con-
trolling-port pin acts as an input, ren-
dering it a high-impedance port. In this
way, 12 I/O pins can read 32 switches,
and 16 I/O pins can read 64 switches. Se-
lect the values of the pullup resistors to
limit the total current into the control-
ling-port pin to less than the maximum
sink current. Some mCs, such as the Mi-
crochip PIC16C6x family, provide the
ability to enable weak internal pullups
on I/O port pins. By using this feature,
you can eliminate the eight external pull-
up resistors. The code fragment in List-
ing 1 illustrates reading the four 8-bit
DIP switches and storing the results, us-
ing a Microchip PIC16C63 mC. You can
download Listing 1 from EDN’s Web
site, www.ednmag.com. Click on “Search
Databases” and then enter the Software
Design Center to download the file for
Design Idea #2483. (DI #2483)

To Vote For This Design,


Circle No. 313

152 edn | February 17, 2000 www.ednmag.com


design
ideas
Switched-capacitor IC controls feedback loop
Dave Sargent, IBM Research, San Jose, CA
ou can implement a simple control point of zero error and is approximately cover the higher speed range, you need an

Y loop with a constant setpoint over a


wide range of control by using a
switched-capacitor filter. The circuit con-
2V p-p. The rectified output serves as the
dc setpoint voltage for the control loop.
If the motor speed increases, the voltage
additional divide by 10 to stay within the
frequency range of the filter. An example
is given for 6- and 60-Hz rotational
trols motor speed over 1 to 200 Hz or 60 decreases, and if the motor slows down, speeds. Conventional op-amp circuits
to 12,000 rpm. In Figure 1, a National the voltage increases. As simple as the buffer and rectify the output of the filter.
LMF40CIWM four-pole lowpass filter is method is, it can drive a motor-control The application uses one of many full-
the heart of the design. This filter has a chip and provide good speed regulation. wave op-amp-rectifier circuits that follow
cutoff frequency defined by the clock di- You can use the method to control oth- a buffer with a gain of 2. After rectifica-
vided by 50. Consider this filter as a dif- er servo loops that provide a feedback fre- tion, the 75-kV resistors and 0.1-mF ca-
ference amplifier that compares the dif- quency within the range of the filter. The pacitor provide some filtering and time-
ference between two frequencies. The big advantage of this scheme is that the constant conditioning. You set the gain of
relationship between the clock divided by setpoint remains constant with a range of op amp 1 so its output dc voltage is 2.5V
50 and the 500-count encoder divided by speed settings. Another advantage is that at the operating point. Op amp 2 offsets
2 is such that when the clock rate is 1000 the clock provides direct speed calibra- this voltage and moves the operating
times the revolutions per second of the tion thanks to the 1000-to-1 relationship point to 0V when no speed error is pres-
motor, the signal frequency from the en- between the clock and the rotational ent. The offset-adjust trimmer allows for
coder is at approximately the midpoint of speed of the motor. Figure 2 shows some minor variations and calibrates the actu-
the filter response. This midpoint is the circuit details for enhanced operation. To al rotational speed to the clock signal. Op

5V
LMF40CIWM
FOUR-POLE LOWPASS FILTER
12
Figure 1 DIVIDE BY 2 V+

500-COUNT PER REVOLUTION CONTROL OPERATING POINT


(2.5 kHz) 14 FILIN 8 AT 2V P-P
MOTOR-SHAFT ENCODER 7474 FILOUT
5 kHz AT 600 RPM (10-RPS) ROTATION SPEED (RECTIFIED SIGNAL IS THE
5 DC CONTROL VOLTAGE.)
LVSHF
3
1 CLKR
CLKIN
10
AGND

V1
7 CLOCK450 2 FCO

10002RPS CLOCK 15V


(FOR 10 RPS, USE 100-kHz CLOCK.)

5V P-P

SLOWER

2V P-P OPERATING POINT (2.5 kHz)

FASTER

FILTER CUTOFF AT CLOCK/50


(2 kHz WITH A 100-kHz CLOCK)

A lowpass filter is the heart of a wide-range control loop.

154 edn | February 17, 2000 www.ednmag.com


design
ideas
amp 3 provides gain for the proportion- speed settings. Buffer op amp 5 sums the tional circuits control acceleration rate,
al signal. proportional and integral signals at its braking rate, and direction. The speed ac-
You can use a fixed resistor in place of input. A clamp diode limits the positive curacy for the system is a nominal
the 200-kV trimmer. Op amp 4 is an in- drive voltage and prevents any negative 0.002% throughout the range. The speed
tegrator circuit that provides the classical excursions from driving the loop to a clock comes from a DDS chip, and all the
integral control for the loop. The inte- latch-up condition. In an application, the above functions are under control of a
grator makes up for errors in the follow- clamping limits the output to 4.3A, be- PC or front-panel switch settings. (DI
ing control circuits and motor charac- cause the motor-control circuit has a #2486)
teristics throughout the control range. drive characteristic of 1A per volt. When
The integrator control-point output the motor stops, the FET stop switch To Vote For This Design,
voltage therefore changes at different clamps the control signal to zero. Addi- Circle No. 314

Figure 2
NOTES: FROM CONTROL CIRCUITS
ALL OP AMPS USE 612V POWER SUPPLIES. CONTROL, DIRECTION, AND DRIVE CIRCUITS
ALL OP AMPS ARE MC34084. ACCELERATION, BRAKING

OPTICAL START/STOP START/STOP


INDEX OUT MOTOR
ENCODER MOTOR CONTROL
DRIVE
SIGNAL 2
ENCODER CLOCK 500 PER REVOLUTION 6 2
3
+
OP AMP 5 CLAMP
BUFFER AND OP-AMP DIODE
FULL-WAVE 4.3V
DIVIDE BY 10 RANGE DIVIDE BY 2 RECTIFIER CIRCUITS
30.1
INTEGRATOR
MC14017 74HC74 MC34084 3
+ 6
2
31 SELECT RESISTORS FOR 2
OP AMP 4
75k A NOMINAL 2.5V-DC
5V OPERATING POINT INTEGRAL CONTROL
12
14
V+ 0.22 mF 0.1 mF
FILIN 8 3
5 FILOUT + 10k 10k
LVSHF LOWPASS FILTER 6
1 2 FROM START/STOP
CLKIN 3 2 OP AMP 1
CONTROL CIRCUITS
10 CLKR
AGND V2 75k
0.1 mF 10k
7 LMF 40CIWM STOP
503 CLOCK SWITCH
25V
3.3k 2k
2k 10k
SPEED CLOCK SET SPEED TRIM
CLOCK AT 10003RPS FOR 31 RANGE FOR NOMINAL 0V OUT
CLOCK AT 10003RPS FOR 30.1 RANGE 2 AT OPERATING SPEED
2 6
2k 2k
SPEED 3 +
5V TRIM
OP AMP 2

APPROXIMATELY 1.25V 200k


5.1k
EXAMPLES:
LOOP-GAIN SET
31 RANGE
CLOCK=60 kHz.
MOTOR SPEED=60 RPS (3600 RPM). 5V P-P
LMF40 CUTOFF F0=1200 Hz. SLOWER 2
2 6
ENCODER DIVIDED BY 20=1500 Hz.
LMF40 OUTPUT=2V P-P NOMINAL. OPERATING POINT 3 +
2V P-P PROPORTIONAL
(1500 Hz)
30.1 RANGE CONTROL
CLOCK=60 kHz.
FASTER OP AMP 3
MOTOR SPEED=6 RPS (360 RPM).
LMF40 CUTOFF F0=1200 Hz.
ENCODER DIVIDED BY 2=1500 Hz.
LMF40 OUTPUT=2V P-P NOMINAL.
FILTER CUTOFF AT CLOCK/50
(1200 Hz)

A wide-range control circuit uses two ranges for maximum resolution.

156 edn | February 17, 2000 www.ednmag.com


design
ideas
Simple circuit disconnects load
Larry Suppan, Maxim Integrated Products, Sunnyvale, CA
lacing a load-disconnect circuit

P on the output of a boot-


strapped step-up regulator al-
lows the regulator to start with load cur-
Figure 1

VIN
rents much higher than would otherwise
+ C1
be possible (Figure 1). During shut- L1 100 mF Q1
down, the disconnect completely isolates 4.7 mH NDS 8434
9
the battery from the load. The circuit CLK/SEL
LXP, LXN
14, 11

boosts a single NiMH-cell output to 3.3V D1 VOUT


MBR0520L C4
R3 1M 3.3V
and delivers output currents to 600 mA. 100k POUT
13 23220 mF
Step-up regulators are excellent for 16 IC1
R5 C5
portable applications because they ex- ON MAX1703 10 0.22 mF
OUT 4 1M
hibit high efficiency, low supply current 6 C2
(120 mA operating, 20 mA in shutdown), AIN
0.22 mF
and ample current once started. Many,
POK 8 Q2
however, cannot start with maximum 3
POKIN 2N3904
R4 7
load from low supply voltages, such as 100k
AO
1
those from single-cell batteries. This REF FB
2

problem arises because most low-voltage R1


PGND GND R2 166k
CMOS boost regulators derive power 10, 12 5 100k
C3
from their own outputs, which equal VIN 0.22 mF
minus a diode drop at start-up. Low val-
ues of input voltage don’t allow the NOTE:
switching transistor to become fully en- HEAVY LINES INDICATE HIGH-CURRENT PATHS.
hanced at start-up, so the transistor pres-
ents a high impedance that limits the The addition of a couple of transistors enables a switching regulator to start with full load and low
peak inductor current. As a result, the cir- input voltages.
cuit cannot produce enough current to
simultaneously supply the load and To get around this problem and ensure corporate an undervoltage lockout
charge the output capacitor. reliable start-ups, most regulator ICs in- (UVLO). IC1, for example, is a synchro-

2 2
Figure 2
1.8 1.8

1.6 1.6
START-UP VOLTAGE (V)
START-UP VOLTAGE (V)

1.4 1.4

1.2 1.2
WITHOUT LOAD SWITCH WITHOUT LOAD SWITCH

1 1

0.8 0.8
WITH LOAD SWITCH WITH LOAD SWITCH

0.6 0.6
0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000
LOAD CURRENT (mA) (b) LOAD CURRENT (mA)
(a)

The load-disconnect switch in Figure 1 allows the regulator to start up with heavy loads and low input voltages (a). A slight modification of the circuit
in Figure 1 provides 5V-output operation (b).

158 edn | February 17, 2000 www.ednmag.com


design
ideas
nous boost converter whose boot- fore driving Q1. Q1 disconnects the load, vice. Connecting the FB terminal (Pin 2)
strapped operation cannot start until its allowing VOUT to rise to a level (above to ground and removing R1 and R2 pro-
output voltage exceeds the internal UVLO) that ensures full enhancement of duces a 5V regulated output, whose per-
UVLO threshold of 2.3V. You can over- Q1 when it turns on. As a result, the cir- formance is similar to that of the 3.3V
come this start-up limitation with an ex- cuit can start under full load with input version (Figure 2b). (DI #2487)
ternal power MOSFET, Q1, operating as voltages as low as 0.8V (Figure 2a). Be-
a load-disconnect switch, and by using cause the circuit takes the regulator feed-
the power-OK (POK) comparator built back before this switch, the MOSFET you
into many low-voltage switching regula- choose for a given application depends
tors. R3 and R4 set the POK threshold at on the load current and minimum ac-
2.5V, allowing VIN to rise above the UVLO ceptable level of load regulation. The To Vote For This Design,
threshold. Q2 inverts the POK output be- MOSFET shown is a low-threshold de- Circle No. 315

Follow the debouncing flip-flops


Ray Scott and John Stanley, Airport Systems International, Overland Park, KS
uring a recent development ef- dance. The design in Figure 1 minimizes fore the Switch_Debounced output will

D fort, we could not find literature de- the use of flip-flops.


tailing how to debounce an spst mo-
change. A frequency of approximately 15
The circuitry monitors the state of the Hz (or a period of 66 msec) for the De-
mentary switch using only logic (no Switch input. Once the circuit detects a bounce_Clock input works well, even for
capacitors, Schmitt triggers, or other transition, a “qualifying” time of two De- low-cost,“noisy” switches. You can delete
components). Our application placed the bounce_Clock periods begins. If at any the reset logic if you are unconcerned
spst switches several feet from the logic time during the qualifying time the with the power-on state of the
board, and both noisy switches and line Switch input returns to its original state, Switch_Debounced output. Following
transients caused false triggers. Many indicating switch bounce or an electrical power-on, the output will be correct af-
methods simulate a debounce by check- transient, the circuitry returns to its start- ter two clock periods. (DI #2481)
ing the state of the switch on clock edges ing state and begins looking for another
and summing the checks over time, but transition. The Switch input must be
our application required no transitions completely stable for two positive tran- To Vote For This Design,
during the qualification time before ac- sitions of the Debounce_Clock input be- Circle No. 316
knowledgment of a key
press. Thus, the switches INPUT
can work effective- RESET
OR2
ly in noisy environ- F i g u r e 1
ments over reasonably NOT
OR2
long distances. Figure 1 il- NAND3
lustrates a means of de- A
bouncing a momentary DFF
NOT

switch for both the make INPUT PRN PRN


SWITCH Q
and the break operations. D
A
Q D
B OUTPUT
SWITCH_DEBOUNCED
Designers often use pro-
CLRN CLRN
grammable logic to de-
bounce momentary switch- NAND3 NOT
es used in keypads, in key- B
boards, or as configuration NOT
inputs. Flip-flops are usu-
INPUT
ally precious commodities DEBOUNCE_CLOCK
OUTPUT
SWITCH_DEBOUNCED
in programmable logic,
whereas logic gates are
available in greater abun- A debouncing circuit using programmable logic makes frugal use of flip-flops.
160 edn | February 17, 2000 www.ednmag.com
design
ideas
Inductorless converter provides high efficiency
Sam Nork, Linear Technology Corp, Milpitas, CA
wo common methods exist for gen- an input range of 2.4 to 6V,

T erating a regulated dc output voltage


that is lower than the input voltage.
The first approach is to use a low-
ONE-CELL
Li-ION

THREE-CELL
OR

NiMH
10 mF
4

2
VIN
IC1
VOUT

LTC1503-2

C11 C21
1

8
10 mF

1 mF
VOUT
2V/100 mA allowing the IC to take pow-
er from either a single Li-
ion cell or a three-cell
dropout (LDO) regulator. LDO regula- 1 mF NiMH battery. IC1 uses
3
C1+ C2+ 6
tors are small, easy to use, and in- 5
SHDN/SS GND
7 fractional-conversion tech-
Figure 1
expensive, but all the output niques to achieve efficien-
current must also flow through the input; Eschew bulky inductors, using switched-capacitor step-down cies typically more than
hence, they exhibit low efficiency. The conversion. 25% higher than that of an
second approach is to use an inductor- LDO regulator (Figure 2).
based switching regulator. Inductor- 100 Internal control circuitry ensures
based switchers can be efficient, that the device operates with the
LTC1503-2
but they tend to be more complex, Figure 2 optimal step-down ratio as the
80
costly, and area-consuming than their input voltage and load conditions
LDO-regulator counterparts. A third op- vary. You need only four small ce-
tion retains the simplicity and size of an EFFICIENCY (%) 60
ramic capacitors to make a com-
LDO regulator but enjoys the high effi- "IDEAL" plete step-down supply. Quies-
ciency usually reserved for inductor- LOW-DROPOUT
REGULATOR
cent current of 25 mA typical and
based circuits. The circuit in Figure 1 uses 40 the small MSOP-8 package make
switched-capacitor techniques to achieve VOUT=2V the circuit ideal for handheld de-
IOUT=100 mA
high-efficiency step-down conversion vices. (DI #2485)
20
without an inductor. 2 3 4 5 6
VIN
The circuit produces a regulated 2V
output with as much as 100 mA of load- Switched-capacitor conversion yields higher efficiency To Vote For This Design,
current capability. IC1, an LTC1503-2, has than LDO regulators. Circle No. 317

Circle 6 or visit www.ednmag.com/infoaccess.asp Circle 7 or visit www.ednmag.com/infoaccess.asp


162 edn | February 17, 2000 www.ednmag.com

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