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E.G.S. PILLAY ENGINEERING COLLEGE (AUTONOMOUS), NAGAPATTINAM.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING


COURSE PLAN
I. VISION AND MISSION STATEMENTS

COLLEGE DEPARTMENT
COLLEGE MISSION DEPARTMENT MISSION
VISION VISION
Envisioned to 1. To provide world class education to the students To produce globally 1. M1: Establish the emerging
transform our and to bring out their inherent talents skilled, creative, ethical requirements and nurture the spirit of
institution 2. To establish state-of the-art facilities and resources professionals with social innovation and creativity for
into a Global required to achieve excellence in teaching - enthusiasm and academic individuals with international
Center of learning and supplementary process excellence with lifelong competency.
Academic 3. To recruit competent faculty and staff and to learning in Electronics 2. M2: Impart quality education with
Excellence provide opportunity to upgrade their knowledge and Communication value added engineering programs to
and skills engineering field. prepare technically sound, ethically
4. To have regular interaction with the industries in strong engineers with social awareness.
the area of R & D and offer consultancy training 3. M3:0020Promote centre of excellence
and testing services and inculcate the quest for continuous
5. To establish centers of excellence in the emerging advanced learning with productive
areas of research careers in industry and research.
6. To offer continuing education and non-formal
vocational education program that beneficial to the
society

II. GENERAL DETAILS

Subject Code : EC6009


Subject Name : Advanced Computer Architecture
Programme : B.E - ECE
Prepared By Course Coordinator : Mr. M. Nuthal Srinivasan
Reviewed By 1.Domain Coordinator :
2. HOD : Dr. B. Padmanaban
Approved By Programme Coordinator :
Effective Date : 27.06.2018
III. Programme Educational Objectives (PEOs):
1. Graduates successful technical or professional careers in the electronics and communication engineering and its relative disciplines.
2. Graduate will exhibit technical skills to meet the day to day challenges with social consciousness.
3. Graduate will possess lifelong learning ability and teamwork capability.
IV. Programme Outcomes (POs): Graduates will be able to
1. (Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering specialization for the solution
of complex Electronics and Communication Engineering problems.
2. Problem analysis: Identify, formulate, research literature, and analyze complex engineering problems using basics of mathematics, natural sciences,
and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and design system components or processes that meet the
specified needs with appropriate consideration for public health and safety and societal considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools, including prediction and
modeling to solve engineering problems.
6. The engineer and society: Apply reasoning to assess societal, health, safety, legal, and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions in societal and environmental contexts, and
demonstrate the knowledge and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively and write effective reports and design documentation, make effective presentations in both verbal and
written form.
11. Project management and finance: Demonstrate knowledge and understanding of the electronics and communication engineering and management
principles and apply these as a member and leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent and life-long learning in the broadest context
of technological change.
V. Programme Specific Outcomes (PSOs): Graduates will able to
PSO 1: Examine the emerging areas in the field of communication/networking and signal processing.
PSO 2: Apply the principles of semiconductor devices, Digital systems, Microprocessors in the field of consumer electronics, medical, defense and
spacecraft electronic industry
PSO 3: Design and analyze subsystems and /or modules as a team for a variety of comparisons and recent applications in Electronics and
Communications.
PSO 4: Adapt recent developments in the electronics and communication engineering areas along with state-of-the-art Software tools.
VI. PEO vs PO/PSO Correlation Matrix

Programme
PO PSO
Educational
Objectives 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4
I - Graduates successful technical or professional
careers in the electronics and communication                
engineering and its relative disciplines.
II - Graduate will exhibit technical skills to meet
the day to day challenges with social     
consciousness.
III - Graduate will possess lifelong learning ability
     
and teamwork capability.
IV - Graduate will Apply the knowledge of
Electronics and Communication Engineering to         
pursue higher education and research.
Analysis Phase
VII. Course Context and Overview
EC6009-Advanced Computer Architecture is an elective subject in 7th semester in B.E. ECE curriculum. In order to take this course, a student should
have a prerequisite knowledge of Fundamentals of computing and Computer Architecture. In computer engineering, computer architecture is the
conceptual design and fundamental operational structure of a computer system. Computer architecture is a blueprint and functional description of
requirements (especially speeds and interconnections) and design implementations for the various parts of a computer — focusing largely on the way by
which the central processing unit (CPU) performs internally and accesses addresses in memory.
Computer architecture may also be defined as the science and art of selecting and interconnecting hardware components to create computers that meet
functional, performance and cost goals.

Course designed by Anna University, Chennai (R2013)

1 Category Basic Engineering Humanities Professional Professional Employability


Sciences Sciences (ES) and Social Core (PC) Elective Enhancement
(B) Sciences (PE) Course (EEC)
(HSS)
x
2 Broad Electronics Communic Networking General
area ation

x
VIII. Course Outcomes (COs):
After successful completion of the course, students can able to

Competency Cognitive level


CO1 Illustrate the Fundamentals of computer design and its trend in all Understand
aspects
CO2 Explain the Advanced Computer Architecture concepts. (ILP – Understand
Concepts and challenges)
CO3 Contrast various commercial applications and reuse the process, Understand
component and program for various applications.
CO4 Compare the Symmetric and distributed shared memory Understand
architectures
CO5 Choose the commercial problems and specifies the memory and Apply
I/O requirements appropriate to its solution.
CO6 Review the importance of memory and I/O system. Understand

IX. COs Vs Pos/PSOs Matrix:

Course Program Outcomes (POs)


CO
Outcomes
level PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
(COs)
PO level K6/K5
K3 K4 K5 K5
/K4
CO 1 K2 2 1 - -
CO 2 K2 2 1 - -
CO 3 K2 2 1 - -
CO 4 K2 2 2 1 -
CO 5 K3 3 2 1 -
CO 6 K2 2 1 - -

Program Specific Outcomes (PSOs)


Course CO PSO1 PSO2 PSO3 PSO4
Outcomes level
(COs)
PSO level K3 K4 K3 K2
CO 1 K2 2 1 - -
CO 2 K2 2 1 - -
CO 3 K2 2 1 - -
CO 4 K2 2 1 - -
CO 5 K3 3 2 3 -
CO 6 K2 2 1 2 -
Competency addresses outcome: - 1 = Slightly; 2 = Moderately; 3 = Substantially
X. Sub Competencies- Learning Outcomes (LO)/Course Outcomes (CO):
POs-Levels
CO/LO Competency
PO1 – 2, PO2 – 1, PSO1 – 2,
CO 1 Illustrate the Fundamentals of computer design and its trend in all aspects.
PSO2 – 1
LO 1.1 Explain about the fundamentals of CPU and memory systems in systems. Understand
LO 1.2 Describe the different Trends in technology, power, energy and cost with real time statistics. Understand
LO 1.3 Explain the various performance parameters for evaluation of the system. Understand
PO1 – 2, PO2 – 1, PSO1 – 2,
CO 2 Explain the Advanced Computer Architecture concepts. (ILP – Concepts and challenges)
PSO2 – 1
LO2.1 Illustrate the pipelining and instruction level parallelism concepts in computer architecture. Understand
LO2.2 Distinguish the various predictions and scheduling methods in ILP Understand
LO 2.3 Discuss the multithreading and speculation techniques in ILP Understand
Contrast various commercial applications and reuse the process, component and program for PO1 – 2, PO2 – 1, PSO1 – 2,
CO3
various applications PSO2 – 1
LO 3.1 Explain the vector architecture using data level parallelism. Understand
LO 3.2 Discuss the Graphical processing unit used in hardware acceleration. Understand
LO 3.3 Review the SIMD extensions with the help of data level parallelism Understand
LO 3.4 Differentiate between the data level parallelism and loop level parallelism Understand
PO2 – 3, PO2 – 2, PO3 – 1, PSO1
CO4 Compare the Symmetric and distributed shared memory architectures
– 2, PSO2 – 1
Contrast the importance of Symmetric and Distributed shared memory architecture in thread level
LO 4.1 Understand
parallelism
LO 4.2 Relate the different performance issues in thread level parallelism Understand
LO 4.3 Summarize the various memory consistency models in different architectures Understand
POs-Levels
CO/LO Competency
Collect the different case studies related to thread level parallelism like I7 processor, SMT and
LO 4.4 Apply
CMP processors.
Choose the commercial problems and specifies the memory and I/O requirements PO1 – 3, PO2 – 2,PO3 – 1, PSO1
CO5
appropriate to its solution – 3, PSO2 – 2, PSO3 – 3
LO 5.1 Link the cache performance issues with system stability. Apply
LO 5.2 Describe in detail about the Main memory and its performance for the given specification Understand
PO1 – 2, PO2 – 1, PSO1 – 2,
CO6 Review the importance of memory and I/O system
PSO2 – 1, PSO3-2
LO 6.1 Classify the different memory technology and storage devices in different system Understand
LO 6.2 Express the basic functions of RAID technology in memory systems Understand
LO 6.3 Estimate the I/O performance with various parameters. Understand

XI. Competency map with sub-competencies

LO3.1 LO4.1

LO2.1 LO3.2 LO4.2 LO6.1


LO1.1

LO1.2 LO2.2 LO3.3 LO4.3 LO5.1 LO6.2

LO1.3 LO2.3 LO3.4 LO4.4 LO5.2 LO6.3

CO1 CO2 CO3 CO4 CO5 CO6


XII. Test Items for Sub-competencies (Small Questions):

CO/LO Sub-competencies Cognitive


Levels
CO1 Illustrate the Fundamentals of computer design and its trend in all aspects. Understand
LO 1.1 Explain about the fundamentals of CPU and memory systems in systems. Understand
TI1 Draw the block diagram of computer. K1
TI2 Define Amdahl’s law. K1
TI3 Define MIPS and MIPS rate. K1
LO 1.2 Describe the different Trends in technology, power, energy and cost with real time statistics. Understand
TI1 What are the five trends in computer technology? K1
TI2 How to find the cost of an integrated circuit? K2
TI3 Write the Power and Energy equation for improving the computer Performance. K1
LO 1.3 Explain the various performance parameters for evaluation of the system. Understand
TI1 Write the expression for CPU Execution time for 5 Seconds. K2
TI2 Mention any Four performance measurement parameters which monitor the latency. K2
TI3 What do you infer from the term dependability? K2
CO2 Explain the Advanced Computer Architecture concepts. (ILP – Concepts and challenges) Apply
LO 2.1 Illustrate the pipelining and instruction level parallelism concepts in computer architecture. Apply
TI1 What are the various Hazards that affect the system performance?
TI2
TI3
LO 2.2 Distinguish the various predictions and scheduling methods in ILP Understand
TI1
TI2
TI3
LO 2.3 Discuss the multithreading and speculation techniques in ILP Apply
TI1
TI2
TI3
CO3 Contrast various commercial applications and reuse the process, component and program for various Understand
applications
LO 3.1 Explain the vector architecture using data level parallelism. Understand
TI1
TI2
TI3
CO/LO Sub-competencies Cognitive
Levels
LO 3.2 Discuss the Graphical processing unit used in hardware acceleration. Understand
TI1
TI2
TI3
LO 3.3 Review the SIMD extensions with the help of data level parallelism Understand
TI1
TI2
TI3
LO 3.4 Differentiate between the data level parallelism and loop level parallelism Understand
TI1
TI2
TI3
CO4 Compare the Symmetric and distributed shared memory architectures Understand
LO 4.1 Contrast the importance of Symmetric and Distributed shared memory architecture in thread level Understand
parallelism
TI1
TI2
TI3
LO 4.2 Relate the different performance issues in thread level parallelism Understand
TI1
TI2
TI3
LO 4.3 Summarize the various memory consistency models in different architectures Understand
TI1
TI2
TI3
LO 4.4 Collect the different case studies related to thread level parallelism like I7 processor, SMT and CMP Apply
processors.
TI1
TI2
TI3
CO5 Choose the commercial problems and specifies the memory and I/O requirements appropriate to its Apply
solution
LO 5.1 Link the cache performance issues with system stability. Apply
CO/LO Sub-competencies Cognitive
Levels
T11
TI2
TI3
LO 5.2 Describe in detail about the Main memory and its performance for the given specification Understand
TI1
TI2
TI3
CO 6 Review the importance of memory and I/O system Understand
LO 6.1 Classify the different memory technology and storage devices in different system Understand
TI1
TI2
TI3
LO 6.2 Express the basic functions of RAID technology in memory systems Understand
TI1
TI2
TI3
LO 6.3 Estimate the I/O performance with various parameters. Understand
TI1
TI2
TI3

XIII. Test Items for Sub-competencies (Big Questions):

CO/LO Sub-competencies Cognitive


Levels
CO1 Illustrate the Fundamentals of computer design and its trend in all aspects. Understand
LO 1.1 Explain about the fundamentals of CPU and memory systems in systems. Understand
TI1 Explain the Components of a computer system with the block diagram in detail. K2
TI2 Make a Review of Fundamentals of CPU. K2
LO 1.2 Describe the different Trends in technology, power, energy and cost with real time statistics. Understand
TI1 Explain various Technology trends in computer industry. K2
TI2 Explain the impact of Time, volume and commodification on Cost and Price. K2
LO 1.3 Explain the various performance parameters for evaluation of the system. Understand
TI1 State the CPU performance equation and discuss the factors that affect the performance of a computer. K2
TI2 Describe in detail about the Performance Evaluation. K2
CO/LO Sub-competencies Cognitive
Levels
CO2 Explain the Advanced Computer Architecture concepts. (ILP – Concepts and challenges) Apply
LO 2.1 Illustrate the pipelining and instruction level parallelism concepts in computer architecture. Apply
TI1
TI2
LO 2.2 Distinguish the various predictions and scheduling methods in ILP Understand
TI1
TI2
LO 2.3 Discuss the multithreading and speculation techniques in ILP Apply
TI1
TI2
CO3 Contrast various commercial applications and reuse the process, component and program for various Understand
applications
LO 3.1 Explain the vector architecture using data level parallelism. Understand
TI1
TI2
LO 3.2 Discuss the Graphical processing unit used in hardware acceleration. Understand
TI1
TI2
LO 3.3 Review the SIMD extensions with the help of data level parallelism Understand
TI1
TI2
LO 3.4 Differentiate between the data level parallelism and loop level parallelism Understand
TI1
TI2
CO4 Compare the Symmetric and distributed shared memory architectures Understand
LO 4.1 Contrast the importance of Symmetric and Distributed shared memory architecture in thread level Understand
parallelism
TI1
TI2
LO 4.2 Relate the different performance issues in thread level parallelism Understand
TI1
TI2
LO 4.3 Summarize the various memory consistency models in different architectures Understand
TI1
CO/LO Sub-competencies Cognitive
Levels
TI2
LO 4.4 Collect the different case studies related to thread level parallelism like I7 processor, SMT and CMP Apply
processors.
TI1
TI2
CO5 Choose the commercial problems and specifies the memory and I/O requirements appropriate to its Apply
solution
LO 5.1 Link the cache performance issues with system stability. Apply
T11
TI2
LO 5.2 Describe in detail about the Main memory and its performance for the given specification Understand
TI1
TI2
CO 6 Review the importance of memory and I/O system Understand
LO 6.1 Classify the different memory technology and storage devices in different system Understand
TI1
TI2
LO 6.2 Express the basic functions of RAID technology in memory systems Understand
TI1
TI2
LO 6.3 Estimate the I/O performance with various parameters. Understand
TI1
TI2

Design Phase

XIV. Delivery Technologies:


S. No. Delivery Technology
i. Classroom with LCD Projector
Concept Map
XV. Syllabus

UNIT I FUNDAMENTALS OF COMPUTER DESIGN 7 Hours


Review of Fundamentals of CPU, Memory and IO – Trends in technology, power, energy and cost, Dependability - Performance Evaluation

UNIT II INSTRUCTION LEVEL PARALLELISM 10 Hours


ILP concepts – Pipelining overview - Compiler Techniques for Exposing ILP – Dynamic Branch Prediction – Dynamic Scheduling – Multiple instruction Issue – Hardware
Based Speculation – Static scheduling - Multi-threading - Limitations of ILP – Case Studies.

UNIT III DATA-LEVEL PARALLELISM 9 Hours


Vector architecture – SIMD extensions – Graphics Processing units – Loop level parallelism.

UNIT IV THREAD LEVEL PARALLELISM 9 Hours


Symmetric and Distributed Shared Memory Architectures – Performance Issues –Synchronization – Models of Memory Consistency – Case studies: Intel i7 Processor, SMT
& CMP Processors
UNIT V MEMORY AND I/O 10 Hours
Cache Performance – Reducing Cache Miss Penalty and Miss Rate – Reducing Hit Time – Main Memory and Performance – Memory Technology. Types of Storage Devices
– Buses – RAID – Reliability, Availability and Dependability – I/O Performance Measures.
TOTAL: 45 HOURS

Text / Reference Books

Sl. No. Title of the Book Author(s) Publisher


REFERENCES
Computer architecture – A
Morgan Kaufmann / Elsevier
T1 quantitative John L. Hennessey and David A. Patterson
Publishers, 4th. Edition, 2007
approach
Parallel computing architecture : A Morgan Kaufmann /Elsevier Publishers,
R1 David E. Culler, Jaswinder Pal Singh
hardware/software approach 1999
R2 Scalable Parallel Computing Kai Hwang and Zhi. Wei Xu Tata McGraw Hill, New Delhi, 2003
REFERENCE WEBSITES
1 www.freebookcentre.net
2 www.cse.iitd.ernet.in
4 www.books.google
XVI. Detailed Course Plan

S.No. Topic(s) Hours Reference(s) Instructional Remarks


Methods
Unit – I FUNDAMENTALS OF COMPUTER DESIGN
CO1 - Illustrate the Fundamentals of computer design and its trend in all aspects.
Lecture with
LO 1.1 Explain about the fundamentals of CPU and memory systems in systems.
discussions
1. Review of Fundamentals of CPU, Memory and IO 2 T1- Ch.1.1,
T1 – Ch.1.2
Lecture with
LO 1.2 Describe the different Trends in technology, power, energy and cost with real time statistics.
discussions
2. Trends in technology, power, energy and cost 3 T1 – Ch.1.4, 1.5,
1.6
LO 1.3 Explain the various performance parameters for evaluation of the system. Lecture with
discussions
3. Dependability - Performance Evaluation 2 T1 – Ch.1.7, 1.8
Total Number of hours for Unit I: 7 (LH-07, TH-0, PH-0)
S.No. Topic(s) Hours Reference(s) Instructional Remarks
Methods
Unit – II INSTRUCTION LEVEL PARALLELISM
CO2 - Explain the Advanced Computer Architecture concepts. (ILP – Concepts and challenges)
Lecture with
LO 2.1 Illustrate the pipelining and instruction level parallelism concepts in computer architecture.
discussions
1. ILP concepts - Pipelining overview - Compiler Techniques for Exposing ILP 3 1- Ch.2.1,
T1 – Ch.2.2
Lecture with
LO 2.2 Distinguish the various predictions and scheduling methods in ILP
discussions
2. Dynamic Branch Prediction – Dynamic Scheduling – Multiple instruction Issue 3 T1 – Ch.2.3, 2.4,
2.5
LO 2.3 Discuss the multithreading and speculation techniques in ILP Lecture with
discussions
3. Hardware Based Speculation – Static scheduling - Multi-threading - Limitations of ILP – 4 T1 – Ch.2.6, 2.7,
Case Studies 2.8, 2.13
Total Number of hours for Unit I: 10 (LH-10, TH-0, PH-0)
S.No. Topic(s) Hours Reference(s) Instructional Remarks
Methods
S.No. Topic(s) Hours Reference(s) Instructional Remarks
Methods
Unit – III DATA-LEVEL PARALLELISM
CO1 - Illustrate the Fundamentals of computer design and its trend in all aspects.
Lecture with
LO 3.1 Explain the vector architecture using data level parallelism.
discussions
1. Vector architecture – Vector Super Computer, Vector Processing in stream mode 3 R1- Ch.4.1,
R1 – Ch.4.2
Lecture with
LO 3.2 Discuss the Graphical processing unit used in hardware acceleration.
discussions
2. Graphics Processing units 2 R1 – Ch.4.4
LO 3.3 Review the SIMD extensions with the help of data level parallelism Lecture with
discussions
3. SIMD extensions 2 R1 – Ch.5.1, 5.2
LO 3.4 Differentiate between the data level parallelism and loop level parallelism Lecture with
discussions
4. Loop level parallelism 2 R2 – Ch.10.5
Total Number of hours for Unit I: 9(LH-09, TH-0, PH-0)
S.No. Topic(s) Hours Reference(s) Instructional Remarks
Methods
Unit – III THREAD LEVEL PARALLELISM
CO1 - Illustrate the Fundamentals of computer design and its trend in all aspects.
Lecture with
LO 3.1 Explain the vector architecture using data level parallelism.
discussions
1. Vector architecture – Vector Super Computer, Vector Processing in stream mode 3 R1- Ch.4.1,
R1 – Ch.4.2
Lecture with
LO 3.2 Discuss the Graphical processing unit used in hardware acceleration.
discussions
2. Graphics Processing units 2 R1 – Ch.4.4
LO 3.3 Review the SIMD extensions with the help of data level parallelism Lecture with
discussions
3. SIMD extensions 2 R1 – Ch.5.1, 5.2
LO 3.4 Differentiate between the data level parallelism and loop level parallelism Lecture with
S.No. Topic(s) Hours Reference(s) Instructional Remarks
Methods
discussions
4. Loop level parallelism 2 R2 – Ch.10.5
Total Number of hours for UnitBLOOM’S
I: 9(LH-09,
LEVEL CYCLETH-0, PH-0)
TEST 1 CYCLE TEST 2 MODEL EXAM
Remember 20 20 20
XVII. a) Course Understand 80 80 80 Outcomes – Evaluation
Strategy
Apply - - -
Analyze - - -
Evaluate - - -
Create - - -

Internal Mini
Comp. Assignment
Tests Project
b) Tests and Examinations: (Marks) CO1 100%
CO2 80% 20%
CO3 80% 20%
CO4 80% 20%
CO5 100%
CO6 20% 80%

CYCLE TEST 1 100


CYCLE TEST 2 100
c) Internal Marks Assessment Pattern:
MODEL EXAM 100

TOTAL 300/3=100
Course co-coordinator HOD
(M. Nuthal Srinivasan) (Dr. B. Padmanaban)