B.E./B.Tech.

St. Xavier’s Catholic College of Engineering, Chunkankadai, Nagercoil – 629 003.

Second Semester
Information Technology
CS6201 - Digital Principles & System Design
First Internal Assessment Test, February 2017
Time: 1½ Hours Maximum: 50 marks
ANSWER ALL QUESTIONS
PART – A (09 x 02 = 18 marks)
1. State Duality principle?
Duality property states that every algebraic expression deducible from the postulates of
Boolean algebra remains valid if the operators and identity elements are interchanged. If the dual of
an algebraic expression is desired, we simply interchange OR and AND operators and replace 1’s by
0’s and 0’s by 1’s.
2. Draw the logic diagram for half adder.

3. Perform 9’s and 10’s compliment subtraction between 18 and 24?

Ans= -6
4. Draw the logic diagram for the Boolean expression using NAND gates.

5. Realize XOR gate using only 4 NAND gates?

6. Convert (1001010.1101001)2 to base 16 and (23 1.07)8 to base 10?

7. What are the limitations of Karnaugh map?
a. It is limited to six variable map.
b. The K-map simplification is manual technique and simplification process is heavily
depends on human abilities
8. State and prove Consensus theorem?
Consensus theorem states:
XY + X’Z + YZ = XY + X’Z
The YZ term is called the consensus term and is redundant. The consensus term is formed
from a PAIR OF TERMS in which a variable (X) and its complement (X’) are present; the
consensus term is formed by multiplying the two terms and leaving out the selected
variable and its complement.
The consensus of XY, X’Z is YZ .
Consensus Theorem Proof:
XY + X’Z + YZ = XY + X’Z + (X + X’)YZ
= XY + X’Z + XYZ + X’YZ
= (XY + XYZ) + (X’Z + X’YZ)
= XY (1 + Z) + X’Z (1 + Y)
= XY + X’Z
9. Design a half subtractor circuit.?

PART – B (02 x 16 = 32 marks)

10. (a) Simplify the following Boolean function using Quine-McClusky method
F = (A, B, C,D, E)= Σm (0,1,2,3,5,7,8,10,12,13,15). (16)
 F= + BD + +A

Or
10. (b) i) Prove that ( AB + C + D )(C ′ + D )(C ′ + D + E ) = ABC + D . (4)
ii) Simplify the given Boolean function in POS form using K-map and draw the
logic diagram using only NOR gates. F(A, B, C,D)= Σm (0,1, 4,7,8,10,12, 15)+
Σd (2, 6,11,14). (12)
11. a. (i) Explain the gray code to binary converter with the necessary diagram. (10)
 (ii) Find the dual and complement of the following Boolean expression.

xyz’+x’yz+z(xy+w). (6)

Or
11. b. Design a full adder and subtractor using NAND and NOR Gates (16)
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