Beruflich Dokumente
Kultur Dokumente
description
The first members of TI’s new BiMOS general-purpose operational amplifier family are the TLC08x. The BiMOS
family concept is simple: provide an upgrade path for BiFET users who are moving away from dual-supply to
single-supply systems and demand higher ac and dc performance. With performance rated from 4.5 V to 16
V across commercial (0°C to 70°C) and an extended industrial temperature range (–40°C to 125°C), BiMOS
suits a wide range of audio, automotive, industrial, and instrumentation applications. Familiar features like offset
nulling pins, and new features like MSOP PowerPAD packages and shutdown modes, enable higher levels
of performance in a variety of applications.
Developed in TI’s patented LBC3 BiCMOS process, the new BiMOS amplifiers combine a very high input
impedance, low-noise CMOS front end with a high-drive bipolar output stage, thus providing the optimum
performance features of both. AC performance improvements over the TL08x BiFET predecessors include a
bandwidth of 10 MHz (an increase of 300%) and voltage noise of 8.5 nV/√Hz (an improvement of 60%). DC
improvements include an ensured VICR that includes ground, a factor of 4 reduction in input offset voltage down
to 1.5 mV (maximum) in the standard grade, and a power supply rejection improvement of greater than 40 dB
to 130 dB. Added to this list of impressive features is the ability to drive ±50-mA loads comfortably from an
ultrasmall-footprint MSOP PowerPAD package, which positions the TLC08x as the ideal high-performance
general-purpose operational amplifier family.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1OUT 1 10 VDD
1OUT 1 14 VDD 1OUT 1 14 4OUT
1IN – 2 9 2OUT
1IN – 2 13 2OUT 1IN – 2 13 4IN –
1IN+ 3 8 2IN –
GND 4 2IN+ 1IN+ 3 12 2IN – 1IN+ 3 12 4IN+
7
5 GND 4 11 2IN+ VDD 4 11 GND
1SHDN 6 2SHDN
NC 5 10 NC 2IN+ 5 10 3IN+
1SHDN 6 9 2SHDN 2IN – 6 9 3IN –
NC 7 8 NC 2OUT 7 8 3OUT
NC – No internal connection
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V
Differential input voltage range, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND .
VO(PP) = 3 V, AV = 1 0.002%
THD + N Total harmonic distortion plus noise RL = 10 kΩ and 250 Ω, AV = 10 25°C 0.012%
f = 1 kHz AV = 100 0.085%
t(on) Amplifier turnon time‡ 25°C 0.15 µs
RL = 10 kΩ
t(off) Amplifier turnoff time‡ 25°C 1.3 µs
Gain-bandwidth product f = 10 kHz, RL = 10 kΩ 25°C 10 MHz
V(STEP)PP = 1 V, 0.1% 0.18
AV = –1,,
CL = 10 pF,
0.01% 0.39
RL = 10 kΩ
ts Settling time 25°C µs
V(STEP)PP = 1 V, 0.1% 0.18
AV = –1,,
CL = 47 pF,
0.01% 0.39
RL = 10 kΩ
RL = 10 kΩ, CL = 50 pF 32°
φm Phase margin 25°C
RL = 10 kΩ, CL = 0 pF 40°
RL = 10 kΩ, CL = 50 pF 2.2
Gain margin 25°C dB
RL = 10 kΩ, CL = 0 pF 3.3
† Full range is 0°C to 70°C for C suffix and – 40°C to 125°C for I suffix. If not specified, full range is – 40°C to 125°C.
‡ Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current
has reached half its final value.
VO(PP) = 8 V, AV = 1 0.002%
THD + N Total harmonic distortion plus noise RL = 10 kΩ and 250 Ω, AV = 10 25°C 0.005%
f = 1 kHz AV = 100 0.022%
t(on) Amplifier turnon time‡ 25°C 0.47 µs
RL = 10 kΩ
t(off) Amplifier turnoff time‡ 25°C 2.5 µs
Gain-bandwidth product f = 10 kHz, RL = 10 kΩ 25°C 10 MHz
V(STEP)PP = 1 V, 0.1% 0.17
AV = –1,,
CL = 10 pF,
0.01% 0.22
RL = 10 kΩ
ts Settling time 25°C µs
V(STEP)PP = 1 V, 0.1% 0.17
AV = –1,,
CL = 47 pF,
0.01% 0.29
RL = 10 kΩ
RL = 10 kΩ, CL = 50 pF 37°
φm Phase margin 25°C
RL = 10 kΩ, CL = 0 pF 42°
RL = 10 kΩ, CL = 50 pF 3.1
Gain margin 25°C dB
RL = 10 kΩ, CL = 0 pF 4
† Full range is 0°C to 70°C for C suffix and – 40°C to 125°C for I suffix. If not specified, full range is – 40°C to 125°C.
‡ Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current
has reached half its final value.
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage vs Common-mode input voltage 1, 2
IIO Input offset current vs Free-air temperature 3, 4
IIB Input bias current vs Free-air temperature 3, 4
VOH High-level output voltage vs High-level output current 5, 7
VOL Low-level output voltage vs Low-level output current 6, 8
Zo Output impedance vs Frequency 9
IDD Supply current vs Supply voltage 10
PSRR Power supply rejection ratio vs Frequency 11
CMRR Common-mode rejection ratio vs Frequency 12
Vn Equivalent input noise voltage vs Frequency 13
VO(PP) Peak-to-peak output voltage vs Frequency 14, 15
Crosstalk vs Frequency 16
Differential voltage gain vs Frequency 17, 18
Phase vs Frequency 17, 18
φm Phase margin vs Load capacitance 19, 20
Gain margin vs Load capacitance 21, 22
Gain-bandwidth product vs Supply voltage 23
vs Supply voltage 24
SR Slew rate
vs Free-air temperature 25, 26
vs Frequency 27, 28
THD + N Total harmonic distortion plus noise
vs Peak-to-peak output voltage 29, 30
Large-signal follower pulse response 31, 32
Small-signal follower pulse response 33
Large-signal inverting pulse response 34, 35
Small-signal inverting pulse response 36
Shutdown forward isolation vs Frequency 37, 38
Shutdown reverse isolation vs Frequency 39, 40
vs Supply voltage 41
Shutdown supply current
vs Free-air temperature 42
Shutdown pulse 43, 44
TYPICAL CHARACTERISTICS
INPUT BIAS CURRENT AND
INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE INPUT OFFSET CURRENT
vs vs vs
FREE-AIR TEMPERATURE
INPUT BIAS CURRENT AND HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
INPUT OFFSET CURRENT
vs vs
vs
HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
I IB / I IO – Input Bias and Input Offset Current – pA
FREE-AIR TEMPERATURE
20 5.0 1.0
V OH – High-Level Output Voltage – V
VDD = 5 V
–160 2.0 0
–55 –40 –25 –10 5 20 35 50 65 80 95 110 125 0 510 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
TA – Free-Air Temperature – °C IOH - High-Level Output Current - mA IOL - Low-Level Output Current - mA
Figure 4 Figure 5 Figure 6
TYPICAL CHARACTERISTICS
VDD = 12 V
2.0 TA = –40°C 100 100
1.8 80 80
1.6 TA = 125°C 60 60
TA = 70°C
1.4 40 40
VDD = 5 V
AV = 1
1.2 20 20
SHDN = VDD
Per Channel
1 0 0
4 5 6 7 8 9 10 11 12 13 14 15 0 10 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
VDD – Supply Voltage - V f – Frequency – Hz f - Frequency - Hz
Figure 10 Figure 11 Figure 12
12 12
V O(PP) – Peak-to-Peak Output Voltage – V
VDD = 12 V VDD = 12 V
10 10
30
8 8
25
20 6 6
15 VDD = 5 V VDD = 5 V
VDD = 12 V
4 4
10
VDD = 5 V 2 THD+N < = 5% 2 THD+N < = 5%
5 RL = 600 Ω RL= 10 kΩ
TA = 25°C TA = 25°C
0 0 0
10 100 1k 10k 100k 10k 100k 1M 10M 10k 100k 1M 10M
f – Frequency – Hz f - Frequency - Hz f - Frequency - Hz
Figure 13 Figure 14 Figure 15
CROSSTALK
vs
FREQUENCY
0
VDD = 5 V and 12 V
–20 AV = 1
RL = 10 kΩ
–40 VI(PP) = 2 V
For All Channels
–60
Crosstalk – dB
–80
–100
–120
–140
–160
10 100 1k 10k 100k
f – Frequency – Hz
Figure 16
TYPICAL CHARACTERISTICS
DIFFERENTIAL VOLTAGE GAIN AND DIFFERENTIAL VOLTAGE GAIN AND
PHASE PHASE
vs vs
FREQUENCY FREQUENCY
80 0 80 0
70 70
50 50
Phase Phase
Phase – °
40 –90 40 –90
Phase – °
30 30
20 –135 20 –135
10 10
30°
25° Rnull = 100 Ω 2.5
Rnull = 50 Ω 25°
20° 2
20° Rnull = 50 Ω
Rnull = 20 Ω Rnull = 20 Ω
15° 1.5
15°
10° VDD = 5 V VDD = 12 V 1 VDD = 5 V
10°
RL = 10 kΩ RL = 10 kΩ RL = 10 kΩ Rnull = 20 Ω
5° TA = 25°C 5° TA = 25°C 0.5 TA = 25°C
0° 0° 0
10 100 10 100 10 100
CL – Load Capacitance – pF CL – Load Capacitance – pF CL – Load Capacitance – pF
Figure 19 Figure 20 Figure 21
4.5 CL = 11 pF
9.9 21 CL = 50 pF
Rnull = 100 Ω TA = 25°C AV = 1
4
9.8 20
φ m – Phase Margin – dB
SR – Slew Rate – V/ µ s
3.5
9.7 19 Slew Rate –
RL = 10 kΩ
3
9.6 18
2.5 Rnull = 50 Ω 9.5 17
2
9.4 16
Rnull = 20 Ω RL = 600 Ω
1.5 Slew Rate +
9.3 15
VDD = 12 V
1 9.2 14
RL = 10 kΩ
0.5 TA = 25°C 9.1 13
0 9.0 12
10 100 4 5 6 7 8 9 10 11 12 13 14 15 16 4 5 6 7 8 9 10 11 12 13 14 15 16
CL – Load Capacitance – pF VDD - Supply Voltage - V VDD - Supply Voltage - V
Figure 22 Figure 23 Figure 24
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
SLEW RATE SLEW RATE PLUS NOISE
vs vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE FREQUENCY
25 25 1
SR – Slew Rate – V/ µ s
AV = 100
0.1
15 15
Slew Rate + Slew Rate +
10 10 AV = 10
0.01
VDD = 12 V
5 5 RL= 600 Ω and 10 kΩ
CL = 50 pF AV = 1
AV = 1
0 0 0.001
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 100 1k 10k 100k
TA - Free-Air Temperature - °C TA - Free-Air Temperature - °C f – Frequency – Hz
Figure 25 Figure 26 Figure 27
VO(PP) = 8 V AV = 1 RL = 250 Ω AV = 1
RL = 10 kΩ f = 1 kHz f = 1 kHz
1 1
AV = 100 RL = 250 Ω
0.1 0.1
0.01
RL = 600 Ω RL = 600 Ω
AV = 10 0.01
0.01
AV = 1 RL = 10 kΩ 0.001
0.001 RL = 10 kΩ
LARGE SIGNAL FOLLOWER LARGE SIGNAL FOLLOWER SMALL SIGNAL FOLLOWER PULSE
PULSE RESPONSE PULSE RESPONSE RESPONSE
VI (1 V/Div) VI (5 V/Div)
VI(100mV/Div)
V O – Output Voltage – V
V O – Output Voltage – V
V O – Output Voltage – V
VO (2 V/Div)
VO (500 mV/Div)
VO(50mV/Div)
VDD = 5 V VDD = 12 V
RL = 600 Ω RL = 600 Ω
and 10 kΩ and 10 kΩ VDD = 5 V and 12 V
CL = 8 pF CL = 8 pF RL = 600 Ω and 10 kΩ
TA = 25°C CL = 8 pF
TA = 25°C
TA = 25°C
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.10
t – Time – µs t – Time – µs t – Time – µs
Figure 31 Figure 32 Figure 33
TYPICAL CHARACTERISTICS
LARGE SIGNAL INVERTING LARGE SIGNAL INVERTING SMALL SIGNAL INVERTING
PULSE RESPONSE PULSE RESPONSE PULSE RESPONSE
VI (2 V/div) VI (5 V/div)
VI (100 mV/div)
V O – Output Voltage – V
V O – Output Voltage – V
V O – Output Voltage – V
VDD = 5 V and 12 V
RL = 600 Ω and 10 kΩ
VDD = 5 V VDD = 12 V CL = 8 pF
RL = 600 Ω RL = 600 Ω TA = 25°C
and 10 kΩ and 10 kΩ
CL = 8 pF CL = 8 pF
TA = 25°C TA = 25°C
VO (50 mV/Div)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t – Time – µs t – Time – µs t – Time – µs
Figure 34 Figure 35 Figure 36
CL= 0 pF CL= 0 pF
80 RL = 600 Ω 80 80
RL = 600 Ω RL = 600 Ω
60 60 RL = 10 kΩ 60
RL = 10 kΩ RL = 10 kΩ
40 40 40
20 20 20
100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz
Figure 37 Figure 38 Figure 39
SHUTDOWN REVERSE
ISOLATION SHUTDOWN SUPPLY CURRENT SHUTDOWN SUPPLY CURRENT
vs vs vs
FREQUENCY SUPPLY VOLTAGE FREE-AIR TEMPERATURE
I DD(SHDN) – Shutdown Supply Current - µ A
20 118 60
100 1k 10k 100k 1M 10M 100M 4 5 6 7 8 9 10 11 12 13 14 15 16 –55 –25 5 35 65 95 125
f - Frequency - Hz VDD - Supply Voltage - V TA - Free-Air Temperature - °C
Figure 40 Figure 41 Figure 42
TYPICAL CHARACTERISTICS
I DD – Supply Current – mA
I DD – Supply Current – mA
4.5 4.5
Shutdown Pulse - V
Shutdown Pulse - V
4.0 2 4.0 2
VDD = 5 V VDD = 12 V
3.5 CL= 8 pF 3.5 CL= 8 pF
3.0 TA = 25°C 0 3.0 TA = 25°C 0
2.5 2.5
IDD RL = 10 kΩ IDD RL = 10 kΩ
2.0 –2 2.0 –2
1.5 1.5
IDD RL = 600 Ω IDD RL = 600 Ω
1.0 –4 1.0 –4
0.5 0.5
0.0 –6 0.0 –6
0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80
t - Time - µs t - Time - µs
Figure 43 Figure 44
_ Rnull
+
RL CL
Figure 45
APPLICATION INFORMATION
–
IN –
OUT
+ N2
IN +
N1
100 kΩ
R1
VDD –
NOTE A: R1 = 5.6 kΩ for offset voltage adjustment of ±10 mV.
R1 = 20 kΩ for offset voltage adjustment of ±3 mV.
APPLICATION INFORMATION
RG
Input _ RNULL
Output
+
CLOAD
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
RF
IIB–
RG
+ –
VI VO
+
RS
V
OO ǒ ǒ ǓǓ ǒ ǒ ǓǓ
+ VIO 1 ) R
IIB+
G
F " IIB) RS 1 ) R
R
F
G
" IIB– RF
APPLICATION INFORMATION
2
VIN 10 pF
1
With 0
10 kΩ
CF = 10 pF
V O – Output Voltage – V
1.5 –1
_
1
IN +
0.5 VDD = ±5 V
AV = +1 600 Ω 22 pF
VOUT RF = 10 kΩ 50 Ω
0 RL = 600 Ω
CL = 22 pF
–0.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
t - Time - µs
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 50).
RG RF
–
VO
VI +
R1
C1
+ 2pR1C1
ǒ Ǔǒ
f 1
–3dB
V
V
O
I
+ 1 ) RRF
G
1 ) sR1C1
1 Ǔ
Figure 50. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
VI +
R1 R2 _ f
–3dB
+ 2p1RC
C2
RF
RG =
1
RG
RF
( 2–
Q )
APPLICATION INFORMATION
shutdown function
Three members of the TLC08x family (TLC080/3/5) have a shutdown terminal (SHDN) for conserving battery
life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 125
µA/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the
amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left
floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not
inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always
referenced to the voltage on the GND terminal of the device. Therefore, when operating the device with split
supply voltages (e.g. ± 2.5 V), the shutdown terminal needs to be pulled to VDD– (not system ground) to disable
the operational amplifier.
The amplifier’s output with a shutdown pulse is shown in Figures 43 and 44. The amplifier is powered with a
single 5-V supply and is configured as noninverting with a gain of 5. The amplifier turnon and turnoff times are
measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the
single, dual, and quad are listed in the data tables.
Figures 37, 38, 39, and 40 show the amplifier’s forward and reverse isolation in shutdown. The operational
amplifier is configured as a voltage follower (AV = 1). The isolation performance is plotted across frequency
using 0.1 VPP, 2.5 VPP, and 5 VPP input signals at ±2.5 V supplies and 0.1 VPP, 8 VPP, and 12 VPP input signals
at ±6 V supplies.
APPLICATION INFORMATION
DIE
DIE
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
Thermal Pad Area
Quad
Single or Dual
APPLICATION INFORMATION
ǒ Ǔ
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
For a given θJA, the maximum power dissipation is shown in Figure 54 and is calculated by the following formula:
P
D
+ T –T
MAX A
q JA
Where:
PD = Maximum power dissipation of TLC08x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA = Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
7
PWP Package TJ = 150°C
Low-K Test PCB
6 θJA = 29.7°C/W
Maximum Power Dissipation – W
SOT-23 Package
Low-K Test PCB
5 θJA = 324°C/W
DGN Package
Low-K Test PCB
4 θJA = 52.3°C/W
SOIC Package
Low-K Test PCB
3 θJA = 176°C/W
PDIP Package
Low-K Test PCB
θJA = 104°C/W
2
0
–55 –40 –25 –10 5 20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around
the device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in
these graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output
currents and voltages should be used to choose the proper package.
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts , the model generation software used
with Microsim PSpice . The Boyle macromodel (see Note 1) and subcircuit in Figure 55 are generated using
the TLC08x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D Maximum positive output voltage swing D Unity-gain frequency
D Maximum negative output voltage swing D Common-mode rejection ratio
D Slew rate D Phase margin
D Quiescent power dissipation D DC output resistance
D Input bias current D AC output resistance
D Open-loop voltage amplification D Short-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
APPLICATION INFORMATION
99
DLN
3 EGND +
VDD
9 92
FB
+ – 90 91
RSS ISS
RO2 + DLP + –
VB
RP HLIM VLP VLN
+ –
2 10 – – +
IN – VC R2
J1 J2 – C2
DP 6 7
IN + 53 +
1 11 VLIM
12 DC GCM GA
–
C1 8
RD1 RD2
60 RO1
+ DE
VAD 5
– 54
GND
4 – +
VE OUT
*DEVICE=TLC08X_5V, OPAMP, PJF, INT ga 6 0 11 12 402.12E–6
gcm 0 6 10 99 1.5735E–6
* TLC08X_5V – 5V operational amplifier ”macromodel” sub- ioff 0 6 dc 1.212E–6
circuit iss 3 10 dc 130.40E–6
* created using Parts release 8.0 on 12/16/99 at 14:03 hlim 90 0 vlim 1K
* Parts is a MicroSim product. j1 11 2 10 jx1
* j2 12 1 10 jx2
* connections: non-inverting input r2 6 9 100.00E3
* inverting input rd1 4 11 2.4868E3
* positive power supply rd2 4 12 2.4868E3
* negative power supply ro1 8 5 10
* output ro2 7 99 10
* rp 3 4 2.8249E3
.subckt TLC08X_5V 1 2 3 4 5 rss 10 99 1.5337E6
* vb 9 0 dc 0
c1 11 12 4.6015E–12 vc 3 53 dc 1.5537
c2 6 7 8.0000E–12 ve 54 4 dc .84373
css 10 99 986.29E–15 vlim 7 8 dc 0
dc 5 53 dy vlp 91 0 dc 117.60
de 54 5 dy vln 0 92 dc 117.60
dlp 90 91 dx .model dx D(Is=800.00E–18)
dln 92 90 dx .model dy D(Is=800.00E–18 Rs=1m Cjo=10p)
dp 4 3 dx .model jx1 PJF(Is=80.000E–15 Beta=1.2401E–3 Vto=–1)
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 .model jx2 PJF(Is=80.000E–15 Beta=1.2401E–3 Vto=–1)
fb 7 99 poly(5) vb vc ve vlp vln 0 13.984E6 –1E3 1E3 .ends
14E6 –14E6
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.010 (0,25) M
0.014 (0,35)
14 8
0.010 (0,25)
1 7
0°– 8°
0.044 (1,12)
A 0.016 (0,40)
Seating Plane
PINS **
8 14 16
DIM
MECHANICAL INFORMATION
DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,65 0,25 M
0,25
8 5
Thermal Pad
(See Note D)
0,15 NOM
3,05 4,98
2,95 4,78
Gage Plane
0,25
1 4 0°– 6°
0,69
3,05 0,41
2,95
Seating Plane
0,15
1,07 MAX 0,10
0,05
4073271/A 04/98
MECHANICAL INFORMATION
DGQ (S-PDSO-G10) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,27
0,50 0,25 M
0,17
10 6
Thermal Pad
(See Note D)
0,15 NOM
3,05 4,98
2,95 4,78
Gage Plane
0,25
1 5 0°– 6°
0,69
3,05 0,41
2,95
Seating Plane
0,15 0,10
1,07 MAX
0,05
4073273/A 04/98
MECHANICAL INFORMATION
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14 16 18 20
DIM
0.260 (6,60)
0.240 (6,10)
1 8
0.070 (1,78) MAX
0.310 (7,87)
0.035 (0,89) MAX 0.020 (0,51) MIN
0.290 (7,37)
Seating Plane
0.100 (2,54)
0°– 15°
0.021 (0,53)
0.010 (0,25) M 0.010 (0,25) NOM
0.015 (0,38)
4040049/C 08/95
MECHANICAL INFORMATION
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8 5
0.260 (6,60)
0.240 (6,10)
1 4
0.310 (7,87)
0.020 (0,51) MIN
0.290 (7,37)
Seating Plane
0.021 (0,53)
0.010 (0,25) M
0.015 (0,38) 0.010 (0,25) NOM
4040082 / B 03/95
MECHANICAL INFORMATION
PWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,65 0,10 M
0,19
20 11
Thermal Pad
(See Note D)
Gage Plane
1 10 0,25
A 0°– 8°
0,75
0,50
Seating Plane
PINS **
14 16 20 24 28
DIM
4073225/F 10/98
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