ANEXO 1

library ieee; Port(S : in std_ulogic;

use ieee. std_logic_1164.all; R: in std_ulogic;
entity SR_FF is Q: out std_ulogic;
PORT( S,R: in std_logic; QBAR: out std_ulogic
Q, QBAR: out std_logic); );
end SR_FF; end component;
Architecture behavioral of SR_FF is signal a,b,d,e:std_ulogic;
begin begin
PROCESS(S,R) DUT: SR_FF port map (S => a, R => b, Q=>d,
variable tmp: std_logic; QBAR=>e);
begin process begin
if(S='0' and R='0')then a<= '0';
tmp:=tmp; b<= '0';
elsif(S='1' and R='1')then wait for 1 ns;
tmp:='Z'; a<= '0';
elsif(S='0' and R='1')then b<= '0';
tmp:='0'; wait for 1 ns;
else a<= '0';
tmp:='1'; b<= '1';
end if; wait for 1 ns;
Q <= tmp; a<= '0';
QBAR <= not tmp; b<= '1';
end PROCESS; wait for 1 ns;
end behavioral; a<= '1';
b<= '0';
Código de prueba wait for 1 ns;
library IEEE; assert false report "Prueba";
use ieee.std_logic_1164.all; wait;
entity SR_FF_tb is end process;
end SR_FF_tb; end test;
architecture test of SR_FF_tb is
component SR_FF
 ANEXO 2
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL; when 5 => 7 SEG := “10100100”;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; when 6 => 7 SEG := “11100000”;
ENTITY counter_4b_7seg is
Port (clock_50Mhz : in STD_LOGIC; reset: when 7 => 7 SEG := “10001111”;
in bit;
when 8 => 7 SEG := “10000000”;
7SEG: OUT STD_LOGIC_VECTOR (7
downto 0);
when 9 => 7 SEG := “10000100”;
END counter_4b_7seg;
ARCHITECTURE rt1 OF counter_4b_1hz IS when 10 => 7 SEG := “11100010”;
SIGNAL clkout: std_logic;
CONSTANT max: INTEGER : - 50000000; when 11 => 7 SEG := “11100000”;
CONSTANT half: INTEGER : - max/2;
SIGNAL count: INTEGER RANGE 0 TO max; when 12 => 7 SEG := “11110010”;
SIGNAL F: INTEGER RANGE 0 to 15
BEGIN when 13 => 7 SEG := “11000010”;
PROCESS
BEGIN when 14 => 7 SEG := “10110000”;
WAIT UNTIL clock_50Mhz’ EVENT and
clock_50Mhz – ‘1’ ; when 15 => 7 SEG := “10111000”;
IF count < max THEN count < - count + 1;
ELSE count < - 0; when others => null;
END IF;
IF count < half THEN clkout <- ‘0’; end case
ELSE clkout <- ‘1’;
END PROCESS;
END IF;
END PROCESS; END rtl;
PROCESS (clkout, reset)
VARIABLE cuenta: INTEGER RANGE 0 TO
15;
BEGIN
IF (reset= ‘ 1 ’) THEN
Cuenta: =0;
ELSIF (clkout ‘ EVENT AND clkout= ‘ 0 ‘)
THEN
Cuenta: =cuenta + 1;
END IF;
F <= cuenta;
BEGIN
case F is
when 0 => 7 SEG := “10000001”;

when 1 => 7 SEG := “11001111”;

when 2 => 7 SEG := “10010010”;

when 3 => 7 SEG := “10000110”;

when 4 => 7 SEG := “11001100”;

 ANEXO 3

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ALI is

port (
clock : in std_logic;
reset : in std_logic;
control : in std_logic;
q : inout std_logic_vector((4) downto 0)
);
end ALI;

architecture behavioral of ALI is

signal valor: STD_LOGIC_VECTOR (4 DOWNTO 0);
begin
ALI: process (control, reset, Clock) begin
if control = '1' then
if reset = '1' then
q <= "00000";
elsif rising_edge(clock) then
if q= "11011" then
q <= "00000";
else
q <= std_logic_vector(unsigned(q) + 1);
end if;
end if;
else
if reset = '1' then
q <= "00000";
elsif falling_edge(clock) then
if q= "00000" then
q <= "11111";

else
q <= std_logic_vector(unsigned(q) - 1);
end if;
end if;
end if;
end process;
end behavioral;