vigpushkar@gmail.

com
PUSHKAR VIG 9717453007

OBJECTIVE
To be individualistic, innovative and carve a path of success through hard work and mark
my name in the industry.
To work with a reputed organization in a position where I can develop and utilize my
versatile skill set and innovative ideas to effectively contribute my skills ensuring my
growth through the organization’s growth.

EXPERIENCE

Synopsys India Pvt. Ltd.

Application Consultant I July 2017 – Present

Synopsys India Pvt. Ltd.

Application Consultant Intern August 2016 – July 2017

EDUCATION
PG Diploma in VLSI
CDAC ACTS Pune, Maharashtra, India February 2016 – August 2016
First Class

Bachelor of Technology, Electronics & Communication August 2011 – June 2015

SHARDA UNIVERSITY, Uttar Pradesh, India
CGPA (7.29/10)

Higher Secondary Education June 2010 – April 2011

CBSE, Delhi ,India
Percentage 62%

Secondary Education April 2008 – April 2009

CBSE, Delhi, India
Percentage 88%

Technical Skills
 Programming language : C
 Operating systems : Windows, UNIX
 HDL & verification languages : VHDL, VERILOG
 Scripting languages : SHELL, PERL
 EDA Tools : Formality,Design Compiler, ICC2, Xilinx ISE, Xilinx Vivado, Mentor Graphics’
ModelSim, Micro Magic Max, Deeds
 Technical Knowledge : Formal Verification, Synthesis, STA, Physical Design

Key Projects Undertaken

Projects handled as a part of Synopsys AC team

Provided first hand support for key customers for Formality and Design Compiler , some of
the key activities as follows,

High Performance SoC subsystem implementation

 Developed implementation methodologies to have faster convergence of design from
frontend to backend.
 Owned complete block implementation and showed improvement in Performance and
congestion for customer’s crucial block in a SoC.
Tool deployment and trainings
 Successfully deployed and supported Design Compiler, and Formality for key customers.
 Delivering Formality’s version update trainings.

Complete flow RTL2SYNTHESIS

 Established complete RTL2Synthesis flow using LYNX cockpit for a high priority customer.

Other regular activities

 Creating setup for the flow for various blocks
 Flow flush and Regressions on Design Blocks
 Handling point issues as per customer’s query
 Debugging crashes
 Solution provided by writing scripts as per the requirement.

Block Level Design of Lakshya System (Synopsys Training at RV-VLSI)

PnR flow was performed on a design with 34 macros, approx. 45K standard cells operating at 1GHz
frequency with a supply voltage of 1.1 V, using 7 metal layers.

PG Diploma’s Project:

Project Name:- “Real Time Image Processing”

Language used: VERILOG

Project Description:- A basic VGA camera module OV7670 is interfaced to zed board using I2C
protocol. The resolution of the image captured by OV7670 is 640x480 and the captured image is
enhanced in various aspects like brightness, contrast ,luminescence, grayscale, hue, etc... were
achieved by implementing various image enhancing algorithms like morphological operations like
dilation, erosion and the enhanced image is displayed on the screen by using VGA.

FINAL YEAR PROJECT

Project Name:- “Home Automation using Mobile as GSM Module”.

Project Description:- The aim of this project is to monitor for theft, fire and other
combustible gases like liquid petroleum gas (LPG) leakage to enhance home security.
The system detects the theft using PIR sensor, fire using TEMPERATURE sensor and
leakage of the LPG using GAS sensor and alerts the consumer by sending CALL.

SUMMER INTERNSHIP

1- Defence Research and Development Organisation (June 2014 – July 2014)

Project Name:- “Digital weight measuring device with output serially interfaced to a
computer in real time”.

Project Description:- The objective was to add to the security system of the building by
measuring the weight of everyone entering the building to detect the weight of any concealed
equipment or weapon. The final product is expected to read the weight of the person entering,
display it on a Screen.

2- PROGRAMMING IN C from NIIT (June 2013 – July 2013 )

ACTIVITIES & AWARDS

 Qualified GATE exam in 2016.
 Participated in “Tech talk by Google Technology User Group on Android” Workshop in
college.
 1st runner up in management games in college.
 Part of Inter Branch Volleyball team
 3rd in Zonal Volley Ball tournament at School Level

CAPABILITIES

 Decision making under crucial circumstances.
 Ability to work in team.
 Good communication capability.

HOBBIES

 Playing Cricket, Volleyball, Snooker

 Browsing Internet
 Riding Bikes
 Travelling
 Listening music

PERSONAL DETAILS

Name Pushkar Vig

Marital Status Un-Married
Mother Name Ms. Usha Vig
Father Name Mr. Shyam Pal Vig