1001 Solved Problems in Engineering Mathematics

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Metro Manila 1740, PHILIPPINES

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College of Engineering
CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY
Machine Problem No. 1
BASIC LOGIC GATES
I. OBJECTIVES
1. To demonstrate the operation of the basic logic gates (AND, OR,

NOT) using Verilog Hardware Description Language.
2. To interpret the function/operation of the basic logic gates.
3. To design and create a program of the basic logic gates using

Verilog Hardware Description Language.
II. EQUIPMENT / MATERIALS
1. Icarus Verilog Hardware Description Language
2. Computer System
3. Cmd Application
4. Notepad ++
III. DISCUSSION
A hardware description language (HDL) is a computer-based

language that describes the hardware of digital systems in a textual
form. It resembles an ordinary computer programming language,
Machine Problem 1: BASIC LOGIC GATES 1

ENGR. JENNELYN PEREZ-CABALE
such as C, but is specifically oriented to describing hardware

structures and the behaviour of logic circuits. It can be used to
represent logic diagrams, truth tables, Boolean expressions, and
complex abstractions of the behaviour of a digital system. One way
to view an HDL is to observe that it describes a relationship between
signals that are the inputs to a circuit and the signals that are the
outputs of the circuit.
As a documentation language, an HDL is used to represent and

document digital systems in a form that can be read by both
humans and computers and is suitable as an exchange language
between designers. The language content can be stored, retrieved,
edited, and transmitted easily and processed by computer software
in an efficient manner.
HDLs are used in several major steps in the design flow of an

integrated circuit: design entry, functional simulation or verification,
logic synthesis, timing verification, and fault simulation.
Design entry creates an HDL-based description of the functionality

that is to be implemented in hardware. Depending on the HDL, the
description can be in a variety of forms: Boolean logic equations,
truth tables, a netlist of interconnected gates, or an abstract
behavioural model. The HDL model may also represent a partition of
a larger circuit into smaller interconnected and interacting
functional units.
Logic simulation displays the behaviour of a digital system through

the use of a computer. A simulator interprets the HDL description
and either produces readable output, such as a time-ordered
sequence of input and output signal values, or displays waveforms
of the signals. The simulation of a circuit predicts how the hardware

will behave before it is actually fabricated. Simulation detects

functional errors in a design without having to physically create and
operate the circuit. Errors that are detected during a simulation can
be corrected by modifying the appropriate HDL statements. The
stimulus (i.e., the logic values of the inputs to a circuit) that tests the
functionality of the design is called a test bench. Thus, to simulate a
digital system, the design is first described in an HDL and then
verified by simulating the design and checking it with a test bench,
which is also written in the HDL. An alternative and more complex
approach relies on formal mathematical methods to prove that a
circuit is functionally correct.
Logic synthesis is the process of deriving a list of physical

components and their interconnections (called a netlist) from the
model of a digital system described in an HDL. The netlist can be
used to fabricate an integrated circuit or to lay out a printed circuit
board with the hardware counterparts of the gates in the list. Logic
synthesis is similar to compiling a program in a conventional high-
level language. The difference is that, instead of producing an
object code, logic synthesis produces a database describing the
elements and structure of a circuit. The database specifies how to
fabricate a physical integrated circuit that implements in silicon the
functionality described by statements made in an HDL. Logic
synthesis is based on formal exact procedures that implement
digital circuits and addresses that part of a digital design which can
be automated with computer software.
Timing verification confirms that the fabricated, integrated circuit

will operate at a specified speed. Because each logic gate in a
circuit has a propagation delay, a signal transition at the input of a
circuit cannot immediately cause a change in the logic value of
the output of a circuit. Propagation delays ultimately limit the speed

at which a circuit can operate. Timing verification checks each

signal path to verify that it is not compromised by propagation
delay. This step is done after logic synthesis specifies the actual
devices that will compose a circuit and before the circuit is released
for production.
In VLSI circuit design, fault simulation compares the behaviour of an

ideal circuit with the behaviour of a circuit that contains a process-
induced flaw. Dust and other particulates in the atmosphere of the
clean room can cause a circuit to be fabricated with a fault. A
circuit with a fault will not exhibit the same functionality as a fault-
free circuit. Fault simulation is used to identify input stimuli that can
be used to reveal the difference between the faulty circuit and the
fault-free circuit. These test patterns will be used to test fabricated
devices to ensure that only good devices are shipped to the
customer. Test generation and fault simulation may occur at
different steps in the design process, but they are always done
before production in order to avoid the disaster of producing a
circuit whose internal logic cannot be tested.
The language reference manual for the Verilog HDL presents a

syntax that describes precisely the constructs that can be used in
the language. In particular, a Verilog model is composed of text
using keywords, of which there are about 100. Keywords are
predefined lowercase identifiers that define the language
constructs. Examples of keywords are module, endmodule, input,
output, wire, and, or, and not. Any text between two forward slashes
( // ) and the end of the line is interpreted as a comment and will
have no effect on a simulation using the model. Multiline comments
begin with /* and terminate with */. Blank spaces are ignored, but
they may not appear within the text of a keyword, a user-specified
identifier, an operator, or the representation of a number. Verilog is

case sensitive, which means that uppercase and lowercase letters

are distinguishable (e.g., not is not the same as NOT). The term
module refers to the text enclosed by the keyword pair module . . .
endmodule. A module is the fundamental descriptive unit in the
Verilog language. It is declared by the keyword module and must
always be terminated by the keyword endmodule.
IV. ACTIVITY
Create a Verilog HDL program that emulates the function of an OR,

AND and NOT gate. Show your program listing using primitive gates.
Display your output in command prompt and in gtkwave simulation
window.
NOT GATE:
Input Output
0 1
1 0

AND GATE:
Input
Output
X Y
0 0 0
0 1 0
1 0 0
1 1 1
OR GATE:
Input
Output
X Y
0 0 0
0 1 1
1 0 1
1 1 1

V. SOURCE CODE
VI. PRINTED OUTPUT
VII. OBSERVATION
VIII. CONCLUSION

CpE 424L-3 – ADVANCED LOGIC CIRCUIT & DESIGN

LABORATORY
Name of Student : ______________________________________________

Student Number : ______________________________________________
Case No./ Title : ______________________________________________
Year and Section : ______________________________________________
RUBRICS FOR LABORATORY REPORT
Highly Below Not

Exceptional Satisfactory
Criteria Satisfactory Satisfactory Satisfactory Score
(5) (4) (3) (2) (1)
Follows the Follows the Follows the Does not Does not
given format given format given format follow the follow the
TITLE PAGE
and is written and is written but the given format given format
correctly and correctly information is but the and the
(X2)
neatly incorrect information is information is
correct incorrect
All machine All machine 75% of the 50% of the 25% of the
problems problems machine machine machine
have been have been problems problems problems
answered answered have been have been have been
HANDS-ON completely. completely. answered answered answered
ACTIVITY The program The program properly. The properly. The properly. The
(CO1 & CO2) is running / is running / program is program is program is
executing executing running / running / running /
(X8) efficiently. correctly. executing executing executing
Proper Proper correctly. correctly. correctly.
programming programming Proper There is no There is no
techniques techniques programming programming proper
were applied were applied techniques techniques programming
with minimal but with long were applied applied, with techniques
Date of Revision: Date of Effectivity: Endorsed by: Noted by: Approved by:
January 2017 June 2017 Shiella Marie Garcia Joel R. Palacol Lorena C. Ilagan
Department Chair CQI Officer College Dean
number of number of but with long long number applied, with

lines of codes lines of codes number of of lines of long number
and with and without lines of codes codes and of lines of
aesthetic aesthetic and without without codes and
presentations presentations aesthetic aesthetic without
presentations presentations aesthetic
presentations
All required All required 75% of the 50% of the 25% of the
source code source code required required required
SOURCE CODE
is printed, is printed and source code source code source code
(CO1 & CO2)
readable, readable is printed and is printed is printed
well readable
(X2)
presented,
and neat.
All required All required 75% of the 50% of the 25% of the
output is output is required required required
PRINTED printed, printed, output is output is output is
OUTPUT readable, readable and printed and printed printed
(CO1 & CO2) well well readable
presented, presented
(X2) neat and with
pleasing
designs.
The student The student The student The student The student
was able to was able to was able to was not able was not able
identify and identify and explain the to discuss to discuss the
explain tags, explain the tags, and clearly the developed
attribute and tags, and attributes tags, and program.
values used in attributes used in the attributes
OBSERVATION
the used in the development used in the
(CO2)
development development of the development
of the of the program and the program.
(X2)
program. program. with
Very clear, Very clear insufficient
complete and support
and with complete
sufficient and straight
support. to the point.
The student The student The student The student The student
CONCLUSION
was able to was able to was able to was able to was not able
(CO3)
attain all the attain all the attain 75% of attain 50% of to attain any
objectives. objectives. the objective the objectives.
(X2)
Discussed Very clear and is written objectives Conclusions
with clarity, and well. and is not were not

complete, is complete. written well. written well.
written well
and with
sufficient
support.
The The The The The
APPEARANCE laboratory laboratory laboratory laboratory laboratory
AND report follows report follows report follows report does report does
PRESENTATION the given the given the given not follow the not follow the
OF format, format, format but is given format given format.
LABORATORY complete, complete not organized and is not Untidy and
REPORT organized and and with organized with
and neatly organized. incomplete and have incomplete
(X2) presented. contents. incomplete contents.
contents.
TOTAL SCORE
Comment(s):
______________________________________________________________________________
______________________________________________________________________________
ENGR. JENNELYN P. CABALE

_______________________________________ ________________
Name of Faculty and Signature Date

1001 Solved Problems in Engineering Mathematics

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Alabang-Zapote Road, Pamplona 3, Las Piñas City,

Metro Manila 1740, PHILIPPINES

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

Machine Problem No. 1

BASIC LOGIC GATES

1. To demonstrate the operation of the basic logic gates (AND, OR,

2. To interpret the function/operation of the basic logic gates.

3. To design and create a program of the basic logic gates using

II. EQUIPMENT / MATERIALS

1. Icarus Verilog Hardware Description Language

A hardware description language (HDL) is a computer-based

Machine Problem 1: BASIC LOGIC GATES 1

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

such as C, but is specifically oriented to describing hardware

As a documentation language, an HDL is used to represent and

HDLs are used in several major steps in the design flow of an

Design entry creates an HDL-based description of the functionality

Logic simulation displays the behaviour of a digital system through

Machine Problem 1: BASIC LOGIC GATES 2

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

will behave before it is actually fabricated. Simulation detects

Logic synthesis is the process of deriving a list of physical

Timing verification confirms that the fabricated, integrated circuit

Machine Problem 1: BASIC LOGIC GATES 3

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

at which a circuit can operate. Timing verification checks each

In VLSI circuit design, fault simulation compares the behaviour of an

The language reference manual for the Verilog HDL presents a

Machine Problem 1: BASIC LOGIC GATES 4

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

case sensitive, which means that uppercase and lowercase letters

Create a Verilog HDL program that emulates the function of an OR,

Machine Problem 1: BASIC LOGIC GATES 5

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

Machine Problem 1: BASIC LOGIC GATES 6

CPE 424L-3: ADVANCE LOGIC CIRCUIT & DESIGN LABORATORY

VI. PRINTED OUTPUT

Machine Problem 1: BASIC LOGIC GATES 7

CpE 424L-3 – ADVANCED LOGIC CIRCUIT & DESIGN

Name of Student : ______________________________________________

RUBRICS FOR LABORATORY REPORT

Highly Below Not

number of number of but with long long number applied, with

with clarity, and well. and is not were not

ENGR. JENNELYN P. CABALE

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