04 - Comparators and Offset Cancellation Techniques

Comparators and Offset Cancellation Techniques
Jieh-Tsorng Wu
September 7, 2016
ES
National Chiao-Tung University
A
1896
Department of Electronics Engineering
Comparators
Vi1
Vo
Typical Architecture
Vi2
Vi1
Vo A Latch Vo
Vi2
CLK
Vi1 Vi2
0
• A comparator compares the instantaneous values of two inputs and generates a

digital 1 or 0 level depending on the polarity of the difference.
• Usually a clock is applied to improve the performance.
Comparators 4-2 Data-Conversion ICs; Jieh-Tsorng Wu

Comparator Design Considerations
• Resolution (gain).
• Accuracy (offset).
• Input range (dynamic range).
• Common-mode rejection.
• Speed (conversion time, over-drive recovery).
• Power dissipation.
• Input kickback noise.
• Area

Comparison by Using Single-Pole Amplifier
Vo
Vo Vi
Ao
Vi
R C U
g t
m Vi
t
a
Vo h
−ta /(RC)
i C
U= = Ao 1 − e Ao = gmR τm =
Vi gm
 
ta 1 ta
= Ao × ln   ⇒ ≈U if U Ao
τm 1− U
Ao
τm
• The comparator amplification needs not be linear.

Comparison by Using Multi-Stage Cascaded Amplifier
Vo1 Vo2 Vo
Vi
R C R C R C
g g g
m Vi m V o1 m V o(N−1)
ta 1
≈ (U × N!) N for ta Aoτm
τm
• There exits an optimum number of cascaded stages for minimum ta.
• Optimum in N is very broad.

√
• Gain of 10 (i.e. 10 dB) per stage results in near optimum delay (within 10%).

Comparison by Using Positive-Feedback Regeneration
Vo(t)
Vo
Vo1 Vo2 Vo(0)
t
C R g g R C
m m t
a
d Vo1 Vo1
C + + gmVo2 = 0
dt R d Vo Vo
⇒ C + − gm Vo = 0 Vo = Vo1 − Vo2
d Vo2 Vo2 dt R
C + + gmVo1 = 0
dt R
The amplifcation gain of the regenerative latch is
Vo(ta) C RC τm C
U= =e t/τr
τr = = = Ao = gmR τm =
Vo(0) gm − 1/R Ao − 1 1 − 1/Ao gm

Comparison by Using Positive-Feedback Regeneration
The relationship between amplification gain U and amplification time ta is
ta 1
= × ln(U) ≈ ln(U)
τm 1 − 1
A o
• The regeneration time constant is τr ≈ τm(1 + 1/Ao) ≈ τm where τm = C/gm.
• The gain U is not bounded by Ao.
• It is faster than the multi-stage cascaded amplifier, and dissipates less power.
• Require a strobe signal (clock).
• Offset due to mismatches between devices, interconnects, and parasitics.

Metastability of a Regenerative Latch
Vo
VD
The probability of metastability is
VA VD /U VD 1 VD T
− τc
PM = = × = ×e r
VA VA U VA
VD
U Tc t
VD
0 The mean time to failure (MTF) is
U
1
VA
MTF =
PM × fs
VD
fs = Number of comparisons per second
• The voltage swing of a differential digital signal is ±VD .
• The comparator’s analog input is uniformly distributed between ±VA.
• A metastable state occurs when the input is too small that the output cannot exceed
±VD after Tc duration of regeneration.

Comparator Typical Architecture
Preamplifier Latch
Vi Vo
A Latch
Vi1 Vo1
VOSA VOSL
Vi2 Vo2 2 2
vna vnl
• The equivalent input offset and input noise are
2 2
VOSL σ (VOSL) vnl
VOS = VOSA + σ 2(VOS ) = σ 2(VOSA) + vn2 = vna
2
+
A A2 A2
T
− τc
• The probability of metastability is PM = (1/A) × (VD /VA) × e r .
• The preamplifier also provides: (1) input common mode rejection; (2) kick-back noise
reduction; (3) analog signal processing (offset cancellation, averaging).

Offset of a Source-Coupled Pair
Id1 Id2 Id1 Id2
Vi1 M1 M2 Vi1 M1 M2
Vi2 Vi2
VOS
M1 M2 M1 M2
2 2 2
!
Vov σ (∆β) 1 Vov

σ 2(VOS ) = σ 2(∆Vt ) + × = A2V + · A2β
2 β2 W ·L t 4
2 2 2
W AVt σ (∆β) Aβ
β = µCox σ 2(∆Vt ) = =
L W ·L β2 W ·L

Offset of a Regenerative Latch
VDD
I1 I1 = Gm1(Vo1 − VS1)
M3 M1
Gm1
Vo1 Vo2
I2 = Gm2(Vo2 − VS2)
Vo1 Vo2
C1C2 1/2

τr =
C1 Gm2 C2 Gm1Gm2
M4 M2 I2 Gm2 C2 1/2

α=
VSS Gm1 C1
1
Vo1(t) ∼ + [(Vo1(0) − VS1) − α(Vo2(0) − VS2)] × et/τr + VS1
2
1
Vo2(t) ∼ − [(Vo1(0) − VS1) − α(Vo2(0) − VS2)] × et/τr + VS2
2
We have Vo1(∞) − Vo2(∞) > 0 ⇔ Vo1(0) − VS1 > α(Vo2(0) − VS2)

Offset of a Regenerative Latch
Define Vo(t) = Vo1(t) − Vo2(t), then
Vo(∞) > 0 ⇔ Vo(0) > VOS
where
VOS = α[Vo2(0) − VS2] − [Vo2(0) − VS1]
• Consider only capacitor mismatch. Gm1 = Gm2. VS1 = VS2. C1 = C and C2 = C + ∆C.
s 
C2 1 ∆C
VOS = (α − 1) · [Vo2(0) − VS2] =  − 1 · [Vo2(0) − VS2] ≈
 · [Vo2(0) − VS2]
C1 2 C
• Reference: A. Nikoozadeh and B. Murmann, “An Analysis of Latch Comparator Offset

due to Load Capacitor Mismatch,” TCAS-II, 2006/12, pp. 1398–1402.

Comparator Speed-Power-Accuracy Trade-off
For a MOST pair, mismatches and input-referred offset are modeled as
2 2 2 2
!
AVt0 σ (∆β) Aβ 1 Vov
σ 2(∆Vt ) = = ⇒ σ 2(VOS ) = A2V + · A2β
W ·L β2 W ·L W ·L t 4
For a comparator
2
A2Vt · A2β
2 Vov
gm 2I/Vov 1 σ (VOS ) + 4
Speed ∝ ≈ ∝ ≈
2 2 2
C (2/3) · W L · Cox Accuracy VDD W L · VDD
2
Speed × Accuracy 1 VDD
Power ∝ I · VDD ⇒ ∝ ×
Power

2
Vov Vov
Cox · AV + 4 · A2β
2
t
• K. Uyttenhove and M. Steyaert, “Speed-power-accuracy tradeoff in high-speed CMOS

ADCs,” TCAS-II, 2002/4, pp. 280–286.

Equivalent Input Noise of a Source-Coupled Pair
Id1 Id2 Id1 Id2
Vi1 M1 M2 Vi2 Vi1 M1 M2 Vi2
2 2 2
vn1 vn2 vn
The equivalent input noise voltage for a MOSTFET is
2
vn1 1 Kf 1 2

= 4kT γ + · γ≈
∆f gm W LCox f 3
The equivalent input noise voltage for a source-coupled pair is
2 2
vna = 2 × vn1

Regenerative Latch Noise Analysis
VDD
Vo
M3 M1 Vo1 Vo2
Vo1 Vo2
M4 M2 2 g 2
id1 C R m g R C id2
m
VSS
id2 2
q q
= 4kT (γgm) γ≈ id 1(t) = 4kT γgm × n1(t) id 2(t) = 4kT γgm × n2(t)
∆f 3
n1(t) and n2(t) are random variables. n1 = n2 = 0 n21 = n21 = 1 n1 × n2 = 0
d Vo1 Vo1 d Vo2 Vo2
KCL ⇒ C + + gmVo2 + id 1 = 0 C + + gmVo1 + id 2 = 0
dt R dt R

Regenerative Latch Noise Analysis
Let Vo = Vo1 − Vo2, n(t) = n1(t) − n2(t), and G = 1/R, we have
4kT γgm
p
d Vo Vo d Vo gm − G
C + − gmVo + (id 1 − id 2) = 0 ⇒ = × Vo − × n(t) = 0
dt R dt C C
If n(t) = 0, we have the canonical regeneration function:
C
V (t) = V (0)e t/τr
Regeneration Time Constant = τr =
gm − G
Applying the stochastic differential equation (SDE) analysis,
4kT γgm τr h 2t/τ i

=E Vo2(t) + Vo2(0) 2t/τr
e r −1

E e ·
C2 2
2 2kT γgm

2
E Vo (t) ≈ E Vo (0) + e2t/τr = E Vo2(0) + vnl
2
e2t/τr

·
C gm − G
• Reference: P. Nuzzo, et. al., “Noise Analysis of Regenerative Comparators for

Reconfigurable ADC Architectures,” IEEE TCAS1 2008/7, pp. 1441–1454.

Comparator’s Noise Measurement
PDF PDF
vn
Do
σ 0 σ vn Vi 0 vn
Vi
P(Do=1)
1
CLK 0.5
Vi
σ 0 σ
1 2 2
vn2 =σ 2
Probability Density Function = PDF(vn) = √ e −vn /(2σ )
2πσ
Z∞
Vi

P (Do = 1) = PDF(vn + Vi )d vn = 0.5 + 0.5 × erf √
0 2σ

MOST Comparator: Preamp + Regenerative Sense Amplifier
VDD
M3 M5
M4 M6
Vo
V i1 M1 M2
V i2 M7 M8 M9 M10
I1 VDD M11 CLK M12
VSS VSS VSS

• During the track mode (φ = 1), want gm7,m8 < gm9,m10 so that the combination of
M7-M8 and M9-M10 pair become the resistive loads for M5 and M6. The small-signal
voltage gain is
vo gm1 (W/L)6
≈ ·
vi gm9 − gm7 (W/L)4
• During the latch mode (φ = 0), M7, M8, and M11 must be large enough to prevent
the change of latched state by the Vi variation.
• All nodes are low impedance, thus giving fast operation.
• Overdrive recovery can be improved by adding an equalizing switch between the Vo

nodes.
• The preamplifier buffers the kickback from the input circuitry.
• Reference: B. Song, et al., JSSC, 1990/12, pp. 1328–1338.

VDD VDD
CLK M13
M3 M5
M4 M6 M11 M12
IVT1
A
Vo
V i1 M1 M2
B
IVT2
V i2
M8 M7
CLK M9 M10
I1
VSS VSS VSS

• During the track mode (φ = 1), need M7 and M8 large enough to overpower the M9-
M10 cross-coupled pair and pull VA and VB below the input threshold level of IVT1 and
IVT2.
• During the latch mode (φ = 0), the M9-M10 and M11-M12 pairs provide regeneration.
They must be large enough to to prevent the change of latched state by the Vi
variation.
The input threshold level of IVT1 and IVT2 must be high enough to avoid false
triggering.

Regenerative Latches
VDD VDD
M19 M20 M19 M20

M17 M18 M17 M18
CLK CLK CLK CLK
CLK M15 M16 CLK Vl M15 M16 Vl
M13 M14 M13 M14
Vl M11 M12 Vl CLK M11 M12 CLK
VSS VSS
Triode Input Stage Saturated Input Stage
• By moving input pair to the top of the latch, input pair can be biased into saturation
for lower offset.

A Low-Offset Regenerative Latch
VDD
• No power dissipation when

M5 M6
M7 M8 CK=0.
M9 M10
CLK CLK
• When CK=1, the M1-M2 pair is
Vo
activated first, the M3-M4 pair is
second, and the M5-M6 pair is
M3 M4 the last.
• Kickback noise is generated at

M1 M2 input during the 0-to-1 transition
Vi of CK.
CLK M11
• Reference: B. Razavi, 1999
ISSCC Short Course.
VSS

A Dynamic Two-Stage Comparator
VDD VDD
M17
M3 M4 M11 M12
φ
Van Vap M13 M14
Vap Van
C1 C2
Vop Von
Vip M1 M2 Vin
φ φ
φ M5 M17 M15 M16 M18
VSS VSS
• Reference: M. van Elzakker, el. al., “A 10-bit Charge-Redistribution ADC Consuming

1.9 µW at 1 MS/s”, JSSC 2010/5, pp. 1007–1015.

A Dynamic Two-Stage Comparator
Let C1 = C2 = C. When φ = 1, let gm1 = gm2 = gm, gm/Id = 2/Vov ∼ 1/nUT , Id = Id 5/2.
gm Vi gm Vi Id 1 Id 2
= Id +
Id 1 Id 2 = Id − Van = VDD − ×t Vap = VDD − ×t
2 2 C C
Van + Vap Id gm Vi
Va,cm = = VDD − × t Va,d m = Vap − Van = ×t
2 C C
∆Va,d m gmVi Vi ∆Va,d m ∆Va,cm
= = ⇒ Ad m ≡ = ∆Va,cm ∼ |Vtp|
∆Va,cm Id Vov /2 Vi Vov /2
Id C
∆Va,cm = × Ta ⇒ Ta = ∆Va,cm ×
C Id
Consider only thermal noise. The equivalent input noise power is estimated as
2 1
vn2 ≈ 4kT × × Bn Bn =
gm 2Ta
kT Id 1 kT Vov /2 kT 4
⇒ vn2 = 4 × × =4× × = ×
C gm ∆Va,cm C ∆Va,cm C Ad m

Double Latching to Reduce Meta-Stability
VDD VDD
φa φa φa φa
b
φb
φb
M3 M4 M3 M4
b
Static Latch Dynamic Latch
M1 M2 M1 M2
Vi Vi
φa M11 φa M11
VSS VSS
φa
φb

A Dual-SCP Differential-Difference Preamplifier
Io Io
Vi = Vi + − Vi −
Vi Gm1 Vi VR Gm2 VR VR = VR+ − VR−
Io = Io+ − Io−
IB IB
Io = Gm1Vi − Gm2VR
= Gm(Vi − VR ) if Gm1 = Gm2
• Matched source-coupled pairs.
• The SCP’s input voltage range must cover the full Vi range.

An Alternative Dual-SCP Differential-Difference Preamplifier
Io Io
Vi + = +∆Vi + VCMI
Vi − = −∆Vi + VCMI
Vi Gm1 VR VR Gm2 Vi VR+ = +∆VR + VCMR
VR− = −∆VR + VCMR
IB IB Io = Io+ − Io−
Io = Gm1 (+∆Vi + VCMI ) − (+∆VR + VCMR ) − Gm2 (−∆Vi + VCMI ) − (−∆VR + VCMR )

= (Gm1 + Gm2) · (∆Vi − ∆VR ) + (Gm1 − Gm2) · (VCMI − VCMR )
• Matched source-coupled pairs or matched common-mode voltage.
• The SCP’s input voltage range must cover the common-mode difference between Vi
and VR , i.e., VCMI − VCMR .

Differential-Difference Preamplifier + Latch
VDD VDD
M15 M17 M18 M16
M7 M9 M10 M8 φ φ
Vop Von
Van Vap
M13 M14
M1 M3 M4 M2
Vip Vin Vap M11 M12 Van
VRP VRN
VB1
M5 M6 φ M19
VSS VSS
Differential−Difference Preamplifier Regenerative Latch

A Switched-Capacitor Differential-Difference Preamplifier
Vi VCMI
1 Ca
1d S3 Ci
S1
2
VR
S5 Vo
2
VR
S6 Ci A1
1d 1 Ca
S4 S2
Vi VCMI
Ci
During φ2 = 1 Vo = −(Vi − VR ) × × A1
Ci + Ca
• Ca is the input capacitance of A1.
• The A1’s input common-mode range must tolerate the switching errors from S1 and
S2, and the common-mode difference between Vi and VR .

Pipelined Comparator with SC Preamplifier
VDD VDD
M3 M4
M5 M6
φ2 φ2
φ1d
a
Vi
Ci1 Ci2
M3 M4
VR M1 M2 φ2
φ2d
M1 M2
IB
φ1 φ1
VCMI VCMI a
VSS
φ2 M11
φ1 VSS
φ2

Output Offset Storage (OOS)
V V
2 c o
V
i Latch V’
S1 o
A C Q
S2 o C
1 S3 L
V OS V OSL
1a
During the reset mode (φ1 = 1)
Vo = 0 Vc = A × VOS
During the amplification mode (φ2 = 1)

0
Vo Co C V C + C

∆Q o ∆Q OSL o L
= Vi × A · + − VOSL = A · Vi + − ·
UL Co + CL Co + CL Co + CL ACo A Co
1 Co + CL ∆Q

Input-Referred Offset = VOS,i n = × VOSL · −
A Co Co
UL = Latch Amplification

Output Offset Storage (OOS)
• During the reset-to-amplification transition, let S3 open before S2, so that ∆Q can be
a constant.
• Amplifier A cannot employ high gain.
• Amplifier A must cover the input common-mode range.
• Want latch with high-impedance (capacitive) input so as not to discharge Co during

amplification.
• Make Co CL to avoid attenuation.

Multistage Output Offset Storage
S1 V V V
c1 X c2 Y c3
V V
i o
A1 C A2 C A3 C
1 2 3
V OS1 V OS2 V OS3
S2 S3 S4 S5
S1
S2
S3
S4
S5
I II III IV V

During Period I, S1 open, S2–S5 closed.
Vc1 = A1VOS1 Vc2 = A2VOS2 Vc3 = A3VOS3
During Period II, S3 open.
VX = 2 = S3 Switching Error Vc1 = A1VOS1 + 2 Vc2 = A2(VOS2 − 2)
During Period III, S4 open.
VY = 3 = S4 Switching Error Vc2 = A2(VOS2 − 2) + 3 Vc3 = A3(VOS3 − 3)
During Period IV, S5 open.
Vo = 4 = S5 Switching Error Vc3 = A3(VOS3 − 3) + 4

During Period V (amplification mode), S2 closed, S1 open.
Vo = A1 · A2 · A3 · Vi + 4
4
VOS,i n =
A1 · A2 · A3

Input Offset Storage (IOS)
1a
Q
V S3
c V
2 o
V V’
i Latch o
S1 Ci
S2 A
C
1 L
V OS V OSL
A
Vo = Vc = VOS ×
A+1
0
Vo VOS ∆Q VOSL

A ∆Q
= −Vi × A + VOS − A − VOSL = −A Vi − + +
UL A + 1 Ci A + 1 Ci A
VOS∆Q VOSL
Input-Referred Offset = VOS,i n = − −
A + 1 Ci A

Input Offset Storage (IOS)
• The S3 switching error ∆Q is input-independent.
• During the reset-to-amplification transition, let S3 open before S2.
• The IOS allows rail-to-rail input common-mode level and quick overdrive recovery.
• Amplifier A can employs high gain.
• Amplifier A may require compensation Cc to ensure closed-looped stability. Cc can

be switched off during the amplification mode.

Multistage Input Offset Storage
V S3 V S4
S1 c1 c2
V V
i o
C C X
1 A1 2 A2
V OS1 V OS2
S2
S1
S2
S3
S4
I II III IV

During Period I, S1 open, S2–S4 closed.
A1 A2 A2 A1
Vc1 = VOS1 Vc2 = VOS2 − Vc1 = VOS2 − VOS1
A1 + 1 A2 + 1 A2 + 1 A1 + 1
During Period region II, S3 open. Let 1 be the 3 switching error.
A1 A2 A1
Vc1 = VOS1 + 1 Vc2 = VOS2 − VOS1 + A11
A1 + 1 A2 + 1 A1 + 1
During Period III, S4 open. Let 2 be the S4 switching error.
A2 A1 A2
Vc2 = V − V + A11 + 2 Vo = V − A 2 2
A2 + 1 OS2 A1 + 1 OS1 A2 + 1 OS2

During Period IV (amplification mode), S2 open, S1 closed.
A2 VOS2 2

Vo = A 1 A 2 Vi + VOS2 − A22 = A1A2 Vi + −
A2 + 1 A1(A2 + 1) A1
VOS2 2
Input-Referred Offset = VOS,i n = −
A1(A2 + 1) A1

MOST Comparator: Auto-Zeroing Inverter
VDD
Vo
2 Vo = Vx
Vi1 MA
S1 Vx 1
Vo
1 C S3
Vi2 I Bias Point
MB
S2
Vx
VSS

MOST Comparator: Auto-Zeroing Inverter
• Trade-off between speed and resolution by selecting different value of C.
• Very sensitive to supply noises.
• Power dissipation is strongly process- and supply-dependent.
• Kickback noise presented at the inputs.
• Reference: T. Kumamoto, et. al., JSSC, 1986/12, pp. 976–982.

MOST Comparator: Cascaded Auto-Zeroing Inverters
VDD VDD
V M1 M3
i1
S1
Latch Vo
C S3 C S4
V 1 2
i2 M2 M4
S2
VSS VSS CK
S1
S2
S3
S4
CK

Differential Auto-Zeroing Preamplifier
VDD
1 1
Vip M3 M4 Vin
S1 1a 1a S2
Vop Von
2 C S5 S6 C 2
VRp I1 I2 VRn
M1 M2
S3 S4
IB
VSS
• Switched-capacitor differential-difference preamplifier.
• Turn off S5 and S6 switches before turning off S1 and S2 switches.

Variable-Offset Regenerative Latch
VDD
CK M5 M6 CK
M10 M8 M9 M11
Vo2 Vo1
M3 I1 M4
C1
I1 Vi1 M1 M2 Vi2 I2
C2
VSS CK VSS
M7
VSS
• Offset is adjusted by varying C1 and C2, or I1 and I2.

Comparator Offset Calibration
V CM
V OS
CK
CAL
CAL
V i1
Dc 0 t
V i2
CAL V OS
CAL
V CM Up/Down
Counter
• During Calibration, Vi = Vi 1 − Vi 2 = 0.

Comparator Background Offset Calibration
q[k] CK q[k]
V i1 Dr
Dc
V i2
CHP1 V OS CHP2
Up/Down
Counter
• CHP1 and CHP2 are random choppers controlled by a binary random sequence, q[k].
• Reference: C-C Huang and J-T Wu, “A Background Comparator Calibration

Technique for Flash Analog-to-Digital Converters,” IEEE TCAS-I, 2005/09, pp. 1732-
1740.

Latch with Offset-Calibration Charge Pump
φ1 φ1a φc
V1 Vcm
S1 C1 S3 Va
φ2 Dc
VRC [n] Vc
S2
Vcm Vos Latch
Ip
up φ1a
1
Dc
φ1
dn
0 φ2
C2
In φc
Offset−Calibration Charge Pump
• Reference: Y-H Chung and J-T Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” IEEE JSSC,
2010/11, pp. 2217–2226.

Latch with Offset-Calibration Charge Pump
VDD
φc M9 M10 φc
Dc,p Dc,n
M11 M12
Va,p M1 M2 Va,n Vcm M5 M6 Vc
VDD M3 VDD M7
φc M4 φc M8
VSS VSS

BJT Latched Comparator
VCC
R1 R2
Q7
Q8
Q1 Q2 Q3 Q4
Vi Vo
Q5 Q6
φ
I1 I2 I3
VEE

BJT Latched Comparator
• During the track mode (φ = 1), the variation of input capacitance with Vi causes
input-dependent delay and hence harmonic distortion.
• Speed may be limited by overdrive recovery.
• During latch-to-track transition, Q1 and Q2 are initially off, the I1 current then flows
through Q5 and the emitter junctions of Q1 and Q2 to the input, creating kickback
noise.
• Usually preceded by a buffer.

A Sampled-Data Amplifier with Internal Offset Cancellation
φ1 = 1 (Sample)
C
3
C C
1 5
1 V V o1
i1
C a1 a2
3
2
1 V V o2
i2
C C C C
1 5 2 6
1
V V o1 C
i1 4
1
2 a1 a2
1 1 φ2 = 1 (Hold)
V V o2
i2 C
C C 1 3
2 6
C C
1 5
2 V o1
C
4 1
a1 a2
V o2
C C
2 6
C
4

A Sampled-Data Amplifier with Internal Offset Cancellation
• During reset mode, OOS is applied to a1 and IOS is applied to a2. a1 is low gain and
a2 is high gain.
• The OOS and IOS perform correlated double sampling (CDS) so that the effect of 1/f
noise is also reduced.
• Additional capacitors in the signal path (i.e., C5 and C6) can degrade the closed-loop
settling behavior.
• Reference: Yen, JSSC, 1982/12, pp. 1008–1013.

Operational Amplifier with Offset Compensation
VDD
M9
M10 VBP1
M3
M4 VBP2
S3 Vo1
1
2
Vi1 M1 M2 Vo2
S1 1 1
M11
2 M6 VBN2
Vi2 M5 S5 M12 S6
S2
C1 C2
S4
1 I1 VBN1 I2
M8
M7
VSS

S3
S1 1
Vi 2 Vo
S2 G m1 R
S4
1 S5
G m2 S6
C1 C2
• The Gm2 compensation circuit is not in the signal path. The original frequency/speed
performance can be maintained.

Vo = −VOS1 · Gm1R + (−VOS2 − Vo) · Gm2R

VOS1 · Gm1R + VOS2 · Gm2R Gm1
⇒ Vo = − ⇒ Vo ≈ −VOS1 · − VOS2 If Gm2R 1
1 + Gm2R Gm2
• VOS1 and VOS2 are the input-referred offset of the Gm1-R and Gm2-R pairs.
Gm1 VOS1 VOS2 Gm2

Vo = Vi · Gm1R − VOS1 − VOS2 + ∆V · Gm2R = Gm1R Vi − − + ∆V
Gm2 Gm2R Gm1R Gm1
VOS1 VOS2 Gm2
Input-Referred Offset = VOS,i n = + − ∆V ·
Gm2R Gm1R Gm1
• ∆V is due to the mismatch between the switching errors of S5 and S6. Its effect on Vo
can be reduced by making Gm2/Gm1 small.

The Chopper Stabilization Technique
1
fc
1
Vi A Vo
1 LPF
VOS
f
f f f f f
0 0 0 fc 0 fc 0
• The bandwidth of the amplifier A must be wider than fc.
• The amplifier A should employ design of minimizing thermal noise.

A Chopper Operational Amplifier
VDD
φ
R1 R2 I3 I4 I5
M5 M6
C1
M3 M4 1
φ C2 Vo
RL
Vi M1 M2
Vi
I1 I2 M7 M8 M9
VSS
φ a
b φa
b
φb
a

A Chopper Operational Amplifier
• The M1–M2 is a low-gain low-noise stage.
• The M3–M4 is a high-gain stage with low Gm. A common-mode feedback circuit is
required to stabilize the drain voltages of M3 and M4.
• The M5–M8 is a high-gain Miller stage for frequency compensation and low-pass
filter.
• The M9 is a low-gain buffer stage.
• The chopper can introduce additional kT/C noise.
• Reference: A. Bakker, et al., “A CMOS Nested-Chopper Instrumentation Amplifier

with 100-nV Offset,” JSSC 2000/12, pp. 1877–1883.
• Reference: C. Enz and G. Temes, “Circuit Techniques for Reducing the Effects
of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper
Stabilization,” Proc. IEEE, 1996/11, pp. 1584–1614.

Residual Offset of Chopper Amplifier
1
fc
1
Vi A Vo
1 LPF
VOS
f
t Modulation Signal
t Spikes at Input
t Demodulation Signal
Residual Offset
t Demodulated Spikes

Chopper Modulation with Guard Time
1
fc
1
Vi A Vo
1 LPF
VOS
f
t Modulation Signal
t Spikes at Input
t Demodulation Signal
Residual Offset
t Demodulated Spikes

Chopper Modulation with Guard Time
• The spikes at the input is due to the switching error mismatch of the chopper.
• The residual offset is linear dependent on chopper frequency.

√
• Reference: Q. Huang and C. Menolfi, “A 200nV Offset 6.5nV/ Hz Noise PSD 5.6kHz
Chopper Instrumentation Amplifier,”, ISSCC 2002.

Ripple at Chopper Amplifier Output

Ripple Suppression Using Auto Correction Feedback
• Reference: Y. Kusuda, “Auto Correction Feedback for Ripple Suppression in a

Chopper Amplifier,” JSSC, 2010/08, pp. 1436–1445.

Switched-Capacitor Notch Filter

A Chopper Amplifier (Kusuda) — Block Diagram
• 0.35 µm CMOS technology, 5 V supply, and 100 pF external load capacitor.
• 50 kHz chopping frequency.

A Chopper Amplifier (Kusuda) — Gm, Gm, Gm Schematic
√
Achieve 1.3 µV input offset, 95 nV/ Hz input noise density, 130 dB open-loop dc gain,
and 100 kHz unity-gain frequency, at 13 µA supply current.

04 - Comparators and Offset Cancellation Techniques

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04 - Comparators and Offset Cancellation Techniques

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Comparators and Offset Cancellation Techniques

• A comparator compares the instantaneous values of two inputs and generates a

• Usually a clock is applied to improve the performance.

Comparators 4-2 Data-Conversion ICs; Jieh-Tsorng Wu

• Input range (dynamic range).

• Speed (conversion time, over-drive recovery).

• Input kickback noise.

Comparators 4-3 Data-Conversion ICs; Jieh-Tsorng Wu

• The comparator amplification needs not be linear.

Comparators 4-4 Data-Conversion ICs; Jieh-Tsorng Wu

• There exits an optimum number of cascaded stages for minimum ta.

• Optimum in N is very broad.

Comparators 4-5 Data-Conversion ICs; Jieh-Tsorng Wu

The amplifcation gain of the regenerative latch is

Comparators 4-6 Data-Conversion ICs; Jieh-Tsorng Wu

The relationship between amplification gain U and amplification time ta is

• The regeneration time constant is τr ≈ τm(1 + 1/Ao) ≈ τm where τm = C/gm.

• The gain U is not bounded by Ao.

• Require a strobe signal (clock).

• Offset due to mismatches between devices, interconnects, and parasitics.

Comparators 4-7 Data-Conversion ICs; Jieh-Tsorng Wu

• The voltage swing of a differential digital signal is ±VD .

• The comparator’s analog input is uniformly distributed between ±VA.

Comparators 4-8 Data-Conversion ICs; Jieh-Tsorng Wu

• The equivalent input offset and input noise are

Comparators 4-9 Data-Conversion ICs; Jieh-Tsorng Wu

Comparators 4-10 Data-Conversion ICs; Jieh-Tsorng Wu

We have Vo1(∞) − Vo2(∞) > 0 ⇔ Vo1(0) − VS1 > α(Vo2(0) − VS2)

Comparators 4-11 Data-Conversion ICs; Jieh-Tsorng Wu

Define Vo(t) = Vo1(t) − Vo2(t), then

Vo(∞) > 0 ⇔ Vo(0) > VOS

VOS = α[Vo2(0) − VS2] − [Vo2(0) − VS1]

• Reference: A. Nikoozadeh and B. Murmann, “An Analysis of Latch Comparator Offset

Comparators 4-12 Data-Conversion ICs; Jieh-Tsorng Wu

For a MOST pair, mismatches and input-referred offset are modeled as

• K. Uyttenhove and M. Steyaert, “Speed-power-accuracy tradeoff in high-speed CMOS

Comparators 4-13 Data-Conversion ICs; Jieh-Tsorng Wu

Vi1 M1 M2 Vi2 Vi1 M1 M2 Vi2

The equivalent input noise voltage for a MOSTFET is

The equivalent input noise voltage for a source-coupled pair is

Comparators 4-14 Data-Conversion ICs; Jieh-Tsorng Wu

Comparators 4-15 Data-Conversion ICs; Jieh-Tsorng Wu

Let Vo = Vo1 − Vo2, n(t) = n1(t) − n2(t), and G = 1/R, we have

Applying the stochastic differential equation (SDE) analysis,

4kT γgm τr h 2t/τ i

• Reference: P. Nuzzo, et. al., “Noise Analysis of Regenerative Comparators for

Comparators 4-16 Data-Conversion ICs; Jieh-Tsorng Wu

Comparators 4-17 Data-Conversion ICs; Jieh-Tsorng Wu

I1 VDD M11 CLK M12

VSS VSS VSS

Comparators 4-18 Data-Conversion ICs; Jieh-Tsorng Wu

• All nodes are low impedance, thus giving fast operation.

• Overdrive recovery can be improved by adding an equalizing switch between the Vo

• The preamplifier buffers the kickback from the input circuitry.

• Reference: B. Song, et al., JSSC, 1990/12, pp. 1328–1338.

Comparators 4-19 Data-Conversion ICs; Jieh-Tsorng Wu

VSS VSS VSS

Comparators 4-20 Data-Conversion ICs; Jieh-Tsorng Wu

Comparators 4-21 Data-Conversion ICs; Jieh-Tsorng Wu

M19 M20 M19 M20

CLK M15 M16 CLK Vl M15 M16 Vl

M13 M14 M13 M14

Vl M11 M12 Vl CLK M11 M12 CLK

• Make Co CL to avoid attenuation.

VX = 2 = S3 Switching Error Vc1 = A1VOS1 + 2 Vc2 = A2(VOS2 − 2)

VY = 3 = S4 Switching Error Vc2 = A2(VOS2 − 2) + 3 Vc3 = A3(VOS3 − 3)

Vo = 4 = S5 Switching Error Vc3 = A3(VOS3 − 3) + 4

During Period region II, S3 open. Let 1 be the 3 switching error.

During Period III, S4 open. Let 2 be the S4 switching error.