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PLASMA TV
SERVICE MANUAL
CHASSIS : PD12C

MODEL : 60PZ750S 60PZ750S-ZA

CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

P/NO : MFL67083606(1103-REV00) Printed in Korea

 CONTENTS

CONTENTS ............................................................................................................................... 2

SAFETY PRECAUTIONS ...........................................................................................................3

SPECIFICATION.........................................................................................................................4

ADJUSTMENT INSTRUCTION ..................................................................................................6

BLOCK DIAGRAM....................................................................................................................11

EXPLODED VIEW .................................................................................................................. 12

SCHEMATIC CIRCUIT DIAGRAM ..............................................................................................

Copyright ©2011 LG Electronics Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
 SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in
the Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to
prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance Leakage Current Hot Check (See below Figure)

An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this monitor is blown, replace it
with the specified.
When replacing a high wattage resistor (Oxide Metal Film
Resistor, over 1W), keep the resistor 10mm away from PCB.
Plug the AC cord directly into the AC outlet.
Do not use a line Isolation Transformer during this check.
Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC
voltage measurements for each exposed metallic part. Any
voltage measured must not exceed 0.75 volt RMS which is
corresponds to 0.5mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.

Keep wires away from high voltage or high temperature parts. Leakage Current Hot Check circuit

Due to high vacuum and large surface area of picture tube, AC Volt-meter
extreme care should be used in handling the Picture Tube.
Do not lift the Picture tube by it's Neck.

Good Earth Ground

such as WATER PIPE,
Leakage Current Cold Check(Antenna Cold Check) CONDUIT etc.
To Instrument’s
With the instrument AC plug removed from AC source, connect 0.15uF
exposed
an electrical jumper across the two AC plug prongs. Place the METALLIC PARTS
AC switch in the on position, connect one lead of ohm-meter to
the AC plug prongs tied together and touch other ohm-meter
lead in turn to each exposed metallic parts such as antenna 1.5 Kohm/10W
terminals, phone jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1MΩ and 5.2MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

Copyright ©2011 LG Electronics Inc. All rights reserved. -3- LGE Internal Use Only
Only for training and service purposes
 SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.

V Application Range
This spec is applied to PDP TV used PD12C Chassis.

Model Name Market Place Brand

Albania, Austria, Belgium, Bosnia, Bulgaria, Coratia, Czech, Denmark,
Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy,
60PZ750S-ZA Kazakhstan, Latvia, Lithuania, Luxembourg, Morocco, Netherlands, Norway, LG
Poland, Portugal, Romania, Russia, Serbia, Slovakia, Slovenia, Spain,
Sweden, Switzerland, Turkey, Ukraine, UK

V Specification
Each part is tested as below without special appointment.
(1) Temperature : 25 °C ± 5 °C (77 °F ± 9 °F), CST : 40 ± 5
(2) Relative Humidity: 65 % ± 10 %
(3) Power Voltage: Standard Input voltage (100 V - 240 V ~, 50 / 60 Hz)
* Standard Voltage of each product is marked by models.
(4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with
SBOM.
(5) The receiver must be operated for about 20 minutes prior to the adjustment.

V Test Method
(1) Performance : LGE TV test method followed.
(2) Demanded other specification
Safety : CE, IEC specification
EMC : CE, IEC

Model Name Market Remark

Albania, Austria, Belgium, Bosnia, Bulgaria, Coratia, Czech, Denmark,
Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Safety : IEC/ EN60065,
60PZ750S-ZA Kazakhstan, Latvia, Lithuania, Luxembourg, Morocco, Netherlands, EMI : EN55013
Norway, Poland, Portugal, Romania, Russia, Serbia, Slovakia, EMS : EN55020
Slovenia, Spain, Sweden, Switzerland, Turkey, Ukraine, UK

V Module Specification
(1) 3D 60” - FHD
No Item
1 Display Screen Device
2 Aspect Ratio
3 PDP Module
4 Operating Environment
5 Storage Environment
6 Input Voltage
Specification Remark
152 cm (60 inch) wide Color Display Module PDP
16:9
PDP60R3####,
RGB Closed (Well) Type, Glass Filter (43%)
Pixel Format: 1920 horiz. By 1080 ver.
1) Temp. : 0 deg ~ 40 deg
2) Humidity : 20 % ~ 80% LGE SPEC
3) Temp. : -20 deg ~ 60 deg
4) Humidity : 10 % ~ 90 %
AC 100 V ~ 240 V, 50 / 60 Hz Maker LG

Copyright ©2011 LG Electronics Inc. All rights reserved. -4- LGE Internal Use Only
Only for training and service purposes
V Model General Specification
No Item Specification Remarks
1 Market Albania, Austria, Belgium, Bosnia, Bulgaria, 36 Country
Coratia, Czech, Denmark, Estonia, Finland, ,
France, Germany, Greece, Hungary, Ireland,
Italy, Kazakhstan, Latvia, Lithuania, Luxembourg,
Morocco, Netherlands, Norway, Poland, Portugal,
Romania, Russia, Serbia, Slovenia, Spain, Sweden,
Slovakia, Switzerland, Turkey, Ukraine, UK
2 Broadcasting system 1) PAL/SECAM BG EU (PAL Market)
2) PAL/SECAM DK
3) PAL Ⅰ/Ⅱ
4) SECAM L/L’
5) DVB T / T2 Supporting T2 is only for **PZ***T./W
6) DVB C
7) DVB S Supporting S is only for **PZ***S/G
3 Receiving system Analog : Upper Heterodyne G DVB-T
Digital : COFDM - Guard Interval(Bitrate_Mbit/s)
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
G DVB-C
- Symbolrate :
4.0Msymbols/s to 7.2Msymbols/s
- Modulation :
16QAM, 64-QAM, 128-QAM and 256- QAM
G DVB-S
- symbolrate
DVB-S2 (8PSK / QPSK) : 2 ~45Msymbol/s
DVB-S (QPSK) : 2 ~ 45Msymbol/s
- viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5,
5/6, 8/9, 9/10
4 Scart Jack (1EA) PAL, SECAM Scart 1 Jack is Full scart and support
RF-OUT(Analog), MNT-OUT
5 Video Input (1EA) PAL, SECAM, NTSC Side AV
6 Component Input (1EA) Y/Cb/Cr, Y/ Pb/Pr
7 RGB Input RGB-PC Analog (D-Sub 15Pin)
8 HDMI Input (4EA) HDMI-PC HDMI/DTV,HDMI2, HDMI3, HDMI4
HDMI-DTV
9 Audio Input (3 EA) RGB/DVI Audio, Component, AV L/R Input
10 SPDIF Out(1 EA) SPDIF Out
11 USB(2EA) For SVC, S/W Download, X-Studio, DivX
12 Ethernet LAN
Copyright ©2011 LG Electronics Inc. All rights reserved. -5- LGE Internal Use Only
Only for training and service purposes
 ADJUSTMENT INSTRUCTION

1. Application Range * Each Chassis has it’ own MAC Address. Please be careful of
download.
This spec sheet is applied to all of the PD12C chassis.

2. Specification
(1) Because this is not a hot chassis, it is not necessary to use
an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of
25 °C ± 5 °C of temperature and 65 % ± 10 % of relative
humidity if there is no specific designation.
(4) The input voltage of the receiver must keep 100 V ~ 240
V, 50 / 60 Hz.
(5) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over
15 °C 3-2. ADC Adjustment
- In case of keeping module is in the circumstance of 0 °C,
it should be placed in the circumstance of above 15 °C O Auto-control adjustment protocol(RS-232C)
for 2 hours Order Command Set response
- In case of keeping module is in the circumstance of below 1. Inter the aa 00 00 a 00 OK00x
-20 °C, it should be placed in the circumstance of above Adjustment
15 °C for 3 hours,. mode
2. Change the XB 00 40 b 00 OK40x (Adjust 480i Comp1 )
Source XB 00 60 (Adjust 1080p Comp1)
O After RGB Full White in HEAT-RUN Mode, the receiver b 00 OK60x (Adjust 1080p RGB)
must be operated prior to the adjustment. 3. Start ad 00 10
O Enter into HEAT-RUN MODE Adjustment
4. Return the OKx ( Success condition )
1) Press the POWER ON KEY on R/C for adjustment.
Response NGx ( Failed condition )
2) OSD display and screen display PATTERN MODE. 5. Read data ( main ) (main : component1 480i, RGB 1080p)
- Set is activated HEAT run without signal generator in this Adjustment ad 00 20 00000000000000000000000007c007b006dx
mode. data ( main ) (main : component1 480i, RGB 1080p)
- Single color pattern ( WHITE ) of HEAT RUN MODE uses ad 00 30 000000070000000000000000007c00830077x
6. Confirm ad 00 99 NG 03 00x (Failed condition)
to check panel.
Adjustment NG 03 01x (Failed condition)
- Caution : If you turn on a still screen more than 20 NG 03 02x (Failed condition)
minutes (Especially digital pattern, cross hatch OK 03 03x (Success condition)
pattern), an after image may be occur in the 7. End of ad 00 90 d 00 OK90x
black level part of the screen. Adjustment

(1) Adjustment of RGB

3. PCB assembly adjustment 1) Convert to PC in Input-source.
2) Signal equipment displays
method Output Voltage: 700 mVp-p
Caution: Using ‘power on’ button of the control R/C power on Impress Resolution FHD (1920 x 1080 @ 60Hz)
TV. Model : 225 in Pattern Generator
Pattern : 65 in Pattern Generator
(MSPG-925 SERISE)
3-1. Download MAC Address,
CI+ Key and widevine Key.
* Connect TV SET and PC which download keys Writing
program by RS232C-Cable

(1) Start Program and Click ‘start’ Button to connect TV and

PC.
(2) When download succeed, you can see “OK” on the
screen. 3) Adjust by commanding AUTO_COLOR_ADJUST

Copyright ©2011 LG Electronics Inc. All rights reserved. -6- LGE Internal Use Only
Only for training and service purposes
 (2) COMPONENT input ADC
V Convert to Component in Input-source.
V Signal equipment displays
Impress Resolution 480i
MODEL: 209 in Pattern Generator(480i Mode)
PATTERN : 65 in Pattern Generator
(MSPG-925 SERISE)
Impress Resolution 1080i
MODEL: 225 in Pattern Generator(1080P Mode)
PATTERN: 65 in Pattern Generator
(MSPG-925 SERISE)

3-3. DFT Process.

* Depend on situation, Step can be changed. 3-4. Insert Tool OPTION
and Model Name download.
No STEP (1) Press IN_START key on R/C to insert Tool OPTION
1 DFT Mode-In (2) On the “ Tool Option ”, Insert Tool Option by a number key
2 Tool Option Write (3) Press the ENTER(V)
(4) Press ENTER(V) again.
3 AREA Option Write (5) Select “OK to Download” by using F/G(VOL +/-) and press
4 [RF]RF CHECK G(VOL +)
5 [RF]<DTV>EYE Model Name PZ950S/G PZ750S/G PZ570S/G
6 [COMP1]Color Test Tool Option 1 50 INCH 32777 32793 32809
7 [RGB]Color Test 60 INCH 32781 32797 32813
8 Version Check Tool Option 2 50 INCH 65 130 195
9 Wireless Check 60 INCH 65 130 195
10 Motion Check Tool option 3 19807 19807 19807
11 CI Card detect Check Tool option 4 8016 8016 8016
12 CI Key Check Tool option 5 14921 14921 14920
13 EDID Write Tool option 6 857 857 857
14 [AV2]Color Test
15 KEY1 Test
16 KEY2 Test
3-5. EDID(The Extended Display
17 [HDMI1]Color Test
Identification Data) download
18 [HDMI2]Color Test
19 [HDMI3]Color Test (1) Press the ADJ KEY on R/C and enter EZ ADJUST.
20 [HDMI4]Color Test (2) Select “5.EDID D/L” by using D / E (CH +/-) and press
ENTER(V).
21 [TV]USB2 Audio Test
(3) Select “Start” and press navigation key(G).
22 SPDIF OUT Audio Test (4) EDID download is executed automatically.
23 [AV1]Color Test (5) Press EXIT key on R/C

24 [TV]<AV1-OUT>Color Test * Caution

25 [AV1]Scart_RGB Color Test - Never connect HDMI & D-sub Cable when the user
download EDID .
26 [TV]USB1 Audio Test
27 LAN Port Check
28 3D Check

Copyright ©2011 LG Electronics Inc. All rights reserved. -7- LGE Internal Use Only
Only for training and service purposes
* EDID DATA 4-2. Download Serial number (RS-232C)
V Press “Power on” key of service R/C.
(1) RGB
(Baud rate : 115200 bps)
V Connect RS232 Signal Cable to RS-232 Jack.
V Write Serial number by use RS-232.
V Must check the serial number at the Diagnostics of SET UP
menu.
(Refer to below ‘6.SET INFORMATION’).

4-3. Adjustment of White Balance

(2) HDMI Required Equipment
O Remote controller for adjustment
O Color Analyzer ( CS-1000, CA-100,100+,CA-210 or same
produc: CH 10 (PDP)
* Please adjust CA-210, CA-100+ by CS-1000 before
measuring
O Auto W/B adjustment instrument(only for Auto adjustment)
O 9 Pin D-Sub Jack(RS232C) is connected to the AUTO W/B
EQUIPMENT.

Before Adjust of White Balance, Please press POWER ONLY

key
Adjust Process will start by execute RS232C Command.
O Color temperature standards according to CSM and Module

CSM PLASMA
3-6. Confirmation
(1) Press ‘InStart’ Key on Factory SVC Remote Controller. Cool 11000K
And MUST check ADC & EDID ADJ status is OK. Medium 9300K
Warm 6500K

O CS-1000/CA-100+/CA-210(CH 10) White balance

4. SET assembly adjustment method adjustment coordinates and color temperature.
* Caution : Each PCB assembly must be checked by check JIG
Color Coordinate
set. (Because power PCB Assembly damages to PDP CSM Temp ±Color Coordinate
Module, especially be careful) x y
Cool 0.276 0.283 11000K 0.002
4-1.POWER PCB Assembly Voltage Medium 0.285 0.293 9300K 0.002
adjustment (Va/Vs Voltage Adjustment) Warm 0.313 0.329 6500K 0.002

Test equipment : D.M.M 1EA * Manual W/B process (using adjusts Remote control)
Connection Diagram for Measuring : refer to fig.4 Please Adjust in AV 1 MODE, Turn off Energy Saving Mode.
Adjustment method (1) Enter ‘PICTURE RESET’ on Picture Mode, then turn off
Fresh Contrast and Fresh colour in Advanced Control
(1) Va adjustment (2) After enter Service Mode by pushing “ADJ” key,
1) Connect + terminal of D. M.M. to Va pin of P811, (3) Enter White Pattern off of service mode, and change off ->
connect -terminal to GND pin of P811. on.
2) After turning VR901,voltage of D.M.M adjustment as (4) Enter “W/B ADJUST” by pushing “ G ” key at “3. W/B
same as Va voltage which on label of panel right/top ADJUST”.
(deviation; ±0.5V)
(2) Vs adjustment * Gain Max Value is 192. So, Never make any Gain Value over
1) Connect + terminal of D. M..M. to Vs pin of P811, 192 and please fix one Value on 192, between R, G and B.
connect -terminal to GND pin of P811.
2) After turning VR951, voltage of D.M.M adjustment as Min Tpy Max
same as Vs voltage which on label of panel right/top (
R-GAIN 0 192 192
deviation ; ±0.5V)
G-GAIN 0 192 192
B-GAIN 0 192 192

Copyright ©2011 LG Electronics Inc. All rights reserved. -8- LGE Internal Use Only
Only for training and service purposes
* Auto-control interface and directions 4-6. Checking the EYE-Q Operation.
(1) Adjust in the place where the influx of light like floodlight (1) Press the EYE Key on the adjustment remote controller.
around is blocked. (Illumination is less than 10ux). (2) Check the Sensor DATA ( It must be under 10) and keep
(2) Measure and adjust after sticking the Color Analyzer (CA- the data longer than 1.5s
100+, CA210 ) to the side of the module. (3) Check ‘OK’
(3) Aging time
After aging start, keep the Power on (no suspension of
power supply) and heat-run over 5 minutes

4-4. Serial number download & Model (Sensor DATA 0 ~ 4095, Power Saving Mode 0 ~ 12)
name D/L and Check Tool Option. * IF you press IN-STAP Button, change Green Eye-check OSD.
(1) Press "Power on" button of a service R/C.(Baud rate :
115200 bps)
(2) Connect RS232-C Signal Cable and start ‘Option Check 4-7. Ping TEST
Program Ver3.8’ * This test is to check Network operation.
(3) Scan serial Number and press ‘F5’ button.
(4) Check ‘OK’ on program (1) program.
(5) Press ‘In start’ button on SVC R/C, check Serial Number
and Model Name.

(1) Equipment Setting

1) Play the LAN Port Test PROGRAM.
2) Input IP set up for an inspection to Test
*IP Number : 12.12.2.2

(2) LAN PORT inspection (PING TEST)

* In this case Network setting is on Manual Setting.
1) Play the LAN Port Test Program.
2) connect each other LAN Port Jack.
3) Play Test (F9) button and confirm OK Message.
4) remove LAN CABLE

4-5. Check Tool Option and write Country

Group & Area Code(Option) D/L
Model Name PZ950S/G PZ750S/G PZ570S/G
Tool Option 1 50 INCH 32777 32793 32809
60 INCH 32781 32797 32813
Tool Option 2 50 INCH 65 130 195
(3) Check Wireless function.
60 INCH 65 130 195 1) Connect set and Dongle of Wireless to Cable of HDMI &
Tool option 3 19807 19807 19807 TTA 20Pin
2) At OSD of SET, check the message like Fig 3.
Tool option 4 8016 8016 8016 3) Detach Cable of Wireless Dongle
Tool option 5 14921 14921 14920
Tool option 6 857 857 857
Area option / Code 0 0 0

Copyright ©2011 LG Electronics Inc. All rights reserved. -9- LGE Internal Use Only
Only for training and service purposes
4-8. Magic Motion Remote Controller test (1) On 3D Mode, Check the picture like below.
Required Equipment
- RF Remote Controller for test, IR-KEY-Code Remote
Controller for test
* You must confirm the battery power of Remote Controller
before test
(Recommend that change the battery per every lot)

(1) If you select the ‘start key(Mute)’ on the controller, you can
pairing with the TV SET.
(2) You can check the cursor on the TV Screen, when select
the ‘OK Key’ on the controller (2) If RF Emitter is correctly working, you can see that the
(3) You must remove the pairing with the TV Set by select lamp of RF tester turns on.
‘Vol+(STOP) Key’ on the controller

4-9. 3D Function Test

Required Equipment
O Pattern Generator : MSHG-600, MSPG-6100 [SUPPORT
HDMI1.4])
MODE : HDMI mode NO. 872
Pattern No.83

(1) Please input 3D test pattern like below (HDMI mode NO.
872 , pattern No.83)
5. Set Information
(Serial No & Model name)
5-1. Check the serial number
& Model Name
(1) Push the menu button in DTV mode.
(2) Check the Serial Number
Select the STATION -> Diagnostics -> To set

(2) When 3D OSD appear automatically, then press OK button

on ADJ Remote Controller.
(3) Check the picture. The picture must be same as below.
(Don’t have to wear 3D glasses.) 6. SW Download Guide.
* Put a *.bin to USB Stick and Turn on TV

(1) Put the USB Stick to the USB socket

(2) Automatically detecting update file in USB Stick
* If your downloaded program version in USB Stick is Low,
it didn’t work.
But your downloaded version is High, USB data is
automatically detecting.
(3) Show the message “Copying files from memory”
(4) Updating is staring.
(5) Updating Completed, The TV will restart automatically.
After turn on TV, Please press ‘IN-STOP’ button on ADJ
Remote-control.
4-10. Check RF Emitter. * IF you don’t have ADJ R/C, enter ‘Factory Reset’ in
OPTION MENU.
Required Equipment
(6) When TV turn on, check the Updated version on
- Pattern Generator : 3D-GT002, MSHG-600,
Diagnostics MENU.
MSPG-6100 [SUPPORT HDMI1.4])
MODE : HDMI mode NO. 872
Pattern No.83

Copyright ©2011 LG Electronics Inc. All rights reserved. - 10 - LGE Internal Use Only
Only for training and service purposes
 BLOCK DIAGRAM

Copyright ©2011 LG Electronics Inc. All rights reserved. - 11 - LGE Internal Use Only
Only for training and service purposes
 EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

400
601
604

520
240

910
602
209
200

590
208

900
206
201
580

205

501
303
301

204
207

A13
202

203

A10
300

302

304

LV1

A12
120
560

A21

A4
A2
305

540
570

- 12 - LGE Internal Use Only

 Strap Setting
NAND FLASH MEMORY
+3.3V_Normal
8Gbit Boot ROM Device Select - (FA4,FAD7,FAD2,FAD1)
+3.3V_Normal
IC102 IC102-*1 +3.3V_Normal
K9F8G08U0M-PCB0 TC58DVG3S0ETA00 0000: ST Micro M25P or compatible Serial Flash
0010: 8-bit 512Mbit 512B page SLC NAND Flash devices
R154 R157 R160 R164 R167 R170 R175 R177 R179 R181 R183 R187 R192
0100: 8-bit 128, 256Mbit 512B page SLC NAND Flash devices 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
R113 R117 R122 R127 0110: 8-bit 1Gbit 2KB page SLC NAND Flash devices OPT OPT OPT OPT OPT OPT OPT OPT OPT OPT
NC_1 NC_29 NC_1 NC_28 10K 10K 10K 10K 1000: 8-bit 2Gbit, 4Gbit, 8Gbit 2KB page SLC NAND Flash devices
1 48 1 48 OPT OPT
TOSIBA-NAND 1010: 8-bit 16Gbit, 32Gbit 4KB page SLC NAND Flash devices (O)
NC_2 SS-NAND NC_28 NC_2 NC_27 CI_ADDR[4] 0001:
2.7K

2 47 8-bit 8/16/32Gbit 2KB page MLC NAND Flash devices

2 47 NAND_DATA[7]0011: 8-bit 16/32Gbit 4KB page MLC NAND Flash devices NAND_DATA[0]
NC_3 NC_27 NC_3 NC_26 CI_ADDR[7]
3 46 3 46 NAND_DATA[2]0101: 8-bit 32Gbit 8KB page MLC NAND Flash devices
NAND_DATA[0-7] 0111: 3B dual IO Serial Flash NAND_DATA[6]
NC_4 NC_26 NC_4 NC_25 NAND_DATA[1]1001: BB dual IO Serial Flash
4 45 4 45 R114 R118 R123 R128 CI_ADDR[6]
R107

10K 10K 10K 10K 1011: fast Serail Flash > 50Mhz
NC_5 I/O7 NC_5 I/O8 1100: OneNAND Flash (always 16-bit) NAND_CLE
5 44 NAND_DATA[7] 5 44 OPT OPT
Open Drain OPT 1110: Reserved NAND_DATA[4]
0 NC_6 I/O6 NC_6 I/O7 1101, 1111: Reserved
R133 6 43 NAND_DATA[6] 6 43 CI_ADDR[9]
R/B I/O5 RY/BY I/O6 CI_ADDR[11]
NAND_RBb 7 42 NAND_DATA[5] 7 42
CI_ADDR[12]
RE I/O4 RE I/O5
NAND_REb 8 41 NAND_DATA[4] 8 41 CI_ADDR[13]
CE NC_25 CE NC_24 CI_ADDR[8]
NAND_CEb 9 40 9 40
OPT OPT NAND ECC (FA3, FA2, FALE) NAND_DATA[3]
NC_7 NC_24 0 NC_7 PSL
NAND_CEb2 R149 0 10 39 R148 10 39 NAND_DATA[5]
4700pF NC_8 NC_23 NC_8 NC_23 +3.3V_Normal R155 R158 R161 R165 R168 R171 R176 R178 R180 R182 R184 R188 R193
C102 11 38 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
11 38
OPT OPT OPT
C101 VCC_1 VCC_2 +3.3V_Normal VCC_1 VCC_2
12 37 12 37
0.1uF VSS_1 VSS_2
C104 10uF VSS_1 VSS_2 R111 R115 R119
13 36 13 36 10K 10K 10K
10V OPT 000 = ECC disabled
NC_9 NC_22 NC_9 NC_22 OPT
14 35 CI_ADDR[3] 001 = ECC 1-bit repair
C103 14 35 010 = ECC 4-bit BCH (O)
NC_10 NC_21 0.1uF NC_10 NC_21 CI_ADDR[2] 011 = ECC 8-bit BCH, 27 byte spare
15 34 15 34 NAND_DATA[0]:
NAND_ALE 100 = ECC 12-bit BCH, 27 byte spare 0: System is LITTLE endian (O) CI_ADDR[9],CI_ADDR[11],CI_ADDR[12],CI_ADDR[13]
CLE NC_20 CLE NC_20 101 = ECC 8-bit BCH, 16 byte spare TVM Crystal oscillator bias/gain control
NAND_CLE 16 33 16 33 R112 R116 R120 1: System is BIG endian
10K 10K 10K 110, 111 = Reservedd 0000: 210uA
ALE I/O3 ALE I/O4 OPT 0001: 390uA
NAND_ALE 17 32 NAND_DATA[3] 17 32 CI_ADDR[7]:
0: Disable EDID automatic Downloading from Flash (O) 0010: 570uA
WE I/O2 WE I/O3 0011: 730uA
NAND_WEb 18 31 NAND_DATA[2] 18 31 1: Enable EDID automatic Downloading from Flash
0100: 890uA (O)
+3.3V_Normal WP I/O1 WP I/O2 0111: 1290uA
Write Protection 19 30 NAND_DATA[1] 19 30 NAND_DATA[6] :
0: Disable OSC clock output on chip Pin (O) 1000: 1416uA
NC_11 I/O0 NC_11 I/O1 1111: 2196uA
- High : Normal Operation 20 29 NAND_DATA[0] 20 29 1: Enable OSC clock output on chip pin.
R103
4.7K

- Low : Write Protection 0101, 0110, 1001, 1010, 1011, 1100, 1101, 1110: Reserved
OPT

NC_12 NC_19 NC_12 NC_19

21 28 21 28 CI_ADDR[6]:
0: Host MIPS run at 500 MHz (O) CI_ADDR[8]:
NC_13 NC_18 NC_13 NC_18 0: RESETOUTb (in On/Off only) stay asserted until software releases them.
22 27 22 27 1: Host MIPS run at 250 MHz
FLASH_WP 1: Fix amount of delay for de-assertion on RESETOUTb (in On/IOff only)
NC_14 NC_17 NC_14 NC_17 at end of RESETb pulse (O)
23 26 23 26 NAND_CLE:
0: Differential Oscillators TVM not bypassed (O)
NC_15 NC_16 NC_15 NC_16 NAND_DATA[3]:
24 25 24 25 1: Differential Oscillators TVM bypassed
0: MIPS will boot from external flash (O)
NAND_DATA[4]: 1: MIPS will boot from ROM
0: 27MHz TVM Crystal Frequency
1: 54MHz TVM Crystal Frequency (O) NAND_DATA[5]:
0: FLASH MODE
1: BSC_SLAVE(BBS) MODE (O)

+3.3V_Normal

R198
NVRAM FOR ATMEL_EEPROM
IC103-*1
AT24C256C-SSHL-T

10K A0
RGB_DDC_SDA VCC
1 8
+3.3V_Normal
S
B
D

A1 WP
2 7
+3.3V_Normal
A2 SCL
IC101 Q100 IC101
3 6
G

LGE35230(BCM35230KFSBG) BSS83
LGE35230(BCM35230KFSBG) GND SDA
R197

4 5
FOR ST_EEPROM
C118 NAND_DATA[0-7] C116

4.7K

4.7K
IC103

OPT
R173

R174
NON_BCM_CAP 0.1uF 0.1uF
M24M01-HRMN6TP
B5 AE27 16V NON_BCM_CAP
HDMI_CLK- HDMI0_CLKN TXA0N AG6 AB1 NAND_DATA[7]
TXOUT0_L0N
22

C5 AE28 54MHz_XTAL_P TVM_XTALIN FAD_7 FOR ATMEL_EEPROM

HDMI_CLK+ HDMI0_CLKP TXOUT0_L0P TXA0P AB3 NAND_DATA[6] R199 0 NC VCC
AF27 FAD_6 1 8 Write Protection
TXA1N AF6 AC1 NAND_DATA[5]
TXOUT0_L1N 54MHz_XTAL_N TVM_XTALOUT FAD_5
A4 AF28 AC2
HDMI_RX0- HDMI0_D0N TXOUT0_L1P TXA1P NAND_DATA[4] R169 0 E1 WP - Low : Normal Operation
B4 AG27 FAD_4 2 7
HDMI_RX0+ TXA2N +3.3V_Normal AC3 NAND_DATA[3] A8’h - High : Write Protection
HDMI0_D0P TXOUT0_L2N FAD_3
AG28 V5 AD2
TXOUT0_L2P TXA2P NAND_DATA[2] E2 SCL
LNB_INT IRRXDA FAD_2 3 6 R190 33
A3 AE26 AD3 SCL3_3.3V

4.7K
HDMI_RX1- HDMI0_D1N TXCLK_LN TXACLKN NAND_DATA[1]

OPT
R172
B3 AF26 FAD_1
+3.3V_Normal HDMI_RX1+ HDMI0_D1P TXCLK_LP TXACLKP R196 AE2 NAND_DATA[0] VSS SDA
FAD_0 4 5 R191 33
AH27 10K AB4 SDA3_3.3V
TXOUT0_L3N TXA3N RGB_DDC_SCL
A2 AG26 FP_IN0 C117
S
B
D

Y4 C115
HDMI_RX2- HDMI0_D2N TXOUT0_L3P TXA3P 8pF
B2 AF25 FP_IN1 8pF
R105 R104 AG1
R195

R102 HDMI_RX2+ HDMI0_D2P TXOUT0_L4N TXA4N NAND_ALE OPT OPT

4.7K 4.7K AE25 FALE
4.7K TXA4P AA4 AF1
TXOUT0_L4P SPARE_ADC1 FCEB_0 NAND_CEb
Q101 Y5 AC5
G

BSS83 SPARE_ADC2 FCEB_1 NAND_CEb2

W2 AE6
CEC FCEB_2 /CI_CE1
AH26
22

C119 AB2 AG5

TXOUT0_U0N TXB0N SC_ID /CI_CE2
V4 AG25 0.1uF FS_IN1 FCEB_3
TXB0P AB5
DDC0_SCL TXOUT0_U0P 16V FS_IN2
W4 AE24
DDC0_SDA TXOUT0_U1N TXB1N
AD24 AF3
TXOUT0_U1P TXB1P FLASH_WP
NFWPB
+5V_MAIN
V3
V2
HDMI0_HTPLG_IN TXOUT0_U2N
AH25
AF24
TXB2N U3
VGA_SDA FWE
AG2
NAND_WEb
54MHz X-TAL
+3.3V_Normal U2 AE3
HDMI0_HTPLG_OUT TXOUT0_U2P
TXCLK_UN
AE23
TXB2P
TXBCLKN
BBS CONNECT VGA_SCL FRD
AA5
NAND_REb
C113
SUNNY
X101
D13 AD23 FRDYB /PCM_WAIT 12pF 54MHz
HDMI_ARC HDMI0_ARC TXCLK_UP TXBCLKP 54MHz_XTAL_N
R101 E6 AG24
4.7K TXB3N Y2
HDMI0_RESREF TXOUT0_U3N R121 R126 R129 R131 BCM_RX RDA 3 2
AF23 Y1 AF2 X-TAL_2 GND_1
TXOUT0_U3P TXB3P +3.3V_Normal 2.2K 2.2K 2K 2K CI_ADDR[2-14] R189
R106 AC22 DEBUG BCM_TX TDA FA_0 NAND_CLE 1M
3K TXB4N AE1 4 1 OPT
TXOUT0_U4N P101 FA_1 NAND_RBb GND_2 X-TAL_1
AD22 33 AA3 AC4
TXOUT0_U4P TXB4P SDA0_3.3V R135 CI_ADDR[2]
TJC2508-4A BSCDATAA FA_2
R136 33 AA2 AD5 CI_ADDR[3]
SCL0_3.3V BSCCLKA FA_3 KDS 54MHz_XTAL_P
AD4 CI_ADDR[4] C114 X101-*1
AG23 FA_4 12pF 54MHz
VCC R137 33 H3 AE4 CI_ADDR[5]
TXOUT1_L0N SCL2_3.3V RDB/GPIO FA_5 X-TAL_1 GND_2
AH23 1 C106 R109 R110 H2 AE5 1 4
TXOUT1_L0P 4.7uF 1.5K 1.5K R138 33 CI_ADDR[6]
AE22 SDA2_3.3V TDB/GPIO FA_6
AD6 GND_1 X-TAL_2
TXOUT1_L1N CI_ADDR[7] 2 3
AE21 SCL FA_7
2 H4 AH3 CI_ADDR[8]
TXOUT1_L1P BSC_S_SCL FA_8
AF22 H5 AF4
TXOUT1_L2N CI_ADDR[9]
AH22 OPT BSC_S_SDA FA_9
OPT OPT OPT AH4
TXOUT1_L2P SDA +3.3V_Normal CI_ADDR[10]
AG22 3 C110 FA_10
C107 C108 C109 AG4 CI_ADDR[11]
TXCLK1_LN 33pF FA_11
AF21 33pF 33pF 33pF
TXCLK1_LP 50V 50V R141 4.7K F25 NMIB
AF5 CI_ADDR[12]
AG21 GND 5V_HDMI_1 50V 50V FA_12 +3.3V_Normal
TXOUT1_L3N 4 AG3 CI_ADDR[13]
AF20 FA_13
5V_HDMI_2 W5 AH2 CI_ADDR[14]
TXOUT1_L3P PCM_5V_CTL POWER_CTRL FA_14
AD21 AH5
TXOUT1_L4N FA_15
AC21 U5
TXOUT1_L4P 5V_HDMI_3 R142 22 OPT R146 10K
R147 R150 R153 R156 R159 R162 R166
AON_HSYNC 1K 1K 1K 1K 1K 1K 1K
R143 22 OPT U4 STRAP_PCI
5V_HDMI_4 AON_VSYNC
AD15
AG20 TRSTB TP122
R144 22 OPT W3 AF14
TXOUT1_U0N AON_GPIO_36 TDI/GPIO TP123
AH20 W1 AH14
TXOUT1_U0P R130 R145 22 OPT
AD19 AON_GPIO_37 TDO TP124
2K AD14
TXOUT1_U1N +3.3V_Normal TMS/GPIO TP118
AE19 AB6 AG14
TXOUT1_U1P AON_RESETOUTB TCK/GPIO TP119
AF19 Y6 AC16
TXOUT1_U2N FOR HDMI STANDARD R132 4.7K
AH19 TVM_BYPASS DINT/GPIO TP120
TXOUT1_U2P APPLY ONLY WHEN CONNECT TO PULL-UP GPIO OPT
AE18 R139 0 TP121
TXCLK1_UN JRST TP125
AD18 Y3 AH7
TXCLK1_UP +3.3V_Normal JRST
AG19 SOC_RESET RESETB AVS_VFB
G24 AG7 R163
TXOUT1_U3N RESETOUTB AVS_VSENSE 1K
AF18 AD7
TXOUT1_U3P R124 AVS_RESETB
AG18 1K J6 AF7
TXOUT1_U4N TMODE AVS_NDRIVE_1
AF17 OPT W6 AH8
TXOUT1_U4P TESTEN AVS_PDRIVE_1
R125 +3.3V_Normal
1K
AC18 F7 C6
LT0VCAL_MONITOR C111 0.01uF DTV/MNT_V_OUT
AH16 VDAC_VREG VDAC_1
E7 D7
GPIO_BL_ON C112 0.1uF VDAC_RBIAS VDAC_2
AG16
BL_PWM/GPIO R140
560
BCM REFRENCE is 562ohm 1%

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX63525101
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN & NAND FLASH 1 19

Copyright © 2011 LG Electronics Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 +0.9V_CORE POWER 2.5V
+2.5V_BCM35230 ADAC_AVDD25 CORE 0.9V
+2.5V_BCM35230 AADC_AVDD25
C233 C204 +0.9V_CORE HDMI_AVDD +0.9V_CORE USB_AVDD +0.9V_CORE VAFE2_DVDD
6.3V
NFM18PS105R0J NFM18PS105R0J
+3.3V_Normal L202 L205
BLM18PG121SN1D BLM18PG121SN1D L209 L214 L219
C247 BLM18PG121SN1D BLM18PG121SN1D BLM18PG121SN1D
IN OUT IN OUT 22uF
10V
GND GND C249 C253 C256 C258 C202
DDR_1333

10uF 10uF 0.1uF 0.1uF C274 C280 C284 C285 C288 C292 C296 C299 390pF
16V 16V C261 C263 C267 C271 22uF 0.1uF 22uF 4.7uF 0.1uF 22uF 4.7uF 0.1uF 50V
NVR_1M

10uF 4.7uF 0.1uF 0.01uF 10V 16V 10V 10V 16V 10V 10V 16V READY
R250

R251

R201

R224

R254

R255

R256

R257

16V
OPT

OPT

FHD

MHP
1K

1K

1K

1K

1K

1K
T2

1K

1K
S

+3.3V_Normal
MODEL_OPT_0 C244
6.3V
NFM18PS105R0J +2.5V_BCM35230 EPHY_VDD25 +2.5V_BCM35230
MODEL_OPT_1 +0.9V_CORE PLL_AUD_AVDD +0.9V_CORE VAFE3_DVDD +0.9V_CORE PLL_MAIN_AVDD
C232 C234 C236 C238 IN C248 L203
OUT BLM18PG121SN1D L210 L215 L217
MODEL_OPT_2 4.7uF 0.1uF 0.1uF 4.7uF 10uF BLM18PG121SN1D BLM18PG121SN1D BLM18PG121SN1D
GND
MODEL_OPT_3 C251 C252 C255 C259 C260 C262 C266 C270 C272
0.1uF 4.7uF 0.1uF 10uF 4.7uF 10uF 4.7uF 0.1uF 0.01uF C277 C281 C294 C297
16V 16V 6.3V 10V 6.3V 10V 16V 50V 4.7uF 0.1uF C287 C290 C2006
MODEL_OPT_4 390pF 4.7uF 0.1uF
4.7uF 0.1uF
+0.9V_CORE 16V 50V
MODEL_OPT_5 *NOTE 20
Close to BCM IC
MODEL_OPT_6
NVR_256K

DDR_1600

NOT_MHP

MODEL_OPT_7 C225 +2.5V_BCM35230 VAFE3_VDD25

NON_T2

C221 C223 +2.5V_BCM35230 VAFE2_VDD25

NON_S

0.22uF +0.9V_CORE PLL_MIPS_AVDD

0.1uF 0.01uF
R260

R261

R219

R229

R264

R265

R266

R267

L204
R286 0 6.3V L206 +0.9V_CORE PLL_VAFE_AVDD
BLM18PG121SN1D
1K

1K

1K
HD

1K

1K

1K

1K

1K

MODEL_OPT_0 RF_BOOSTER_CTL BLM18PG121SN1D L211 L218

R285 0 BLM18PG121SN1D BLM18PG121SN1D
C254 C257 C2007
MODEL_OPT_1 LG8300_RESET C250
4.7uF 0.1uF 390pF C200
R220 0 4.7uF 16V C265 C269
50V 4.7uF 0.1uF 390pF C295 C298
MODEL_OPT_2 /CI_CD2 10V 16V 50V C279 C282 C2009
*NOTE 20 READY 390pF 4.7uF 0.1uF
R230 0 +1.5V_DDR Close to BCM IC 4.7uF 0.1uF
MODEL_OPT_3 REMOTE_SW_CTRL 50V
*NOTE 20
Close to BCM IC
MODEL OPTION C203 C205 C207 C209 C211 C213 C215 C220 C222
BCM 10uF 10uF 4.7uF 4.7uF 0.1uF 0.1uF 0.01uF 0.1uF 0.01uF +2.5V_BCM35230
external PLL_VAFE_AVDD25
NO_FRC internal LG FRC2
URSA5
FRC L207
BLM18PG121SN1D
MODEL_OPT_0 0 0 1 1
C264 C268 C2008 POWER 3.3V
MODEL_OPT_1 0 1 0 1 390pF
4.7uF 0.1uF
16V 50V +3.3V_Normal USB_AVDD33 +3.3V_Normal HDMI_AVDD33
*NOTE 20 L212 L216
HIGH LOW Close to BCM IC BLM18PG121SN1D BLM18PG121SN1D

MODEL_OPT_4 DDR speed 1333 1600 IC101 C283

C291 C293
+0.9V_CORE 0.1uF
close to soc
LGE35230(BCM35230KFSBG) 16V 4.7uF 0.1uF
MODEL_OPT_5 T2 Tuner Support Not Support IC101
C217
H_NIM

MODEL_OPT_6 S Tuner Support Not Support

LGE35230(BCM35230KFSBG) 16V H_NIM NON_BCM_CAP
0.1uF 100
R246 +3.3V_Normal V12 K10
MODEL_OPT_7 PHM Enable Disable IF_P_MAIN VDDC_1 VSS_1
V7 K11
H_NIM

H_NIM

NON_BCM_CAP R212 H_NIM L201 VDDC_2 VSS_2

F26 C17 1K C218 M10 K12
EPHY_VREF VI_IFP0 100 BLM18PG121SN1D +3.3V_Normal VDAC_AVDD33
D26 B17 0.1uF R245 VDDC_3 VSS_3
16V N10 L12
EPHY_RDAC VI_IFM0 IF_N_MAIN VDDC_4 VSS_4 L213
R211 D15 P10 M12
6.04K VDDR_AGC VDDC_5 VSS_5 BLM18PG121SN1D
F27 R10 N12
EPHY_TDP EPHY_TDP closed to soc C229 VDDC_6
F28 B16 VSS_6
0.1uF T10 P12
EPHY_TDN EPHY_TDN AGC_SDM_2 H_NIM VDDC_7 VSS_7 C286 C289
E27 A16 R213 2K U10 R12
EPHY_RDP EPHY_RDP AGC_SDM_1 IF_AGC_MAIN VDDC_8 VSS_8 4.7uF 0.1uF
E26 C216 0.01uF V10 T12 16V
EPHY_RDN EPHY_RDN H_NIM VDDC_9 VSS_9
A15 W10 U12
GPIO_0 VDDC_10 VSS_10
C16 +3.3V_Normal V13 W12
GPIO_1 VDDC_11 VSS_11
F5 G28 L11 K13
USB_MONCDR GPIO_2 VDDC_12 VSS_12
E5 G26 M11 L13
C201 USB_RREF GPIO_3 VDDC_13 VSS_13
R210 +3.3V_Normal R233 R234 N11 M13
100pF 4.87K 1.2K 1.2K VDDC_14 VSS_14
1% C2 P11 N13
OPT USB_DM2 USB_PORT1DN R231 33 VDDC_15 VSS_15
USB_DP2
D1 W14 SDA1_3.3V R11 P13 IC101
USB_PORT1DP PCI_VIO_0 R232 33 VDDC_16 VSS_16
W15 SCL1_3.3V T11 R13 LGE35230(BCM35230KFSBG)
PCI_VIO_1 VDDC_17 VSS_17
E1 W13 C227 C231 U11 T13
/USB_OCD2 USB_PWRFLT_1/GPIO PCI_VIO_2 VDDC_18 VSS_18 AADC_AVDD25
D2 33pF 33pF V11 U13 NON_BCM_CAP
USB_CTL2 USB_PWRON_1/GPIO 50V 50V VDDC_19 VSS_19
W11 W16 F19 F20
B1 J5 OPT OPT VDDC_20 VSS_20 ADAC_AVDD25 AADC_AVDD25 AADC_AVSS
V14 K14
USB_DM1 USB_PORT2DN GPIO_4 REMOTE_OR_MODULE_RX VDDC_21 VSS_21
C1 R5 R280 22 L18 L14 D25 G22
USB_DP1 USB_PORT2DP GPIO_5 MODEL_OPT_0 VDDC_22 VSS_22 ADACA_AVDD25 ADACA_AVSS
V6 M18 M14 D24 G21
GPIO_6 CI_DET VDDC_23 VSS_23 ADACC_AVDD25 ADACC_AVSS
C3 H6 R240 100 N18 N14 E24 F22
/USB_OCD1 USB_PWRFLT_2/GPIO GPIO_7 M_RFModule_RESET VDDC_24 VSS_24 ADACD_AVDD25 ADACD_AVSS
C4 AE15 P18 P14 EPHY_VDD25
USB_CTL1 USB_PWRON_2/GPIO GPIO_70 EPHY_ACTIVITY VDDC_25 VSS_25
AF15 R18 R14 F24 F23
GPIO_71 EPHY_LINK VDDC_26 VSS_26 EPHY_BVDD25 EPHY_AVSS
PCM_TS_DATA[0-7] AG15 R214 22 T18 T14 E25
GPIO_72 DTV_ATV_SELECT VDDC_27 VSS_27 EPHY_AVDD25
M4 AF16 R215 22 U18 U14
PCM_TS_CLK TCLKA/GPIO GPIO_73 OPT /CI_CD1
L5 AD16 VDDC_28 VSS_28
PCM_TS_DATA[0] R216 22 V18 K15 HDMI_AVDD
TDATA_0/GPIO GPIO_74 MODEL_OPT_1 VDDC_29 VSS_29
PCM_TS_DATA[1] M5 AE16 R241 22 OPT W18 L15
TDATA_1/GPIO GPIO_75 /CI_CD2 VDDC_30 VSS_30 HDMI_AVDD33
PCM_TS_DATA[2] L6 AG17 R242 22 V15 M15 D5 F6
TDATA_2/GPIO GPIO_76 REMOTE_SW_CTRL VDDC_31 VSS_31 HDMI0_AVDD HDMI0_AVSS_1
PCM_TS_DATA[3] N3 AH17 R243 22 L19 N15 D4 G6
TDATA_3/GPIO GPIO_77 L/R_INDICATOR VDDC_32 VSS_32 +2.5V_BCM35230 HDMI0_AVDD33 HDMI0_AVSS_2
PCM_TS_DATA[4] N1 AE17 R244 22 M19 P15
TDATA_4/GPIO GPIO_78 OPT VDDC_33 VSS_33
PCM_TS_DATA[5] N2 AD17 R228 22 N19 R15 AE20 AB22
TDATA_5/GPIO GPIO_79 OPT VDDC_34 VSS_34 LT0VDD25_1 LT0VSS_1
PCM_TS_DATA[6] M3 P19 T15 AD20 AB21
C2005 C2001 C2002 TDATA_6/GPIO VDDC_35 VSS_35 LT0VDD25_2 LT0VSS_2
PCM_TS_DATA[7] M2 R19 U15 AC20 AB19
TDATA_7/GPIO VDDC_36 VSS_36 +2.5V_BCM35230 LT0VDD25_3 LT0VSS_3
L4 AB13 T19 K16 AB20 AC19
PCM_TS_SYNC TSTRTA/GPIO PCI_AD05 VDDC_37 VSS_37 LT0VDD25_4 LT0VSS_4
N4 AC15 U19 L16 AB18
OPT OPT OPT PCM_TS_VAL TVLDA/GPIO PCI_AD06 VDDC_38 VSS_38 LT0VSS_5
AB12 V19 M16 AB17
FE_TS_DATA[0-7] TS_CLK PCI_AD07 C275
K6 AB11 VDDC_39 VSS_39 LT0VSS_6
W19 N16 0.1uF AC17
F/NIM TCLKD/GPIO PCI_AD08 1. COMP_DET + COMP_AV_DET = COMPONENT VDDC_40 VSS_40 OPT LT0VSS_7
FE_TS_DATA[0] R202 0 J4 AE14 2. COMP_DET ONLY = AV V16 P16
TDATD_0/GPIO PCI_AD09/GPIO SC/COMP2_DET VDDC_41 VSS_41
F/NIM K5 AG13 +1.5V_DDR V17 R16 D14 F15
FE_TS_DATA[1] R203 0 COMP_AV_DET USB_AVDD SPDIF_IN_AVDD25
F/NIM TDATD_1/GPIO PCI_AD10/GPIO VDDC_42 VSS_42
FE_TS_DATA[2] R204 0 J2 AH13 Place Cap T16 SPDIF_IN_AVSS
TDATD_2/GPIO PCI_AD11/GPIO AMP_RESET_N L200
VSS_43 USB_AVDD33
FE_TS_DATA[3] R205F/NIM0 J3 AF13 R217 0 OPT MLG1005S22NJT Very close L10
to L22 Ball U16 E4 G7
TDATD_3/GPIO PCI_AD12/GPIO POR_VDD VSS_44 USB_AVDD USB_AVSS_1
FE_TS_DATA[4] R206F/NIM0 K2 AE13
AV2_SIDE_CVBS_DET
K17 VDAC_AVDD33 D3 G8
TDATD_4/GPIO PCI_AD13/GPIO VSS_45 USB_AVDD33 USB_AVSS_2
FE_TS_DATA[5] R207F/NIM0 K1 AD12 R218 22 C206 C208 L17
TDATD_5/GPIO PCI_AD14/GPIO 1uF 0.1uF VSS_46
FE_TS_DATA[6] R208F/NIM0 K3 AF12
DSUB_DET
10V 16V
READY READY
L22 M17 VAFE2_DVDD D6 G9
TDATD_6/GPIO PCI_AD15/GPIO VDDR1_1 VSS_47 VDAC_AVDD33 VDAC_AVSS
FE_TS_DATA[7] R209F/NIM0 L1 AG10
PCM_RST
AA28 N17 VAFE2_VDD25
TDATD_7/GPIO PCI_AD16/GPIO VDDR1_2 VSS_48
L3 AF10 V28 P17 D18 G20
TS_SYNC TSTRTD/GPIO PCI_AD17/GPIO MODEL_OPT_4 VDDR1_3 VSS_49 VAFE2_DVDD VAFE2_VSS_1
L2 AE10 R28 R17 E17 E18
TS_VAL TVLDD/GPIO PCI_AD18/GPIO DC_MREMOTE VDDR1_4 VSS_50 VAFE2_AVDD25_1 VAFE2_VSS_2
AD10 M28 T17 D16 G18
PCI_AD19/GPIO DD_MREMOTE VDDR1_5 VSS_51 VAFE2_AVDD25_2 VAFE2_VSS_3
AE9 R221 0 OPT J28 U17 D17 G17
PCI_AD20/GPIO VDDR1_6 VSS_52 VAFE3_DVDD VAFE2_DVDD25 VAFE2_VSS_4
PCM_MDI[0-7] P4 AE8 R222 0 OPT K23 W17 F18
PCM_MICLK MPEG_CLK/GPIO PCI_AD21/GPIO VDDR1_7 VSS_53 VAFE2_VSS_5
T2 AC10 M22 K18 VAFE3_VDD25 D9 G16
PCM_MDI[0]
MPEG_D_0/GPIO PCI_AD22 VDDR1_8 VSS_54 VAFE3_DVDD VAFE2_VSS_6
PCM_MDI[1] R3 AC11 T22 K19 D8 F16
MPEG_D_1/GPIO PCI_AD23 VDDR1_9 VSS_55 VAFE3_AVDD25_1 VAFE2_VSS_7
PCM_MDI[2] R2 AC8 T23 H7 E8
MPEG_D_2/GPIO PCI_AD24 VDDR1_10 VSS_56 VAFE3_AVDD25_2
PCM_MDI[3] P3 AB8 very close U22 G14 F9 G13
MPEG_D_3/GPIO PCI_AD25 to SOC R22 pin VDDR1_11 VSS_57 VAFE3_AVDD25_3 VAFE3_VSS_1
PCM_MDI[4] P2 Y22 AB16 E9 G12
MPEG_D_4/GPIO VDDR1_12 VSS_58 VAFE3_DVDD25 VAFE3_VSS_2
PCM_MDI[5] P1 AC14 C242 R7 F8 F12
MPEG_D_5/GPIO PCI_CBE00 0.1uF VSS_59 POR_VDD25 VAFE3_VSS_3
PCM_MDI[6] R6 AG12 R22 M6 PLL_AUD_AVDD G11
MPEG_D_6/GPIO PCI_CBE01/GPIO COMP_DET DDR_LDO_VDDO VSS_60 VAFE3_VSS_4
PCM_MDI[7] N5 AH10 R283 22 AB23 G10
MPEG_D_7/GPIO PCI_CBE02/GPIO MODEL_OPT_5 VSS_61 PLL_MAIN_AVDD VAFE3_VSS_5
T4 AB7 +3.3V_Normal P7 G25 F10
PCM_MISYNC MPEG_SYNC/GPIO PCI_CBE03 VSS_62 PLL_AUD_AVDD VAFE3_VSS_6
P5 G15 W7 PLL_MIPS_AVDD K4
PCM_MIVAL MPEG_DATA_EN/GPIO VDDR3_1 VSS_63 PLL_MAIN_AVDD
AG11 H22 J7 PLL_VAFE_AVDD AD25
R223 22 3D_GPIO_0
PCI_DEVSELB/GPIO VDDR3_2 VSS_64 PLL_MIPS_AVDD
AD11 G23 N7 PLL_VAFE_AVDD25 D11 AD26
PCI_FRAMEB/GPIO MODEL_OPT_6 VDDR3_3 VSS_65 PLL_MIPS_AVSS
R287 0 R4 AE11 AB9 AB10 D12 PLL_VAFE_AVDD
PDP_MODEL_OPT_2 MCIF_RESET/GPIO PCI_IRDYB/GPIO MODEL_OPT_7 VDDR3_4 VSS_66 +0.9V_CORE PLL_VAFE_AVDD25
R288 0 U1 AD13 R236 0 K7 AC23
PDP_MODEL_OPT_3 MCIF_SCLK/GPIO PCI_PAR/GPIO PDP_MODEL_OPT_0 VDDR3_5 VSS_67 L208
T3 AE12 R235 0 AB15 AC6 BLM18PG121SN1D AE7 AC7
MCIF_SCTL/GPIO PCI_PERRB/GPIO PDP_MODEL_OPT_1 VDDR3_6 VSS_68 TVM_OSC_AVDD TVM_OSC_AVSS
/PCM_IRQA
T1 AC12 R225 OPT22 L7 G19 C273
MCIF_SDI/GPIO PCI_REQ1B VDDR3_7 VSS_69 C276 +3.3V_Normal
+3.3V_Normal T5 AC13 R226 OPT 22 AB14 AA22 0.1uF 0.01uF U6
MCIF_SDO/GPIO PCI_SERRB/GPIO VDDR3_8 VSS_70 AUX_AVDD33
AH11 R247 22 M7 J23 OPT
PCI_STOPB/GPIO 3D_GPIO_1 VDDR3_9 VSS_71
AF11 R227 22 N6 J22
PCI_TRDYB/GPIO 3D_GPIO_2 VDDR3_10 VSS_72
P6 K22 C278
VDDR3_11 VSS_73 0.1uF
+0.9V_CORE J25
VSS_74
MOTION

N22
R289

R290

R293

R295

VSS_75
DVR

OPT

OPT

+3.3V_Normal AA6 N23

1K

1K

1K

1K

AON_VDDC_1 VSS_76
AA7 M25
AON_VDDC_2 VSS_77
Y7 P22
PDP_MODEL_OPT_0 AON_POR_VDD VSS_78
R25
VSS_79
PDP_MODEL_OPT_1 U7 V22
HIGH LOW AON_VDDR3 VSS_80
W22
PDP_MODEL_OPT_2 VSS_81
NON_MOTION

MODEL_OPT_0 DVR READY Support Not Support T7 W23

AON_VDDR10_1 VSS_82
PDP_MODEL_OPT_3 T6 V25
NON_DVR

MODEL_OPT_1 MOTION R/C Support Not Support AON_VDDR10_2 VSS_83

AA25
R291

R292

R294

R296

MODEL_OPT_2 VSS_84
1K

1K

1K

1K

MODEL_OPT_3

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX63525101
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 2 19
MAIN POWER

Copyright © 2011 LG Electronics Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 IC101
C320 0.1uF LGE35230(BCM35230KFSBG)
DSUB_R+
Run Along DSUB_R Trace C321 0.1uF
DSUB_G+ C327 0.1uF NON_BCM_CAP
Run Along DSUB_G Trace C328 0.1uF B6 IC101
VI_R LGE35230(BCM35230KFSBG)
R311 R317 A6
36 36 VI_INCM_R
C7
VI_G NON_BCM_CAP
A7
VI_INCM_G B15 AF8
C322 0.1uF B7 SPDIF_INC_P AUD_SCK
DSUB_B+ VI_B I2SSCK_OUTA/GPIO
C8 C15 AF9
Run Along DSUB_B Trace C323 0.1uF +3.3V_Normal SPDIF_INC_N I2SWS_OUTA/GPIO AUD_LRCK +3.3V_Normal
VI_INCM_B AG9
R312 I2SSD_OUTA0/GPIO AUD_LRCH
36 C13 C14 AC9
DSUB_HSYNC SPDIF_IND_P I2SSOSCK_OUTA/GPIO AUD_MASTER_CLK
HSYNC_IN B14 AD8
A13 SPDIF_IND_N
DSUB_VSYNC VSYNC_IN I2SSD_OUTA1/GPIO
R301 R302 AD9 R300 R304
2.2K 2.2K I2SSD_OUTA2/GPIO 1.2K 1.2K
C9 REMOTE_OR_MODULE_TX G4
COMP_Y/AV1_CVBS C329 0.1uF I2SSCK_IN/GPIO
VI_Y1 R308 33 F4 E2 R307 33
C330 0.1uF A9 SCL3_3.3V I2SWS_IN
COMP_Pr VI_PR1 I2SSCK_OUTC/GPIO MOD_SCL
B9 OPT OPT R309 33 G5 F2 R326 33 OPT OPT
Run Along COMP_Y_IN,COMP_Pr_IN,COMP_Pb_IN Trace COMP_Pb C331 0.1uF SDA3_3.3V I2SSD_IN/GPIO I2SWS_OUTC/GPIO MOD_SDA
VI_PB1 E3
C332 0.1uF B8 C301 C302 TU_RESET C300 C317
VI_INCM_COMP1 I2SSD_OUTC/GPIO
33pF 33pF F3 33pF 33pF
50V 50V I2SSOSCK_OUTC/GPIO 50V 50V
C11 C305 1uF 10V C25
SC_R/COMP2_Pr C333 0.1uF PC_L_IN AADC_LINE_L1
VI_SC_R1 B24 G2
C334 0.1uF A10 PC_R_IN C306 1uF 10V
AADC_LINE_R1 SC_RE1
SC_G/COMP2_Y VI_SC_G1 I2SSCK_OUTD/GPIO
B10 C307 1uF 10V A24 G3
SC_B/COMP2_Pb C335 0.1uF INCM_AUD_PC AADC_INCM1 I2SWS_OUTD/GPIO SC_RE2
VI_SC_B1 G1
C336 0.1uF C10
Run Along SC R,G,B Trace VI_INCM_SC1 I2SSD_OUTD/GPIO
C308 1uF 10V E22 H1
R310 R318 AV2_SIDE_L_IN AADC_LINE_L2 I2SSOSCK_OUTD/GPIO S2_RESET
0 0 D10 C309 1uF 10V E23
SC_FB AV2_SIDE_R_IN AADC_LINE_R2
VI_FB_1/GPIO D23
F13 INCM_AUD_SIDE_AV C310 1uF 10V
AADC_INCM2
VI_FS1 B13
SPDIF_OUTA/GPIO SPDIF_OUT
A12 C311 1uF 10V C24
COMP_L_IN AADC_LINE_L3
VI_SC_R2 C23 AG8
C12 COMP_R_IN C312 1uF 10V
VI_SC_G2 AADC_LINE_R3 AUDMUTE_0/GPIO
B12 C313 1uF 10V B23 E13
INCM_AUD_COMP AADC_INCM3 AUDMUTE_1
VI_SC_B2
B11
VI_INCM_SC2 BCM35230_with_CAP_220pF E21 C28
SC/COMP2_L_IN C314 1uF 10V
IC101-*1
AADC_LINE_L4 ADAC_AL_N
E12 LGE35230 C315 1uF 10V D21 C27
SC/COMP2_R_IN AADC_LINE_R4 ADAC_AL_P
VI_FB_2/GPIO D22
E14 BCM_CAP
INCM_AUD_SC C316 1uF 10V
VI_FS2
U26
DDR_DQA_0 DDR_ADA_0
V23
AADC_INCM4
R26
U27
DDR_DQA_1 DDR_ADA_1
AB27
Y23
D28
R27
DDR_DQA_2 DDR_ADA_2
Y26 ADAC_AR_N
E15 V27
DDR_DQA_3
DDR_DQA_4
DDR_ADA_3
B22 D27
VI_L1
P26
DDR_DQA_5 DDR_ADA_4
AB26
AADC_LINE_L5 ADAC_AR_P
F17
U25
P27
DDR_DQA_6 DDR_ADA_5
Y24
AC26
C22
VI_C1_1 R24
DDR_DQA_7 DDR_ADA_6
AADC_LINE_R5
E16 N24
DDR_DQA_8
DDR_DQA_9 DDR_ADA_ALT_4
AB24 A22 C26
C337 0.1uF
T25 AC25
AADC_INCM5 ADAC_CL_N SCART_Lout_N
SC_CVBS_IN VI_INCM_LC1_1 M23
DDR_DQA_10 DDR_ADA_ALT_5
AC24
A27
F14 R23
DDR_DQA_11 DDR_ADA_ALT_6
SCART_Lout_P
C338 0.1uF VI_C1_2 N25
DDR_DQA_12
AB25 ADAC_CL_P
Run Along SC_CVBS Trace E11 T24
DDR_DQA_13
DDR_DQA_14
DDR_ADA_7
DDR_ADA_8
AD28 F21
VI_INCM_LC1_2
N26
DDR_DQA_15 DDR_ADA_9
Y25
AADC_LINE_L6
AV2_SIDE_CVBS_IN C303 0.1uF L26
H27
DDR_DQA_16 DDR_ADA_10
AA27
AC27
D20 B27
L27
DDR_DQA_17 DDR_ADA_11
AA26 AADC_LINE_R6 ADAC_CR_N SCART_Rout_N
Run Along SIDE_CVBS Trace C304 0.1uF C18 J26
DDR_DQA_18
DDR_DQA_19
DDR_ADA_12
DDR_ADA_13
AA24 E20 B28
M27 AD27
AADC_INCM6 ADAC_CR_P SCART_Rout_P
VI_CVBS1 G27
DDR_DQA_20 DDR_ADA_14

C325 0.1uF B18 M26

DDR_DQA_21
DDR_DQA_22 DDR_BAA_0
Y27

TU_CVBS VI_INCM_CVBS1 H26

L23
DDR_DQA_23 DDR_BAA_1
AB28
W24 A21 B25
Run Along TUNER_CVBS Trace C326 0.1uF A18 DDR_DQA_24 DDR_BAA_2
AADC_LINE_L7
VI_CVBS2
H25
DDR_DQA_25 ADAC_DL_N
C21 A25
OPT

L24 V24
R306 R325 R303 R316 C19 J24
DDR_DQA_26 DDR_RASA_N
W25

75 36 36 VI_INCM_CVBS2 M24
DDR_DQA_27 DDR_CASA_N
V26 AADC_LINE_R7 ADAC_DL_P
1% 36 A19 H23
DDR_DQA_28
DDR_DQA_29
DDR_WEA_N
B21
VI_CVBS3
L25
DDR_DQA_30 DDR_CKEA
U24
AADC_INCM7
B19
H24
DDR_DQA_31
W27
A26
NON_EU VI_INCM_CVBS3
DDR_CKA01_P
W28 ADAC_DR_N
C20 T26
DDR_DMA_0
DDR_CKA01_N
B26
COMP_Y/AV1_CVBS C340 0.1uF P25 N28
ADAC_DR_P
VI_CVBS4 J27
DDR_DMA_1 DDR_CKA23_P
N27

C339 0.1uF B20 K24

DDR_DMA_2
DDR_DMA_3
DDR_CKA23_N

VI_INCM_CVBS4 DDR_VREFA
U23

NON_EU T27
DDR_DQSA_P_0 DDR_RST_N
AA23
T28
E19 DDR_DQSA_N_0
DDR_ZQ
W26

VI_SIF1_1 P24
P23
DDR_DQSA_P_1
D19 DDR_DQSA_N_1

VI_INCM_SIF1_1 K27
E10 K28
DDR_DQSA_P_2
DDR_DQSA_N_2
VI_SIF1_2 K25
F11 K26
DDR_DQSA_P_3

VI_INCM_SIF1_2 DDR_DQSA_N_3

+2.5V_BCM35230

R313
10K
C319 0.1uF
AUDIO INCM
TU_SIF
R305 R314
240 12K

Route Between SIDE_AV_L_IN & SIDE_AV_R_IN Trace

Near JK800 R321 5.1 INCM_AUD_SIDE_AV
+2.5V_BCM35230 Route Between SC_L_IN & SC_R_IN Trace
Near JK900 R322 5.1 INCM_AUD_SC

R319 R323 5.1 Route Between COMP_L_IN & COMP_R_IN Trace

10K Near JK803 INCM_AUD_COMP
Route Along With TUNER_SIF_IF_N OPT
Route Between PC_L_IN & PC_R_IN Trace
C324 0.1uF Near JK801 R324 5.1 INCM_AUD_PC
R315 R320
120 12K
OPT OPT

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX63525101
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN AUDIO/VIDEO 3 19

Copyright © 2011 LG Electronics Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 DDR STRAP DDR_DQ[0]
DDR_DQ[1]
DDR_DQ[2]
DDR_DQ[3]
DDR_DQ[4]
+1.5V_DDR +1.5V_DDR

C410 C432
JEDEC Types : DDR_DQ[0:4] 6.3V
NFM18PS105R0J 6.3V
NFM18PS105R0J
R401 R403 R405 R407 R409
4.7K 4.7K 4.7K 4.7K 4.7K 00001 : DDR3-1333H (CasL=9)(O)
OPT 10101 : DDR3-1600K (CasL=11) C403 C405 C407 C417 C421 C423 C425
IN OUT IN OUT
4.7uF 10uF 10uF 470pF 4.7uF 10uF 10uF
GND GND
+1.5V_DDR

DDR_DQ[10]
DDR_DQ[9]
+1.5V_DDR +1.5V_DDR
DDR_DQ[7]
C402 C433
DDR_DQ[8] C453 C454 C455 6.3V
NFM18PS105R0J 6.3V
NFM18PS105R0J
DDR_DQ[6] 1uF 1uF 1uF
6.3V 6.3V 6.3V
DDR_DQ[5] IN OUT C412 IN OUT C426
1uF 1uF
GND GND

R402 R432 R404 R406 R408 R410

4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
OPT OPT HYNIX_DDR OPT OPT
Bus Width : DDR_DQ[10]
0 - 16b
1 - 32b (O)
DDR_DQ[9] DDR_DQ[7] Maker Chip Width : DDR_DQ[8]
0 - 8b
1 1 SS 1 - 16b (O)
Chip Size : DDR_DQ[6:5]
1 0 Hynix 00 - 4Gbit
01 - 2Gbit (O) +1.5V_DDR
0 1 Reserve 10 - 1Gbit +1.5V_DDR
+1.5V_DDR
11 - 512Mbit
0 0 Reserve IC401 IC402
R422 R430
K4B2G1646C R416
4.99K
K4B2G1646C 4.99K 4.7K
1% 1% R429 OPT
82
DDR_RESETb
N3 M8 N3 M8 R423
DDR_AA0 A0 C415 R417 DDR_AA0 A0 VREFCA C435 4.99K C442
IC101 VREFCA 4.99K P7
P7 0.01uF 1% DDR_AA1 A1
0.01uF 1% 100pF
LGE35230(BCM35230KFSBG) DDR_AA1 A1 P3
P3 DDR_AA2 A2
DDR_AA2 A2 N2 H1 R428
DDR_DQ[0-7] N2 H1 DDR_AA3 A3 DDR_VREFA 82
NON_BCM_CAP DDR_AA3 A3 VREFDQ DDR_VREFA VREFDQ C436
P8 C416 P8 DDR_CKE
DDR01_AA4 0.01uF DDR23_AA4 A4 0.01uF C437 R431
U26 V23 A4 P2
DDR_DQ[0] DDR_DQA_0 DDR_AA0 P2 DDR23_AA5 100pF 4.7K
DDR_ADA_0 DDR01_AA5 A5 A5 OPT
DDR_DQ[1] R26 AB27 R8 L8 R8 L8 R421 240
DDR_DQA_1 DDR_ADA_1 DDR_AA1 DDR01_AA6 R415 240 DDR23_AA6 A6 ZQ
U27 Y23 A6 ZQ R2
DDR_DQ[2] DDR_AA2 R2 1% +1.5V_DDR DDR_AA7 1% +1.5V_DDR
DDR_DQA_2 DDR_ADA_2 DDR_AA7 A7 A7
DDR_DQ[3] R27 Y26 T8 T8
DDR_DQA_3 DDR_ADA_3 DDR_AA3 DDR_AA8 DDR_AA8 A8
V27 A8 R3 B2
DDR_DQ[4] R3 B2 DDR_AA9 DDR_AA13 R424 56
DDR_DQA_4 DDR_AA9 A9 VDD_1 A9 VDD_1
DDR_DQ[5] P26 AB26 L7 D9 L7 D9 R425 56 OPT
DDR_DQA_5 DDR_ADA_4 DDR01_AA4 DDR_AA10 DDR_AA10 A10/AP VDD_2 DDR_AA14
U25 Y24 A10/AP VDD_2 R7 G7 C438 1uF
DDR_DQ[8-15] DDR_DQ[6] DDR01_AA5 R7 G7 DDR_AA11
DDR_DQA_6 DDR_ADA_5 DDR_AA11 A11 VDD_3 A11 VDD_3
DDR_DQ[7] P27 AC26 N7 K2 N7 K2 AR401 56
DDR_DQA_7 DDR_ADA_6 DDR01_AA6 DDR_AA12 DDR_AA12 A12/BC VDD_4 DDR_AA2
R24 A12/BC VDD_4 T3 K8 C400 0.1uF
DDR_DQ[8] T3 K8 DDR_AA13 DDR_AA11
DDR_DQA_8 DDR_AA13 A13 VDD_5 A13 VDD_5
DDR_DQ[9] N24 AB24 N1 N1
DDR_DQA_9 DDR_ADA_ALT_4 DDR23_AA4 VDD_6 DDR_AA3
T25 AC25 VDD_6 M7 N9 C404 0.1uF
DDR_DQ[10] DDR23_AA5 M7 N9 DDR_AA7
DDR_DQA_10 DDR_ADA_ALT_5 NC_5 VDD_7 NC_5 VDD_7
DDR_DQ[11] M23 AC24 R1 R1 AR402 56
DDR_DQA_11 DDR_ADA_ALT_6 DDR23_AA6 VDD_8
R23 VDD_8 M2 R9
DDR_DQ[12] M2 R9 DDR_BAA0 DDR_AA9
DDR_DQA_12 DDR_BAA0 BA0 VDD_9 BA0 VDD_9
DDR_DQ[13] N25 AB25 N8 N8 C450 0.1uF
DDR_DQA_13 DDR_ADA_7 DDR_AA7 DDR_BAA1 DDR_BAA1 BA1 DDR_AA8
T24 AD28 BA1 M3 C406 0.1uF
DDR_DQ[16-23] DDR_DQ[14] DDR_AA8 M3 DDR_BAA2 DDR_AA0
DDR_DQA_14 DDR_ADA_8 DDR_BAA2 BA2 BA2
DDR_DQ[15] N26 Y25 A1 A1 AR403 56
DDR_DQA_15 DDR_ADA_9 DDR_AA9 VDDQ_1 DDR_AA1
L26 AA27 VDDQ_1 J7 A8 C439 1uF
DDR_DQ[16] DDR_AA10 J7 A8 DDR23_CLK DDR_BAA0
DDR_DQA_16 DDR_ADA_10 DDR01_CLK CK VDDQ_2 CK VDDQ_2
DDR_DQ[17] H27 AC27 K7 C1 K7 C1
DDR_DQA_17 DDR_ADA_11 DDR_AA11 DDR01_CLKb DDR23_CLKb CK VDDQ_3 DDR_BAA2
L27 AA26 CK VDDQ_3 K9 C9 C408 0.1uF
DDR_DQ[18] DDR_AA12 K9 C9 DDR_CKE DDR_BAA1
DDR_DQA_18 DDR_ADA_12 DDR_CKE CKE VDDQ_4 R418 R419 CKE VDDQ_4
DDR_DQ[19] J26 AA24 R412 R413 D2 56 56 D2 AR404 56
DDR_DQA_19 DDR_ADA_13 DDR_AA13 56 56 1% 1% VDDQ_5 DDR_AA10
M27 AD27 1% 1% VDDQ_5 +1.5V_DDR L2 E9 C451 0.1uF
DDR_DQ[20] DDR_AA14 +1.5V_DDR L2 E9 DDR_AA12
DDR_DQA_20 DDR_ADA_14 CS VDDQ_6 CS VDDQ_6
DDR_DQ[21] G27 K1 F1 R420 10K K1 F1
DDR_DQA_21 C401 R414 10K ODT
C419 ODT VDDQ_7 DDR_WEb
M26 Y27 VDDQ_7 J3 H2 C409 0.1uF
DDR_DQ[24-31] DDR_DQ[22] DDR_BAA0 1000pF J3 H2 1000pF DDR_RASb
DDR_DQA_22 DDR_BAA_0 DDR_RASb RAS VDDQ_8 RAS VDDQ_8
DDR_DQ[23] H26 AB28 K3 H9 K3 H9 AR405 56
DDR_DQA_23 DDR_BAA_1 DDR_BAA1 DDR_CASb DDR_CASb CAS VDDQ_9 DDR23_AA6
L23 W24 CAS VDDQ_9 L3 C440 1uF
DDR_DQ[24] DDR_BAA2 L3 DDR_WEb DDR23_AA4
DDR_DQA_24 DDR_BAA_2 DDR_WEb WE WE
DDR_DQ[25] H25 J1 J1
DDR_DQA_25 NC_1 DDR23_AA5
L24 V24 NC_1 T2 J9
DDR_DQ[26] DDR_RASb T2 J9 DDR_RESETb
DDR_DQA_26 DDR_RASA_N DDR_RESETb RESET NC_2 RESET NC_2
DDR_DQ[27] J24 W25 L1 L1 AR406 56 C452 0.1uF
DDR_DQA_27 DDR_CASA_N DDR_CASb NC_3 DDR01_AA6
M24 V26 NC_3 L9
DDR_DQ[28] DDR_WEb L9 DDR01_AA4
DDR_DQA_28 DDR_WEA_N NC_4 NC_4
DDR_DQ[29] H23 F3 T7 F3 T7
DDR_DQA_29 DDR_QS0 DQSL DDR_AA14 DDR_QS2 DQSL NC_6 DDR_AA14 DDR01_AA5
L25 U24 NC_6 G3
DDR_DQ[30] DDR_CKE G3 DDR_QS2b
DDR_DQA_30 DDR_CKEA DDR_QS0b DQSL DQSL R426 56
DDR_DQ[31] H24 DDR_CASb
DDR_DQA_31 R427 56 C441 1uF
W27 C7 A9 C7 A9 DDR_RASb
DDR_DM[0-3] DDR_CKA01_P DDR01_CLK DDR_QS1 DDR_QS3 DQSU VSS_1
W28 DQSU VSS_1 B7 B3
DDR01_CLKb B7 B3 DDR_QS3b
DDR_CKA01_N DDR_QS1b DQSU VSS_2 DQSU VSS_2
DDR_DM[0] T26 E1 E1
DDR_DMA_0 VSS_3 VSS_3
DDR_DM[1] P25 N28 E7 G8 E7 G8
DDR_DMA_1 DDR_CKA23_P DDR23_CLK DDR_DM[0] DML DDR_DM[2] DML VSS_4
J27 N27 VSS_4 D3 J2
DDR_DM[2] DDR23_CLKb D3 J2 DDR_DQ[16-23] DDR_DM[3]
DDR_DMA_2 DDR_CKA23_N DDR_DQ[0-7] DDR_DM[1] DMU VSS_5 DMU VSS_5
DDR_DM[3] K24 J8 J8
DDR_DMA_3 VSS_6 VSS_6
U23 E3 M1 DDR_DQ[16] E3 M1
DDR_VREFA DDR_VREFA DDR_DQ[0] DQL0 VSS_7
DQL0 VSS_7 F7 M9
DDR_DQ[1] F7 M9 DDR_DQ[17]
DQL1
DQL1 VSS_8 VSS_8
T27 AA23 F2 P1 DDR_DQ[18] F2 P1
DDR_QS0 DDR_DQSA_P_0 DDR_RST_N DDR_RESETb DDR_DQ[2] DQL2 VSS_9
T28 DQL2 VSS_9 F8 P9
DDR_QS0b DDR_DQ[3] F8 P9 DDR_DQ[19]
DQL3
DDR_DQSA_N_0 DQL3 VSS_10 VSS_10
W26 R411 240 H3 T1 DDR_DQ[20] H3 T1
DDR_ZQ DDR_DQ[4] DQL4 VSS_11
P24 DQL4 VSS_11 H8 T9
DDR_QS1 1% DDR_DQ[5] H8 T9 DDR_DQ[21]
DDR_DQSA_P_1 DQL5 VSS_12 DQL5 VSS_12
P23 G2 DDR_DQ[22] G2
DDR_QS1b DDR_DQSA_N_1 DDR_DQ[6] DQL6
DQL6 H7
DDR_DQ[7] H7 DDR_DQ[24-31] DDR_DQ[23]
DQL7
K27 DDR_DQ[8-15] DQL7 B1
DDR_QS2 DDR_DQSA_P_2 B1 VSSQ_1
K28 VSSQ_1 D7 B9
DDR_QS2b DDR_DQ[8] D7 B9 DDR_DQ[24]
DQU0
DDR_DQSA_N_2 DQU0 VSSQ_2 VSSQ_2
C3 D1 DDR_DQ[30] C3 D1
DDR_DQ[14] DQU1 VSSQ_3
K25 DQU1 VSSQ_3 C8 D8
DDR_QS3 DDR_DQ[13] C8 D8 DDR_DQ[29]
DQU2
DDR_DQSA_P_3 DQU2 VSSQ_4 VSSQ_4
K26 C2 E2 DDR_DQ[28] C2 E2
DDR_QS3b DDR_DQSA_N_3 DDR_DQ[12] DQU3 VSSQ_5
DQU3 VSSQ_5 A7 E8
DDR_DQ[9] A7 E8 DDR_DQ[25]
DQU4
DQU4 VSSQ_6 VSSQ_6
A2 F9 DDR_DQ[26] A2 F9
DDR_DQ[10] DQU5 VSSQ_7
DQU5 VSSQ_7 B8 G1
DDR_DQ[15] B8 G1 DDR_DQ[31]
DQU6
DQU6 VSSQ_8 VSSQ_8
A3 G9 DDR_DQ[27] A3 G9
DDR_DQ[11] DQU7 VSSQ_9
DQU7 VSSQ_9

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX63525101
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN DDR 4 19

Copyright © 2011 LG Electronics Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 +5V_MULTI Switch
P_+5V
+5V_MULTI
fr. PWR SUPPLY UNIT R538
0
2012
P_17V 1/10W
P500 C563
10uF
L502 16V
SMAW200-H18S1 MLB-201209-0120P-N2 OPT

+5V_MAIN
C522 C526
100uF 0.1uF
25V 50V R537
OPT 0
L516 P_+5V 3216
MLB-201209-0120P-N2
1 2 1/4W
C565
L503 10uF
MLB-201209-0120P-N2 16V
3 4 OPT

C523 C527 C530 C535

5 6 10uF
16V
100uF
16V
0.1uF
16V
10uF
6.3V
OPT
7 8
9 10 PSU_ERR_DET
+5V_ST C525
11 12 16V
0.1uF
OPT +5V_TU
R506 13 14 +5V_ST Max 420mA
OPT 2K
R508
100 R512 +5V_NORMAL 17V->5V Closed to Tuner
15 16 0

L518
RL_ON
+5V_ST C511 L512
0.1uF
16V
17 18 C524
10uF
C528
100uF
C531
0.1uF
C536
10uF
22.0uH
16V 16V 16V 6.3V
OPT
R507
10K IC506
OPT R509 P_17V C561
100 TPS54231D

SMAB34

R532
105K
0.1uF
19

1%
MOD_ON C581 C585 R1

D500
AC_DET 50V C577 10uF 10uF

40V
C512 10uF 16V 6.3V
0.1uF C532 BOOT PH 16V OPT
16V 0.1uF 1 8
16V

VIN GND
2 7

-->3.12V EN COMP R533

3 6 20K R2

R519
OPT 1%

16K
C549 C551 C554
10uF 4.7uF 0.01uF SS VSENSE C576
25V 50V 50V 4 2A 5
470pF
50V

R520
3.6K
C560
0.015uF C582
50V 15pF

+3.3V_Stand_By +3.3V_Normal +3.3V_TU

R529
51K
50V

TUNER L504 R518

*NOTE 13
POWER_ON/OFF_2
MLB-201209-0120P-N2 10K
OPT
+3.3V_ST
+5V_ST C539 C540 C541 C544
0.1uF
16V
22uF
16V
0.1uF
16V
0.1uF
16V
0.1uF
Vout=0.8*(1+R1/R2)
IC500 50V
R510 C558
AP2121N-3.3TRE1 0 OPT

VIN 3 2 VOUT
+1.25V_TU
+3.3V_TU
1
C502 C506 GND C510 C514 C516 POWER_ON/OFF_2
IC503
10uF
16V
0.1uF
16V
10uF
6.3V
10uF
6.3V
0.1uF
16V R552
+3.3V_NORMAL

OPT
AZ1117BH-ADJTRE1

10K
R523
OPT 120-ohm
BLM18PG121SN1D

R550
10K
INPUT 1A OUTPUT

0.1uF
3 2

C559
OPT

16V
1 C533 C546
ADJ/GND 10uF 0.1uF +5V_MULTI
C537 C538 6.3V 50V
0.1uF 10uF R1
50V 16V OPT
R542 R513
1 R545 R527
1.2K 22
OPT 0

EP[GND]
+3.3V_Normal
C594

VIN_3

PWRGD

BOOT
0.1uF
50V

EN
R2 R541 L506

+0.9V_CORE_BCM35230 10
MLB-201209-0120P-N2 L508

16

15

14

13
V0 = 1.25(1+R2/R1) VIN_1 PH_3
3.6uH
1 12
PLACE THE NEAR TO TUNER THERMAL
VIN_2 2 17 11 PH_2

GND_1 PH_1
3 IC505 10 C578
10uF
C579
10uF
C515 C529 C592 R1
C553 C550 SN1007054RTER 10uF 10uF 50V

R528
22uF 0.1uF GND_2 SS 6.3V 6.3V 6.3V 6.3V

51K
4 9 100pF C593
10V 50V

1%
0.1uF

0.01uF
16V

8
MAX 4000 mA

C595
AGND

VSENSE

COMP

RT/CLK
+0.9V_CORE
+2.5V_BCM35230 R521 R546
+5V_MAIN 13K 330K

R535
+5V_MAIN

16K
1%
L501 IC507 C557
120-ohm

IC501 2uH 3300pF R2

L500 AOZ1037PI [EP]LX AZ1085S-ADJTR/E1 Max 960mA 50V
L515

MLB-201209-0120P-N2
*NOTE 17
PGND NC *NOTE 21 Vout=Vref*(1+R1/R2)|Vref=0.827
R547

1 8 INPUT OUTPUT
5%

OPT 3 3A 2
THERMAL

R553 0 C520 C521 C518 C519 C597 C598 C596

Placed on SMD-TOP VIN PGOOD 10uF 10uF 10uF 10uF 10uF 10uF 3300pF
9

1
0
1000pF

2 7
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 50V
OPT OPT OPT C517 C589 C590 C591
ADJ/GND
C504

10uF 0.1uF
R503

AGND EN R534 0.1uF

50V

10uF
1%

3 6
C500 C503 C508 R504 16V 16V 1K
R1 6.3V 16V
2K

10uF 10uF 0.1uF 16K

16V 16V 16V
OPT
FB
4
5A 5
COMP
1%
R511

R1
+1.5V_DDR
910
1%

R554
R500

1/10W

R2
10K

1
1%

+5V_MULTI
R540
66.5

+5V_ST
R501
1%

4.7K POWER_ON/OFF_2 R2
0.1uF
C501

10K
OPT

16V

R551 OPT

V0 = 1.25(1+R2/R1) +3.3V_ST
+1.5V_DDR
R522

L519
OPT
10K

R502 S
10K

R530
Q501 C C505 RTR030P02
G
R505 2SC3052 0.47uF
Q504 IC504

0
10K B D
Switching freq: 555K POWER_ON/OFF_2 25V AZ1085S-ADJTR/E1

E INPUT 3 2 OUTPUT

1
ADJ/GND
C509 C513
R526
22uF 16V
1% 10V 0.1uF

R524
C507 1K

150
1%
10uF
10V R1
R2 R555

R525
1

75

1%
Vout=Vref*(1+R1/R2)|Vref=0.8 V0 = 1.25(1+R2/R1)

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX63525101
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER 5 19

Copyright © 2011 LG Electronics Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 SUB MICOM +3.3V_ST
+3.3V_ST
OPT
R635

IC602

R670
10K

680
AZ7029RTRE1 for Debugger

OPT
R652
OUT VCC 0 P601 +3.3V_ST
MICOM_RESET 3 OPT 1 12505WS-12A00
2:S15;11:S15 2 DEBUG
SW603 1
JTP-1127WEM GND

+3.3V_ST
2
2 1 OPT MICOM_RESET
C607 C625
0.1uF 3 R649 22
DEBUG 10uF NEC_ISP_Tx
16V 4 3 16V 4

5 R650 22 NEC_ISP_Rx
MICOM MODEL OPTION +3.3V_ST

10K

10K

10K

10K
OCD1A
8
EEPROM for Micom

950

550

OPT
9 +3.3V_ST
OCD1B

R608

R610

R612

R614
10

R651 22
11
FLMD0 IC601 PSU_ERR_DET R605 100 MODEL1_OPT_0
750/950
12
M24C16-WMN6T R606 100
FLMD0

BLUE_LED_0N MODEL1_OPT_1
13
R640 10K
R604 OPT 0 NEC
MODEL1_OPT_2
AMP_MUTE R607 100 MODEL1_OPT_3
NC/E0 VCC
GND 1 8

10K

10K

10K

10K
R687

750/550

750/950
47K C608
+3.3V_ST NC/E1 WC 0.1uF

OPT
10K

2 7

R609

R611

R613

R615
47K

C601 C602 R631 NC/E2 SCL

50V 50V MICOM_DOWNLOAD 3 6 EEPROM_SCL MODEL PWM OPTION
OPT

R629

12pF 12pF 0 33 R688

**PK50 : LED_RED
R641 10K PK70 : LED_RED/LED_WHITE
*NOTE12 VSS SDA
R627

NEC_ISP_Rx 4 5 EEPROM_SDA PK90 : LED_RED/LED_GALAXY/LED_LOGO

R642 10K 33 R689
X601 NEC_ISP_Tx
10MHz PIN NAME PIN NO. HIGH LOW
15pF

15pF

MODEL1_OPT_0 8 ATSC DVB

MODEL1_OPT_1 11 PZ550 PZ750/950

C605

C606

R625
WRLS_PWR_EN
MICOM_RESET

10K MODEL1_OPT_2 30 PZ950 PZ750/550

*NOTE9
WRLS_DET

OPT X602
MODEL1_OPT_3 31

32.768KHz
R632
10Mhz Crystal
4.7M
OPT

SUB ASSY
P122/X2/EXCLK/OCD0B

GND
+3.3V_ST

Wireless IR Buffer Lighting Logo LED

22

P120/INTP0/EXLVI

+5V_MULTI
P124/XT2/EXCLKS
0.1uF

LOGO
P121/X1/OCD0A

+3.3V_ST
R633

P602
C603 LOGO 12507WS-04L
0.1uF L608
BLM18PG121SN1D
C604

+3.3V_ST
R645
47K 1
P123/XT1

R643
22
+3.3V_ST R637 120K R655
IR_WRLS 47K 2
1/16W +3.3V_Normal LOGO
R653
FLMD0

RESET

1% C 10K R691
REGC

B 330
1/16W

OPT
R636
100K
VDD
VSS

P40
P41

E R692
Q601 R657 LOGO
4.7K
1%
R601 4.7K

2SC3052 C 47K
R603 4.7K

R669 C
LOGO
B 10K B Q605 4
E Q603 LED_LOGO 2SC3875S(ALY)
2SC3052
C617 E
10uF 5
48
47
46
45
44
43
42
41
40
39
38
37

OPT
R647
22

R616 22
P60/SCL0 1 36 P140/PCL/INTP6 OPT

SCL2_3.3V RL_ON
EDID_WP +3.3V_ST
R617 22
P61/SDA0 2 35 P00/TI000
SDA2_3.3V SCART_MUTE C
*NOTE4
EEPROM_SCL
P62/EXSCL0 3 34 P01/TI010/TO00 R639 22 B Q606 R646
+3.3V_ST
2SC3052 47K
P63 4 33 P130 R671 22 E IR_MICOM
R644
22
EEPROM_SDA
P33/TI51/TO51/INTP4 IC600 P20/ANI0
R656
47K P603
LED_LOGO 5 32 MICOM_DOWNLOAD C
R654
10K
12507WS-15L

R619 22 OPT P75 6 uPD78F0514 31 ANI1/P21 E

B +3.3V_ST
MODEL1_OPT_3 Q602 R658
2SC3052 C 47K
P74 7 30 ANI2/P22 +5V_MULTI B 1
AC_DET MODEL1_OPT_2 E Q604 C611 C622
P73/KR3 NEC ANI3/P23 R638 22
2SC3052 680pF
50V
10pF
50V
MODEL1_OPT_0 8 29 DISP_EN R660 R662 R665
2
R699

10K 10K 4.7K

P72/KR2 ANI4/P24 R648
10K

R621 22
SOC_RESET
9 28 R695 22
TOUCH_VER_CHECK
22
OPT
KEY1 3
C612
R622 22 P71/KR1 10 27 ANI5/P25 R696 10K *NOTE2
220pF
50V
C618
50V
MOD_ON 10pF
OPT 4
P70/KR0 ANI6/P26 KEY2
R698

C613
11 26
20K

+3.3V_ST 220pF C623

MODEL1_OPT_1 KEY2 50V 10pF
50V
R623 22 P32/INTP3/OCD1B 12 25 ANI7/P27 LED_RED OPT 5
OCD1B KEY1 C614 C619
OPT 10pF 10pF
50V 50V
13
14
15
16
17
18
19
20
21
22
23
24

R661 OPT 6
SUB_SCL 10K R663
OPT 10K
OPT R666
22
R602 7
4.7K SUB_SCL
C610
P31/INTP2/OCD1A
P30/INTP1
P17/TI50/TO50
P16/TOH1/INTP5
P15/TOH0
P14/RXD6
P13/TXD6
P12/SO10
P11/SL10/RXD0
P10/SCK10/TXD0
AVREF
AVSS

+3.3V_ST
10pF R667
OPT 22
SUB_SDA 8
C615
+3.3V_ST 10pF
OPT
+3.3V_Normal +5V_MULTI +3.3V_ST BLUE_LED_0N 9

10
L601 L602 +3.3V_Normal C620
550 750/950 10uF
6.3V
11
C609 1uF

R664
4.7K C624
10uF
LED_Power_On 16V 12
C616 C621
10pF 10pF
50V +3.3V_ST 50V
OPT 13
22
22

14

R697

10K
OPT

R620
R618

15
TOUCH_VER_CHECK

16
22

+3.3V_ST
0
R628

R630

R626
4.7K
HDMI_CEC

NEC_ISP_Rx

NEC_ISP_Tx

POWER_ON/OFF_2

NEC_RXD

NEC_TXD
LED_RED
LED_Power_On

IR_MICOM
OCD1A
SUB_SDA

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX63525101
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM/IR 6 19

Copyright © 2011 LG Electronics Inc. All rights reserved.

Only for training and service purposes LGE Internal Use Only
 * HDMI CEC
+3.3V_Normal +3.3V_HDMI
BODY_SHIELD
5V_HDMI_1 5V_HDMI_4 L701
BLM18PG121SN1D
SHIELD GND

20 20 +3.3V_ST C730
HP_DET HP_DET 0.1uF
HDMI_HPD_4
OPT HDMI_HPD_1 19 OPT
19 5V OPT OPT
5V R712 C734 R717
R707 C735 R722
0.1uF 1K 18 OPT 0.1uF 1K
18 GND OPT
GND OPT OPT OPT OPT R759 D714
R758 D706 17 3.6K 5.5V JP707
17 3.6K 5.5V R708 DDC_DATA
DDC_DATA 22 HDMI_4 R760
DDC_SDA_1 DDC_SDA_4 R761
16 16 R718 22
DDC_CLK JP705 DDC_CLK 27K
100K
DDC_SCL_1 15 DDC_SCL_4
15 R709 JP706 R719 22
NC NC HDMI_4 JP708
22

CDS3C05HDMI1
CDS3C05HDMI1
14
CDS3C05HDMI1
CDS3C05HDMI1

14 CE_REMOTE R779
CE_REMOTE 0 +1.8V_TU
CEC_REMOTE D715 BAT54 +3.3V_TU
CEC_REMOTE 13 HDMI_4
13 CK- 30V
CK-
CK-_HDMI1 CK-_HDMI4
12

HDMI_4

HDMI_4
12 CK_GND

D723

5.6V
CEC_REMOTE HDMI_CEC IC702

D724

5.6V
D718

5.6V

CK_GND
D717

5.6V

EAG62611201 AZ1117BH-1.8TRE1 L702

EAG59023302

AVRL161A1R1NT
11 11 BLM18PG121SN1D
CK+ 10
CK+ S B D IN ADJ/GND
10 CK+_HDMI1 CK+_HDMI4 3 1
1A

OPT
D0-

D716
D0- 9 2
9 D0-_HDMI1 D0-_HDMI4 C717 C728 C729
D0_GND D0_GND BSS83 0.1uF
16V OUT
10uF
6.3V
0.1uF
16V
8 8
D0+
Q709 R778
D0+ 7 1
7 D0+_HDMI1 D0+_HDMI4
D1- D1- G
6 6 D1-_HDMI4
D1-_HDMI1
D1_GND D1_GND
5 5
D1+ D1+
4 4 D1+_HDMI4
D1+_HDMI1
D2- D2-
3 3 D2-_HDMI4
D2-_HDMI1
D2_GND D2_GND
2 2
D2+ D2+
1 1 D2+_HDMI4
D2+_HDMI1

HDMI_4
JK703 RSD-105156-100
YKF45-7058V JK704

HDMI1 HDMI4-SIDE
+3.3V_HDMI

+5V_MULTI
+5V_MULTI
5V_HDMI_2
5V_HDMI_1

A2

A1
A2

A1

SHIELD 5V_HDMI_2
C701 C702 C704 C705 C706 C708 C709
D710 10uF 10uF 10uF
D707 0.1uF 0.1uF 0.1uF 0.1uF
20 C
10V 10V 10V 16V 16V 16V 16V HDMI1 HDMI S/W OUTPUT
HP_DET
C

D2-_HDMI1

D1+_HDMI1

CK-_HDMI1
D1-_HDMI1

D0+_HDMI1

D0-_HDMI1

CK+_HDMI1
D2+_HDMI1

HDMI_CLK-

HDMI_RX0-

HDMI_RX0+

HDMI_RX1-

HDMI_RX1+

HDMI_RX2-

HDMI_RX2+
HDMI_CLK+
HDMI_HPD_2
19 OPT
5V R703 C732 R763
0.1uF 1K R723
18 OPT OPT R715 R720
GND OPT OPT R713
R756 D712 4.7K 4.7K
4.7K 4.7K
17 3.6K 5.5V R704
DDC_DATA 22 JP703
DDC_SDA_2 DDC_SDA_2
16 DDC_SDA_1
DDC_CLK
15 DDC_SCL_2 DDC_SCL_2
NC R705 DDC_SCL_1
JP704
22
CDS3C05HDMI1

14
CDS3C05HDMI1

CE_REMOTE
CEC_REMOTE
13
CK-
CK-_HDMI2
12
CK_GND
D719

5.6V
D720

5.6V
EAG59023302

11 +5V_MULTI
CK+
10 +5V_MULTI
CK+_HDMI2 5V_HDMI_3
5V_HDMI_4
D0-
9 D0-_HDMI2
A2

A1

D0_GND
A2

A1

8
HDMI_4

TPWR_CI2CA
D0+ D708
7 D0+_HDMI2 D711
C

D1-
C

[EP]GND

VCC33_3
6 D1-_HDMI2 R777
4.7K
D1_GND

R0X2P
R0X2N
R0X1P
R0X1N
R0X0P
R0X0N
R0XCP
R0XCN
5 HDMI_4 HDMI_4

TXCN
TXCP
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
D1+ R714 R716 R721 R724
4 D1+_HDMI2 4.7K 4.7K 4.7K 4.7K
D2-
3 D2-_HDMI2 DDC_SDA_4
D2_GND DDC_SDA_3
2

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57