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MARU 220

Doppler VHF Omni-directional Radio


Range

Technical Manual

Volume I

EQUIPMENT DESCRIPTION

Copyright (C) 2005-2007

MOPIENS, Inc. www.mopiens.com


Table of Contents

Chapter 1. Introduction to the System ...................................................... 1-1


1.1. NAVAID Overview.............................................................................................. 1-1
1.1.1. Non Directional Beacon (NDB) ............................................................................. 1-1
1.1.2. Instrument Landing System (ILS) ......................................................................... 1-1
1.1.3. Distance Measuring Equipment (DME) ................................................................ 1-2
1.1.4. VHF Omni-directional Range (VOR) .................................................................... 1-2
1.1.5. Tactical Air Navigation (TACAN) ........................................................................... 1-2 1.2.
Principles of VOR ............................................................................................. 1-3
1.2.1. Principles of the Light Tower ................................................................................. 1-3
1.2.2. Conventional VOR (CVOR) .................................................................................. 1-7
1.2.3. Frequency Spectrum of VOR ................................................................................ 1-8
1.2.4. Doppler VOR (DVOR) ........................................................................................... 1-9
1.2.5. The Continuous Rotation Effect of Antenna ........................................................ 1-11
1.2.6. Comparison between CVOR and DVOR ............................................................ 1-13
1.2.7. Collocation of VOR and DME/TACAN ................................................................ 1-15
1.2.8. Use of VOR ......................................................................................................... 1-15
1.2.9. VOR Receiver ..................................................................................................... 1-16
1.2.10. VOR Course Indicator ......................................................................................... 1-17 1.3.
Related Technology and Theory ................................................................... 1-19
1.3.1. Doppler Effect ..................................................................................................... 1-19
1.3.2. Frequency Band of VOR (VHF) .......................................................................... 1-20
1.4. Characteristics of MARU 220 Doppler VOR ................................................. 1-22
1.5. MARU 220 Doppler VOR Specification ......................................................... 1-23
1.5.1. System Specification ........................................................................................... 1-23
1.5.2. Transmitter Specification .................................................................................... 1-24
1.5.3. Monitor Specification ........................................................................................... 1-25
1.5.4. Antenna Specification ......................................................................................... 1-26
1.5.5. Counterpoise Specification ................................................................................. 1-27
1.5.6. Power Supply Specification ................................................................................ 1-28 1.6.
System Configuration .................................................................................... 1-29 1.6.1.
Hardware ............................................................................................................ 1-30

Page I
System Description / Ed.01

Copyright© 2005-2007 MOPIENS, Inc. All Rights Reserved.


1.6.2. Antenna ............................................................................................................... 1-33
1.6.3. Operating Software (LMMS / RMMS) ................................................................. 1-33
1.6.4. Remote Control Unit ........................................................................................... 1-33
1.6.5. System Redundancy ........................................................................................... 1-34 1.6.6.
Slot Location and LRU Insertion ......................................................................... 1-37

Chapter 2. Sub-Systems Description ........................................................ 2-1


2.1. AES (Antenna Electronics Subsystem) .......................................................... 2-1
2.1.1. Overview ............................................................................................................... 2-1
2.1.2. Function ................................................................................................................ 2-2 2.1.3.
Interface between Units ........................................................................................ 2-3 2.2. MAS
(Modulation Amplifier Subsystem) ......................................................... 2-4
2.2.1. Overview ............................................................................................................... 2-4
2.2.2. Functions .............................................................................................................. 2-5 2.2.3.
Interface between Units ........................................................................................ 2-6 2.3. CMS
(Control & Monitor Subsystem) .............................................................. 2-7
2.3.1. Overview ............................................................................................................... 2-7
2.3.2. Functions .............................................................................................................. 2-8
2.3.3. Interfaces between Units ...................................................................................... 2-9 2.3.4.
Common Data Storage ........................................................................................ 2-11 2.4. PSS
(Power Supply Subsystem) ................................................................... 2-12
2.4.1. Overview ............................................................................................................. 2-12
2.4.2. Functions ............................................................................................................ 2-14 2.4.3.
Interfaces between Units .................................................................................... 2-15 2.5.
Others .............................................................................................................. 2-16
2.5.1. FAN ..................................................................................................................... 2-16
2.5.2. Air Baffle ............................................................................................................. 2-16

Chapter 3. Hardware Description .............................................................. 3-1


3.1. ASU .................................................................................................................... 3-1
3.1.1. Appearance of ASU .............................................................................................. 3-1
3.1.2. ASU Block Diagram .............................................................................................. 3-2
3.1.3. Major ASU Parts ................................................................................................... 3-2
3.1.4. ASU Operations .................................................................................................... 3-3
3.1.5. USB/LSB Turnover Module (TM) .......................................................................... 3-5
3.1.6. Selection Module (SM) ......................................................................................... 3-8
3.1.7. Antenna Selection Signal Decoding ..................................................................... 3-9 3.1.8.
Input Signal Timing ............................................................................................. 3-10 3.2. PDC
.................................................................................................................. 3-13

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System Description / Ed.01

3.2.1. Appearance of PDC ............................................................................................ 3-13


3.2.2. Major PDC Parts ................................................................................................. 3-15
3.2.3. PDC Operations .................................................................................................. 3-16
3.2.4. PDC-CAR ............................................................................................................ 3-17
3.2.5. PDC-SB .............................................................................................................. 3-18
3.2.6. Antenna Fault Detection Circuit .......................................................................... 3-19
3.3. CMA .................................................................................................................. 3-20
3.3.1. Appearance of CMA ........................................................................................... 3-20
3.3.2. CMA Block Diagram ............................................................................................ 3-23
3.3.3. Major CMA Parts ................................................................................................. 3-24
3.3.4. Frequency Synthesizer (SYN) ............................................................................ 3-25
3.3.5. Modulator (MOD) ................................................................................................ 3-26
3.3.6. Carrier Power Amplifier (CPA) ............................................................................ 3-28
3.3.7. Other Circuits ...................................................................................................... 3-29 3.4.
SMA .................................................................................................................. 3-30
3.4.1. Appearance of SMA ............................................................................................ 3-30
3.4.2. SMA Configuration .............................................................................................. 3-32
3.4.3. Major SMA Parts ................................................................................................. 3-33
3.4.4. Frequency Synthesizer (SYN) ............................................................................ 3-34
3.4.5. Modulator (MOD) ................................................................................................ 3-35
3.4.6. Sideband Amplifier Unit (SBA) ............................................................................ 3-36
3.4.7. Other Circuits ...................................................................................................... 3-37 3.5.
LCU .................................................................................................................. 3-38
3.5.1. Appearance of LCU ............................................................................................ 3-38
3.5.2. LCU Functions .................................................................................................... 3-39
3.5.3. Major LCU Parts ................................................................................................. 3-40
3.5.4. Microprocessor and Peripheral Circuits .............................................................. 3-40
3.5.5. Serial Communication Control ............................................................................ 3-42
3.5.6. CSP Control ........................................................................................................ 3-43
3.5.7. Generating Audible Alert and IDENT Tone Playback .......................................... 3-44
3.5.8. Sub-Processor .................................................................................................... 3-44
3.5.9. Other Functions .................................................................................................. 3-46
3.6. MON ................................................................................................................. 3-48
3.6.1. Appearance of MON ........................................................................................... 3-48
3.6.2. Interfaces between Units .................................................................................... 3-49
3.6.3. MON Overview.................................................................................................... 3-50
3.6.4. Major Parts of MON ............................................................................................ 3-52
3.6.5. Microprocessor and Peripheral Circuit ............................................................... 3-52
3.6.6. RF Signal Processing Circuit .............................................................................. 3-55
3.6.7. Reference 30 Hz Signal Processing ................................................................... 3-56

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System Description / Ed.01

3.6.8. Variable 30 Hz Signal Processing ....................................................................... 3-57


3.6.9. Measuring AM depth of 9960 Hz Sub-Carrier Signal.......................................... 3-60
3.6.10. 1020 Hz IDENT Signal Processing ..................................................................... 3-
62
3.6.11. Measuring the SYN Output Frequency ............................................................... 3-
64
3.6.12. Monitoring Status of Transmit Antenna ............................................................... 3-
65
3.6.13. Measuring Carrier Output Level.......................................................................... 3-
66
3.6.14. Interface between MONs .................................................................................... 3-
66
3.6.15. Measuring Power Supply Voltages ..................................................................... 3-
67
3.6.16. Self Test .............................................................................................................. 3-
67 3.6.17. Transmitter Changeover Control ........................................................................ 3-68
3.7. MSG .................................................................................................................. 3-71
3.7.1. Appearance of MSG ........................................................................................... 3-71
3.7.2. Features of MSG ................................................................................................ 3-72
3.7.3. Major Parts of MSG ............................................................................................ 3-73
3.7.4. Microprocessor and Peripheral Circuits .............................................................. 3-73
3.7.5. Modulation Signal Generation for Carrier Wave ................................................. 3-74
3.7.6. Modulation Signal Generation for Sideband ....................................................... 3-77
3.7.7. Switching Signal Generation for Antenna ........................................................... 3-79
3.7.8. RF Phase Control ............................................................................................... 3-83
3.7.9. Other Control and Monitor .................................................................................. 3-84 3.8.
CSU .................................................................................................................. 3-86
3.8.1. Appearance of CSU ............................................................................................ 3-86
3.8.2. CSU Overview .................................................................................................... 3-88
3.8.3. Major Parts of CSU ............................................................................................. 3-89
3.8.4. Redundancy Support Interface of Transmitter and Monitor ................................ 3-90
3.8.5. Test Signal Generator (TSG) .............................................................................. 3-91
3.8.6. Voice Signal Processing ..................................................................................... 3-92
3.8.7. Interface with the Collocated DME or TACAN .................................................... 3-93 3.9.
CSP .................................................................................................................. 3-96
3.9.1. Appearance of CSP ............................................................................................ 3-96
3.9.2. Internals of CSP .................................................................................................. 3-97
3.9.3. Major Parts of CSP ............................................................................................. 3-97
3.9.4. Circuit Description ............................................................................................... 3-97 3.10.
AC / DC Converter .......................................................................................... 3-99

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System Description / Ed.01

3.10.1. Appearance of AC/DC Converter ....................................................................... 3-


99
3.10.2. AC/DC Overview ............................................................................................... 3-
100 3.10.3. Operations ........................................................................................................ 3-100
3.11. DC / DC Converter ........................................................................................ 3-102
3.11.1. Appearance of DC/DC Converter ..................................................................... 3-
102
3.11.2. DC/DC Overview .............................................................................................. 3-
103 3.11.3. Operations ........................................................................................................ 3-103
3.12. RCMU ............................................................................................................. 3-105
3.12.1. Appearance of RCMU ....................................................................................... 3-
105
3.12.2. RCMU Overview ............................................................................................... 3-
106
3.12.3. Major Parts of RCMU ........................................................................................ 3-
107
3.12.4. 3.12.4 Processor ............................................................................................... 3-
107
3.12.5. Serial Communication Control .......................................................................... 3-
109
3.12.6. Controlling the LED Lamp, Graphic LCD and Keypad ...................................... 3-
110
3.12.7. Generating the Audible Alerts ............................................................................3 -
110
3.12.8. Power Supply Unit (SMPS) ................................................................................3 -110
3.13. RMU ................................................................................................................ 3-
111
3.13.1. Appearance of RMU .......................................................................................... 3-
111
3.13.2. Block Diagram of RMU ......................................................................................3 -
112
3.13.3. Major Parts of RMU ...........................................................................................3 -
113 3.13.4. Circuit Description
..............................................................................................3 -113

Chapter 4. Antenna ..................................................................................... 4-1


4.1. Overview ............................................................................................................ 4-1
4.2. Transmit Antenna.............................................................................................. 4-4
4.2.1. Characteristics of Alford Loop Antenna ................................................................ 4-4
4.2.2. Appearance of Transmission Antenna .................................................................. 4-6

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System Description / Ed.01

4.2.3. Electric Structure of Transmission Antenna .......................................................... 4-8 4.3.

Monitor Antenna ............................................................................................. 4-11

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System Description / Ed.01

Contents of Figures
Figure 1-1 Principles of Light Tower ........................................................................................ 1-
3
Figure 1-2 Phase Relationship between Reference and Variable Phase Signals ................... 1-
5
Figure 1-3 Radiation Pattern and Phase Relationship of CVOR ............................................. 1-
7
Figure 1-4 The Frequency Spectrum of VOR Signal ............................................................... 1-8
Figure 1-5 Frequency Deviation by Doppler Effect................................................................ 1-11
Figure 1-6 Implementing the Continuous Rotation Effect by Blending .................................. 1-12
Figure 1-7 Phase Relationship of VOR Signal ...................................................................... 1-13
Figure 1-8 Configuration of the VOR Receiver ...................................................................... 1-16
Figure 1-9 VOR Course Indicator .......................................................................................... 1-17
Figure 1-10 TO-FROM Indicator ............................................................................................ 1-
18 Figure 1-11 Doppler Effect .....................................................................................................
1-19 Figure 1-12 System Diagram
................................................................................................. 1-29
Figure 1-13 Sub-system of MARU 220 .................................................................................. 1-30
Figure 1-14 Unit Mounting Positions ..................................................................................... 1-31
Figure 1-15 Redundant Structure of Power Unit ................................................................... 1-34
Figure 1-16 Redundant Structure of the Transmitter ............................................................. 1-35
Figure 1-17 Redundant Structure of the Monitor ................................................................... 1-36
Figure 1-18 Classifying the Slots of CMS Units ..................................................................... 1-37
Figure 2-1 External View of ASU ............................................................................................. 2-
1
Figure 2-2 Location and Appearance of PDC .......................................................................... 2-
1
Figure 2-3 AES Block Diagram ................................................................................................ 2-3
Figure 2-4 Locations and Appearance of MAS LRUs .............................................................. 2-4
Figure 2-5 MAS Blocks & Interfaces ........................................................................................ 2-
6
Figure 2-6 Locations and Appearance of CMS LRUs ............................................................. 2-7
Figure 2-7 CMS Blocks & Interfaces ..................................................................................... 2-10
Figure 2-8 Locations and Appearances of PSS LRUs .......................................................... 2-13
Figure 2-9 PSS Blocks & Interfaces ...................................................................................... 2-15
Figure 2-10 Location and Appearance of FAN ...................................................................... 2-16
Figure 2-11 Location and Appearance of Air Baffle ............................................................... 2-
16
Figure 3-1 Appearance of ASU ................................................................................................ 3-
1 Figure 3-2 ASU Blocks & Interfaces ........................................................................................
3-2
Figure 3-3 Internals of ASU ..................................................................................................... 3-
3

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System Description / Ed.01

Figure 3-4 Internals of ASU-TM ............................................................................................... 3-5


Figure 3-5 Internals of SIN Path .............................................................................................. 3-6
Figure 3-6 Internals of COS Path ............................................................................................ 3-
6
Figure 3-7 Internals of ASU-SM ............................................................................................... 3-8
Figure 3-8 Antenna Selection Signal Decoding ....................................................................... 3-9
Figure 3-9 Switching Signals and Antenna Selections .......................................................... 3-10
Figure 3-10 Timings of the COS Antenna Switching Signals ................................................ 3-11
Figure 3-11 Timings of the SIN Antenna Switching Signals .................................................. 3-12
Figure 3-12 Front Panel of PDC ............................................................................................ 3-
13 Figure 3-13 PDC Back Panel ................................................................................................
3-14 Figure 3-14 PDC Internals
..................................................................................................... 3-16 Figure 3-15 PDC-CAR
Internals ............................................................................................ 3-17 Figure 3-16 Internals
of PDC-SB ........................................................................................... 3-18 Figure 3-17
Internals of Antenna Fault Detection Circuit ....................................................... 3-19
Figure 3-18 Front Panel of CMA ............................................................................................ 3-
20 Figure 3-19 Rear Panel of CMA ............................................................................................
3-21
Figure 3-20 Internal Blocks of CMA and SMA ....................................................................... 3-
23
Figure 3-21 Internals of SYN ................................................................................................. 3-25
Figure 3-22 Internals of MOD ................................................................................................ 3-26
Figure 3-23 Internals of CPA ................................................................................................. 3-28
Figure 3-24 Front Panel of SMA ............................................................................................ 3-
30
Figure 3-25 Rear Panel of SMA ............................................................................................ 3-31
Figure 3-26 Blocks and Interfaces of SMA ............................................................................ 3-32
Figure 3-27 Internals of SYN ................................................................................................. 3-34
Figure 3-28 Internals of MOD ................................................................................................ 3-35
Figure 3-29 Internals of SBA ................................................................................................. 3-36
Figure 3-30 Front Panel of LCU ............................................................................................ 3-38
Figure 3-31 Internals of LCU ................................................................................................. 3-39
Figure 3-32 LCU Microprocessor .......................................................................................... 3-40
Figure 3-33 Communication Port ........................................................................................... 3-
42
Figure 3-34 Internals of CSP Control .................................................................................... 3-43
Figure 3-35 Generating Audible Alert and IDENT Tone Playback ......................................... 3-
44
Figure 3-36 Sub-Processor Circuit ........................................................................................ 3-44
Figure 3-37 LCU Other Circuits ............................................................................................. 3-
46
Figure 3-38 Front Panel of MON ........................................................................................... 3-48
Figure 3-39 Monitor Interface ................................................................................................ 3-49
Figure 3-40 Block Diagram of MON ...................................................................................... 3-51

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System Description / Ed.01

Figure 3-41 RF Signal Processing Circuit ............................................................................. 3-55


Figure 3-42 Reference 30Hz Signal Processing ................................................................... 3-56
Figure 3-43 Steps of Variable 30Hz Signal Processing ......................................................... 3-
57
Figure 3-44 Measuring AM depth of 9960 Hz Sub-carrier signal .......................................... 3-60
Figure 3-45 Measuring AM Depth of 1020 Hz IDENT Signal ................................................ 3-62
Figure 3-46 IDENT Signal Code Decoding ............................................................................ 3-
63 Figure 3-47 Timing of Morse Code IDENT ............................................................................
3-63
Figure 3-48 Measuring the SYN Output Frequency .............................................................. 3-64
Figure 3-49 Timing Diagram for Monitoring the Status of Transmission Antenna ................. 3-
65
Figure 3-50 Front Panel of MSG ........................................................................................... 3-71
Figure 3-51 Internals of MSG ................................................................................................ 3-72
Figure 3-52 Blending Signal Waveforms ............................................................................... 3-77
Figure 3-53 COS/SIN Blending Signal .................................................................................. 3-78
Figure 3-54 Timing of Antenna Switching Signal ................................................................... 3-
80 Figure 3-55 COS Antenna Switching .....................................................................................
3-81 Figure 3-56 SIN Antenna Switching
....................................................................................... 3-82
Figure 3-57 Phasor Diagram showing RF Phase Relationship ............................................. 3-83
Figure 3-58 Font Panel of CSU ............................................................................................. 3-86
Figure 3-59 Interface Signal to DME/TACAN ........................................................................ 3-89
Figure 3-60 Control Signal Switching Block Diagram ............................................................ 3-90
Figure 3-61 Block Diagram of Test Signal Generator ............................................................ 3-
91
Figure 3-62 Block Diagram of Voice Signal Processor .......................................................... 3-92
Figure 3-63 When the Master is the Current Sink and the Slave is the Current Source ....... 3-93
Figure 3-64 When the Master is the Current Source and the Slave is the Current Sink ....... 3-93
Figure 3-65 Block Diagram of DME Interface ........................................................................ 3-
95 Figure 3-66 Appearance of CSP ............................................................................................
3-96
Figure 3-67 Internals of CSP ................................................................................................. 3-97
Figure 3-68 Front Panel of AC/DC ......................................................................................... 3-99
Figure 3-69 Internals of AC/DC Converter ........................................................................... 3-100
Figure 3-70 Front Panel of DC/DC Converter ..................................................................... 3-102
Figure 3-71 Internals of DC/DC Converter .......................................................................... 3-103
Figure 3-72 Appearance of RCMU ...................................................................................... 3-105
Figure 3-73 Block Diagram of RCMU .................................................................................. 3-106
Figure 3-74 RCMU Processor ............................................................................................. 3-108
Figure 3-75 RCMU Communication Part ............................................................................. 3-109
Figure 3-76 Appearance of RMU .......................................................................................... 3-
111
Figure 3-77 Internals of RMU .............................................................................................. 3-112

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System Description / Ed.01

Figure 4-1 DVOR Antenna System .......................................................................................... 4-


1
Figure 4-2 Antenna Arrangement on the Horizontal Plane of Counterpoise ........................... 4-
2
Figure 4-3 Vertical Radiation Pattern When h=λ/2 .................................................................. 4-4
Figure 4-4 Vertical Radiation Pattern in a Free Space ............................................................ 4-5
Figure 4-5 Horizontal Radiation Pattern .................................................................................. 4-5
Figure 4-6 Appearance of Transmission Antenna ................................................................... 4-
6 Figure 4-7 Electric Distribution of Alford Loop Antenna Radiation Elements ..........................
4-8
Figure 4-8 Matching Stub Assembly ........................................................................................ 4-9
Figure 4-9 4:1 Coaxial Cable Balun ....................................................................................... 4-10
Figure 4-10 Monitor Antenna ................................................................................................. 4-
11

Contents of Tables
Table 3-1 Test Signals Outputted from TSG ....................................................................... 3-3-
68

Abbreviations
ADC Analog to Digital Converter
AES Antenna Electronics Subsystem
AMP Amplifier
ANT Antenna
ASU Antenna Switching Unit
BIT Built In Test
BITE Built In Test Equipment
BPF Band Pass Filter
CMA Carrier Modulation Amplifier
CMS Control Monitor Subsystem
CPA Carrier Power Amplifier
CPD Carrier Power Detector
CSP Control and Status Panel
CSU Control Selection Unit
CVOR Conventional VOR
DAC Digital to Analog Converter
DET Detector
DME Distance Measuring Equipment

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System Description / Ed.01

DPDT Double-Pole Double-Throw


DVOR Doppler VOR
ENV Envelope
GUI Graphic User Interface
LCU Local Control Unit
LPF Low Pass Filter
LSB Lower Sideband
MAS Modulation Amplifier Subsystem
MOD Modulator
MISC MISCellaneous
MMIC Monolithic Microwave Integrated
Circuit
MOD Modulator
MON Monitor
MSG Modulation Signal Generator
PA Power Amplifier
PDC Power Detector &Changeover
PFC Phase Frequency Comparator
PLD Programmable Logic Device
PLL Phase Locked Loop
PSS Power Supply Subsystem
PSU Power Supply Unit
PWM Pulse-Width Modulation
RCMU Remote Control and Monitor Unit
REF CLK Reference Clock
RMU Remote Monitor Unit
SBA Sideband Amplifier Unit
SM Selection Module
SMA Sideband Modulation Amplifier
SPD Sideband Power Detector
SPI Serial Peripheral Interface
SYN Synthesizer
TACAN Tactical Air Navigation System
TCXO Temperature Compensated Crystal Oscillator
TM Toggling Module
UART Universal Asynchronous
Receiver/Transmitter
USART Universal Synchronous/Asynchronous
Receiver/Transmitter
USB Upper Sideband
VOP Voice Processor
VSWR Voltage Standing Wave Ratio

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System Description / Ed.01

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Chapter 1. Introduction to the System

Chapter 1. Introduction to the System


This chapter describes about the basic theories and concepts needed in understanding the
MARU 220 Doppler VOR system.

1.1. NAVAID Overview


The terrestrial wireless facilities in aiding navigation may be followed as below.

1.1.1. Non Directional Beacon (NDB)

NDB refers to the navigation aid facility that becomes the barometer that informs the location
and azimuth of the NDB station to an aircraft by transmitting a non-directional radio wave.

NDB has been the facility used in the air and sea for the longest time as for a simple system
Configuration. NDB is the facility for detecting the azimuth of an NDB terrestrial station
equipped with the Automatic Direction Finder (ADF) by transmitting the non-directional
radio waves in the medium/long-frequency range (200~415kHz).
The accuracy of NDB is in the range of 5~10˚.

1.1.2. Instrument Landing System (ILS)

The Instrument Landing System (ILS) guides aircrafts with directional radio waves so that
they can follow a certain course and land accurately even in the nighttime or when the
visibility is bad. ICAO adopted ILS as a standard for the precision approach support system
in 1950.

ILS consists of the following 3 facilities.  Localizer – Horizontal position of the landing
course, which is the equipment of transmitting the radio wave that indicates the centerline
of runway.
 Glide Path: Vertical position of the landing course, which is the equipment of
transmitting the radio wave that indicates the angle(2.5° ~ 3°) of approach for the
horizontal runway plane.
 Marker: As the equipment of indicating the distance from the end of runway, it consists
of the Inner Marker, Middle Marker and Outer Marker. The Inner Marker is located at
the point 75m away from the start point of runway, 1050m for the Middle Marker and
7200m for the Outer Marker.
1.1.3. Distance Measuring Equipment (DME)

The Distance Measuring Equipment (DME) is the system that provides information to the
aircraft for the slant distance between the terrestrial equipments. Generally, it is operated in
collocation with VOR.

If the DME interrogator mounted onto an aircraft transmits the pulse signal to the terrestrial
station, the DME terrestrial station receives this signal and then transmits the response signal

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Chapter 1. Introduction to the System

to the aircraft after a certain delay time (50μs). The time interval between interrogation pulse
and response pulse is proportional to the slant distance between the aircraft and the terrestrial
DME facility. The DME interrogator calculates the distance by measuring the pulse signal
exchange time.

1.1.4. VHF Omni-directional Range (VOR)

The ultra short wave VOR is the aid facility that supports aircrafts to approach an airport or
to navigate a certain course by providing the azimuth information dependent on the
terrestrial wireless stations. ICAO has adopted VOR in 1949 as the standard for the
nonprecision approach facility.

Aircraft can decide the azimuth based on the terrestrial wireless stations by receiving the
VOR signals. The azimuth is indicated on the indicator of VOR receiver that is mounted on
to the aircraft.

The frequencies used by VOR can be in the range of 108~118MHz. Although the effective
distance reachable by the VOR radio wave is generally limited to the visible range of
distance, it may depend on the surrounding environment, the location that VOR is installed,
and the altitude that the aircraft is flying.

1.1.5. Tactical Air Navigation (TACAN)

It is developed for the course directions of TACAN military aircrafts. TACAN provides the
distance and azimuth information at the same time. Since the distance-measuring signal is
identical to that of DME, civil aircrafts can use TACAN as the DME. Although TACAN can
be used as a stand-alone system, the distance measuring part of TACAN is collocated within
TACAN and VOR so that civil aircrafts can also share it.

1.2. Principles of VOR


1.2.1. Principles of the Light Tower

To aid understanding the basic principles of VOR, let’s assume tow virtual light towers of
using two lights. Let say that one of two lights, referred as “Reference Signal,” is a white
light fixed at one location and can observe all the directions around. The other is a rotating
green light that flashes the light only in one direction and the observer can see the light only
when he is at the right direction. Let’s us call it as “Variable Signal.”

1) The reference signal (white light) lights up only when the variable signal (green light)
face exactly to the magnetic north.
2) The variable signal rotates at a fixed rate and flashes only in one direction.

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Chapter 1. Introduction to the System

Let’s assume that it takes 60 seconds for the variable signal to make a turn of 360° and the
reference signal (white light) flashes when the variable signal faces to the magnetic north.
By measuring the time between the observations of reference signal and variable signal, the
azimuth of current location can be calculated.

N N N

Green Light
(Variable Signal)
120°

Flash of White Light


(Reference Signal)
312°
A

Figure 1-1 Principles of Light Tower

Ex-1) when observing at the “A” point in the above figure 1-1,
1. Observer starts the stopwatch at the point when the white light
flashes.
2. Observer stops the stopwatch as soon as the green light is observed.
3. Assume that the time indicated on the stopwatch is 20 seconds.

In this case, the observer’s azimuth at the magnetic north from the
light tower can be calculated as 6° × 20sec = 120°.

Ex-2) when observing at the “B” point of the figure 1-1,


1. Observer starts the stopwatch at the point when the reference light
(white light) flashes.
2. Observer stops the stopwatch when as soon as the green light is
observed.
3. Assume that the time indicated on the stopwatch is 52 seconds.

In this case, the observer’s azimuth at the magnetic north from the
light tower can be calculated as 6° × 52sec = 312°.

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Chapter 1. Introduction to the System

Reference and Variable Signals of VOR

The signals identical to the reference and variable signals mentioned in the azimuth
principles are used in the actual VOR. The only difference is that these two signals are
radiated to the wireless signals rather than lights.

The principles of VOR are based on the phase relationship between Reference Phase Signal
and Variable Phase Signal, which are two 30 Hz signals.

The reference phase signal, as a sine wave of 30 Hz, is omni-directionally radiated and the
phase of reference signal is identically observed regardless of the observer’s direction.

Although the variable phase signal is also a 30 Hz sine wave, it is rotated and radiated at the
rate of 30 cycles/s and the phase observed varies according to the observer’s position.

The VOR receiver obtains the azimuth by calculating the phase difference between these
two signals.

Figure 1-2 shows the phase relationship between two signals in the 4 directions of VOR. The
phases of two signals will be matched when it is at 0° (or magnetic north). At the 90°
direction, the phase relationship will be changed and the variable signal as relative to the
reference signal will be delayed by 90°.

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Chapter 1. Introduction to the System

Voice and Identification Signals of VOR

The actual VOR signal in addition to the two signals mentioned above includes a unique
IDENT for identifying the VOR transmitting station and optionally, it can include a voice
signal.

IDENT consists of 2~3 different alphabets or digits with the respective transmitting station
and the 1020 Hz sine wave signal whose amplitude is modulated by the carrier wave is keyed
and transmitted. The Morse code is keyed at the speed of 7 words/minute and the
identification signal is repeated at the rate of 3 or 4 times in every 30 seconds.

The voice signal as an optional item is the audio signal in the range of 300 Hz ~ 3,000 Hz,
whose amplitude is modulated by the carrier wave. The voice signal is either transmitting
the IDENT as a voice rather than a Morse code or is used for broadcasting the airport
information (ATIS).

The modulation value included in the VOR signal for each modulated signal is described as
in the following according to the ICAO Annex 10 specification.

 30 Hz AM Signal: 30
% 9960 Hz Sub-carrier :

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Chapter 1. Introduction to the System

30 %  IDENT: 10 % Max. 
Voice Signal: 30 % Max.
1.2.2. Conventional VOR (CVOR)

In case of the conventional VOR, the terrestrial station continuously transmits the directional
(Cardioid characteristics) VHF radio wave while rotating it at the rate of 30 cycles/s in the
clockwise direction. If the receiver within an aircraft receives this signal, the modulated
signal (AM 30 Hz) can be obtained since the signal strength is varied according to the signal
strength. This signal is the variable phase signal.

Since the VOR terrestrial station is also transmitting the reference phase signal of 30 Hz at
the same time, the direction of receiving position can be known from obtaining the phase
difference by receiving these two signals simultaneously. The reference phase signal at the
conventional VOR transmits the carrier wave of 108 ~ 118 MHz by modulating the 9960 Hz
sub-carrier that is frequency-modulated with 30 Hz.

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Chapter 1. Introduction to the System

Figure 1-3 represents the radiation pattern and phase relationship of reference phase signal
(dotted line) and variable phase signal (solid line), which is received respectively from the
four points of due east, due west, due south and north.

While the phase of reference phase signal as in the figure is identical at the 4 points, the
phase of variable phase signal differs by the receiving direction. In other words, the phase
difference of two signals at each point is identical to the azimuth of the point. By doing so,
the azimuth of that point can be obtained by calculating the phase difference between two
signals.

1.2.3. Frequency Spectrum of VOR

Figure 1-4 represents the frequency spectrum of VOR signal that is radiated in the air.

Since each modulation element is amplitude-modulated to the primary carrier wave, the
frequency spectrum as in the figure is distributed in a horizontal symmetry of USB in the
right and LSB in the left around the carrier frequency fc.

The sidebands of amplitude-modulated 30Hz signal appear on the both points ±30 Hz away
from fc and its size is 16dB smaller than that of carrier wave when the amplitudemodulation
level is 30 %.

The Morse code IDENT appears on the both points ±1020 Hz away from the carrier
frequency fc and the spectrum appears on the position ±300 Hz ~ 3000 Hz away from fc
when including voice signal.

The sidebands of frequency-modulated 30 Hz signal (FM 30 Hz) appear at an interval of 30


Hz in the perspective of 9960 Hz carrier wave from both points ±9960 Hz away from the

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Chapter 1. Introduction to the System

primary carrier frequency fc. Although an infinite number of these FM sidebands exist
theoretically, the number of sidebands actually observed is highly limited since the size gets
smaller as it gets away from the sub-carrier.

1.2.4. Doppler VOR (DVOR)

Doppler VOR uses the Doppler Effect to obtain the variable phase signal.

The reference phase signals of Doppler VOR are transmitted Omni-directionally from a
fixed antenna after amplitude-modulating the 30 Hz sine wave signals on the carrier wave.
Since the antenna used in this time is non-directional, an identical signal is received in all
the directions.

The variable phase signal of Doppler VOR is transmitted by the 9960 Hz sub-carrier that has
amplitude-modulated the primary carrier wave. Actually, the sub-carrier doesn’t modulate
the primary carrier wave of 9960 Hz directly, but it indirectly modulates the amplitude of
primary carrier wave that is transmitted from a separate antenna.

The 9960 Hz sub-carrier is transmitted from the sideband antenna at a fixed distance from
the sub-carrier antenna. The sideband antenna is non-directional and is continuously rotating
in the counter clockwise direction at the rate of 30 cycles/s from the sub-carrier antenna.
Therefore, the distance from a certain point to the transmission point of 9960 Hz sub-carrier
changes at the rate of 30 cycles/s.

The Doppler effect occurs since the distance between the transmitting and receiving points
varies according to the time and as the result, the receiving frequency also changes at the
rate of 30 cycles/s as well. If the sideband antenna is rotated, the frequency deviation of 30
Hz cycle occurs in the 9960 Hz sub-carrier signal by the Doppler Effect.

Ultimately, the 9960 Hz sub-carrier signal becomes one that is frequency-modulated by the
30 Hz variable phase signal. At this time, the variable phase signal from the point of
reference phase signal, which is the phase of frequency-modulated 30Hz signal, varies
according to the receiving point.

When the variable phase signal is frequency-modulated by the Doppler Effect, the maximum
frequency deviation Δf follows the equation below.

Δf = v ⋅ f = ωR ⋅ f = 2π⋅30⋅ R ⋅ f c c c

Here, c = the speed of light (3 × 108 m/sec), R =


the rotation radius of sideband antenna, f =
the receiving frequency

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Chapter 1. Introduction to the System

According to the ICAO Annex 10 specification, Δf should be ±480 Hz. The rotation radius
of antenna to raise the frequency deviation of ±480 Hz in a given frequency may be
calculated in the following equation.

480 ⋅c 8⋅c 8⋅λ


R= = =
f ⋅2π⋅30 π⋅ f π

Ex) when f=113MHz, the rotation radius of the antenna can be calculated,

8 300
R= × ≈ 6.76m
3.14 113

Therefore, the circle diameter that the antenna rotates becomes approximately 13.52m.

Figure 1-7 represents the phase relationship for the frequency deviation (solid line) and
reference phase signal (dotted line) of the 9960 Hz sub-carrier signal received respectively
from 4 points of ①due north, ②due east, ③due south and ④due west, which are distant
from the Doppler VOR. As mentioned in the previous section, the frequency deviation curve
of 9960 Hz sub-carrier signal represents the variable phase signal.

Although the phases of reference phase signal are identical at 4 points, as shown in the
following figure, the phases of variable phase signal vary according to the receiving point.
In other words, the phase difference between two signals at a point is the same as the azimuth
of that point. Therefore, the azimuth at a certain point can be obtained by calculating the
phase difference between two signals at any point.

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Chapter 1. Introduction to the System

1.2.5. The Continuous Rotation Effect of Antenna

There are several difficulties in rotating the antenna physically to obtain the variable signal
necessary for the Doppler type of VOR. Instead, the electrically rotating effect can be
obtained by suddenly applying electricity sequentially by arranging 48 or 50 antennas on a
fixed circle perimeter. Switching the antenna can make the sudden sequential electricity
supply. Since the rotation effect can be discontinuous only by the sequential switching of
the antenna, the blending method is used to obtain the continuous rotation effect.

Different magnitudes of electricity are supplied simultaneously to two adjacent antennas to


have the continuous rotation effect. At this time, the electricity applied to these two antennas
is modulated according to a fixed blending function, so that the size of modulation signal at
one side becomes the maximum while that of the modulation signal at the other side becomes
“0.” By applying two signals that the modulation phases between two antennas are 180°
different from each other, the signal from two antennas at one receiving point appears to be

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Chapter 1. Introduction to the System

vector-synthesized. Ultimately, the same effect as an antenna of continuously rotated and


radiated can be obtained by appropriately selecting the antenna switching timing and
blending function.

A general blending signal holds the form of figure 1-6 and it can be classified by the COS
blending signal and SIN blending signal. COS blending signal is applied to the odd
numbered antenna and SIN blending signal is applied to the even numbered antenna.

Figure 1-6 Implementing the Continuous Rotation Effect by Blending

1.2.6. Comparison between CVOR and DVOR

Figure 1-7 has compared the signal phase relationship of conventional VOR and Doppler
VOR when receiving one VOR signal from two aircrafts A (90°) and B (135°) in two
different directions.

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Chapter 1. Introduction to the System

As described earlier, the reference phase signal of conventional VOR is the


frequencymodulated 30 Hz (FM 30 Hz) and the variable phase signal is the amplitude-
modulated 30 Hz (AM 30 Hz). The phase in the reference phase signal from CVOR is slower
than that of the variable phase signal (as much as the azimuth of the receiving point).

The reference phase signal in the Doppler VOR is the amplitude-modulated 30 Hz (AM 30
Hz) and the variable phase signal is the frequency-modulated 30 Hz (FM 30 Hz). The phase
of the reference phase signal in DVOR is faster than that of the variable phase signal (as
much as the azimuth of the receiving point).

However, the receiver calculates the azimuth by calculating the FM 30 Hz phase from the
phase of AM 30 Hz, whether it is the reference phase signal or the variable phase signal.
Therefore, the identical azimuth is obtained from the same receiving point whether it is
DVOR or DVOR. Consequently, CVOR and DVOR can be separated from the perspective

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Chapter 1. Introduction to the System

of an aircraft and also, there is no difference in CVOR and DVOR in the perspective of using
it.

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Chapter 1. Introduction to the System

1.2.7. Collocation of VOR and DME/TACAN

In addition to the azimuth information, VOR can be collocated with DME (Distance
Measuring Equipment) or TACAN in order to provide the distance information necessary
for the blind flying.
When providing the direction and distance information to the civil and military aircrafts, the
VOR is operated in collocation with TACAN and when the direction and distance
information is provided only for the civil aircrafts, the VOR is operated in collocation with
DME (Distance Measuring Equipment).

1.2.8. Use of VOR

In order to aid your understanding, VOR can be considered as a numerous number of spokes
extending from the center of a wheel to the outside in various directions. At this time, the
respective extending spoke can be considered as the bearing azimuth in each direction and
it is called as the radial of that direction. Since only the integer radial is used in the current
VOR navigation, the actually used radials of 360 units can be thought to exist in the bound
of 1° ~ 360°.
Each radial represents the magnetic bearing outbound from the VOR directing to the outside.

The location and frequency of VOR terrestrial station are marked on the radio navigation
chart. Since several VOR terrestrial station can exist in one area, a unique IDENT is allocated
to each VOR to be distinguished from each other. Also, the IDENT is indicated on the radio
navigation chart together with the VOR frequency. The VOR terrestrial station transmits its
own IDENT in a Morse code of 2~3 characters and the aircraft classifies each VOR
terrestrial station as an indicated IDENT.

The way that an actual aircraft uses a specific VOR is first to set the receiver frequency to
the VOR frequency indicated on the radio navigation chart and then to select the targeted
course (radial) by turning the handle of Omni-Bearing Selector (OBS). If it is within the
selected VOR service area, the degree and direction of the current location deviated from
the selected course is indicated on the Course Deviation Indicator (CDI). If the service range
of the aircraft is deviated, an alarm flag will be indicated on the indicator.
1.2.9. VOR Receiver

The VOR receiver mounted onto the aircraft follows the selected VOR frequency channel
and receives the signals from VOR.

The VOR receiver consists of an AM receiver circuit with a general super-heterodyne


method, the band pass filter for VOR signal processing, an FM discriminator, and the phase
comparator and indicator.

The signal received through the antenna is demodulated into the original composite VOR
signal after passing through the circuits of the high frequency amplification, frequency
conversion, medium frequency amplification and demodulation.

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Chapter 1. Introduction to the System

Again, this signal is further classified into the AM 30 Hz signal and 9960 Hz sub-carrier by
the respective filter. The AM 30 Hz signal is separated from the composite VOR signal by
the low pass filter. The 9960 Hz sub-carrier signal is demodulated into the FM 30 Hz signal
after passing through the 9960 Hz band pass filter and FM discriminator.

Two 30 Hz signals (AM 30 Hz signal and FM 30 Hz signal) are inputted to the phase
comparator and the result is indicated on the indicator.
Navigational Signal Processing

Figure 1-8 Configuration of the VOR Receiver

1.2.10. VOR Course Indicator

A typical VOR course indicator is constructed as in the following.

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Chapter 1. Introduction to the System

TO

OBS

Figure 1-9 VOR Course Indicator

1) OBS (Omni Bearing Selector)


OBS is used by a pilot in selecting the course to be navigated. Turn the OBS handle in the
left/right directions so that the course selection arrow near to the compass plate indicates the
desired course azimuth. The azimuth that the arrowhead direction indicates is the course
radial.

2) CDI (Course Deviation Indicator)


CDI, for the course selected by a pilot, indicates how much the location of current aircraft is
deviated from the direction and what degree. If the CDI needle is centered, the aircraft is
positioned on the selected course and if the needle is positioned to the left/right side, it refers
that the aircraft is deviated to the left/right direction. There are five small dots in the left and
right sides of the course indicator center. One dot represents 2° and the needle moves within
the range of 10° to the left and right.

3) TO-FROM Indicator (Flag)


The TO-FROM Indicator indicates whether the current aircraft location on the selected
course radial is at the position approaching to the VOR receiving station or at the position
of getting away from the VOR transmitting station. When the course selected as in the figure
1-10 indicates “TO,” it refers that the aircraft is located in the opposite direction of the
selected radial and when that indicates “FROM,” it means that the aircraft is located in the
same direction as the selected radial.

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Chapter 1. Introduction to the System

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Chapter 1. Introduction to the System

1.3. Related Technology and Theory


1.3.1. Doppler Effect

Doppler Effect, for the relative movement between the wave motion originator and observer,
refers to the phenomenon that the number of vibrations differs when they are stopped and
relatively moving. For example, when a train approaches to the observer on a railroad track,
the siren of the train will be heard high and when the train gets farther off from each other,
it will be hard low. The Doppler Effect can be found from the wave motion and the change
in the observed values of the frequency by this effect depends on the relative velocity of the
wave motion and the relative speed of the observer.

A B

fo

(a) When A and B are not moving

A B
v

fo + f

(b) When A is moving toward B

A -v B

fo - f

(c) When A is moving away from B


Figure 1-11 Doppler Effect

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Chapter 1. Introduction to the System

Suppose that when A in the figure 1-11 emits the radio wave of f0 (Hz), the radio wave is received
by the receiver B and A is moving at the rate of v (m/s) toward B. Then, the frequency of the radio
wave received from B can be calculated as in the following.

f0 + f0v f
=

(c −v)

If A and B are moving in the opposite directions from each other, the following can be
applied.

f = f0 − f0v (c
−v)

Here, c is the speed of radio wave, which is the speed of light (3×108m/s). The frequency
deviation occurred by such Doppler Effect could be summarized as in the following.

v
Δf =f0 − f = f0
(c −v)

Here, since c (the speed of radio wave) is much faster than v (the speed of a moving object),
(c−v)≅ c
Therefore, the following equation can be derived.

ν
Δf ≅ fo
c

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Chapter 1. Introduction to the System

1.3.2. Frequency Band of VOR (VHF)

VHF communication is used for the air traffic communication, aeronautical information
service, aeronautical operation communication and operational communications for the
aircrafts within the line of light.
The frequency range used by VOR falls within the VHF frequency band of 108.000 MHz or
above and 118.000 MHz or below.
Since VHF radio wave has the straight-going nature and the diffraction as compared to those
of LF, MF and HF is relatively small, the reachable distance is wide. Due to these
characteristics, it is widely used such as for the short-distance mobile communication and
aeronautical control.

Uses and Characteristics in Varying the Frequency Range

Weak Strong

Name Frequency Use


Range

VLF 3kHz~30kHz Ship

LF 30kHz~300kHz Weather broadcasting, the


navigation beacons
for ship or aircraft

MF 300kHz~3MHz Radio, amateur radio, ship


accident
communication
Straight Diffraction
HF 3MHz~30MHz Amateur radio, ship
accident communication,
short-wave broadcasting

VHF 30MHz~300MHz FM broadcasting,


television broadcasting,
amateur radio,
aeronautical radio

UHF 300MHz ~3GHz Television broadcasting,


amateur radio,
aeronautical radio, radar

SHF 3GHz~30GHz Weather radar, satellite


Strong Weak
broadcasting, space
communication

EHF 30GHz~300GHz Radar, radio wave


astronomy

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Chapter 1. Introduction to the System

1.4. Characteristics of MARU 220 Doppler VOR


MARU 220 Doppler VOR is designed so that similar instrumental indications in aircraft
represent equal clockwise angular deviations (bearings), degree for degree from magnetic
North as measured from the location where it is installed.

If properly installed, the equipment radiates a radio frequency carrier with which is
associated two separate 30 Hz modulations. One of these modulations is such that its phase
is independent of the azimuth of the point of observation (reference phase). The other
modulation (variable phase) is such that its phase at the point of observation differs from
that of the reference phase by an angle equal to the bearing of the point of observation with
respect to the VOR.

The followings are major features and characteristics of the MARU 220 Doppler VOR.

Compact Design

By enclosing dual transmitter, dual monitor and dual power supply in a single, standard 19”
rack cabinet, its size and power consumption are minimized and the cost-effectiveness is
also accomplished.

State of the Art Digital Technology

The equipment is fully solid-state design with no mechanically moving parts, except for
high-reliability relays and long-life brushless fans. It can be reliably controlled or managed
through the Motorola 68000 series of microprocessor and its flexibility has been greatly
improved by using EPLD to the digital circuit part.

Hot-swappable Plug-in Units

Plug-in types Line Replaceable Units (LRU) with card ejector are used, where applicable.
The hot-swap function is implemented to replace a LRU without turning off the system.

System Operation while Using the Convenient GUI Environment

The system can be controlled at a remote location by implementing the Remote Maintenance
and Monitoring System (RMMS) to the general PC and the major parameters, system status,
unit status, alarm status and RF output level can be controlled and checked.

Self-Diagnostic Function

The Built-in Test Equipment (BITE) function is included to check integrity of the system
operation.

Collocate with DME/TACAN System

MARU 220 can be easily configured to collocate with any DME/TACAN.

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Chapter 1. Introduction to the System

1.5. MARU 220 Doppler VOR Specification


MARU 220 is designed suitable to the ICAO Annex 10 specifications.

1.5.1. System Specification

Item Specification

Azimuth Accuracy Within ±0.5°


(When measuring at the point 300m away from the antenna with the
low angle shot of 3°

Azimuth Stability Within ±0.25°


(When measuring with the system monitor)
A minimum of 200NM or over from the visible distance when using the
output of 100W
Coverage
(Electric field strength of 90 µV/m or electricity density of -107
dBW/m2)

Within the 30%±2% nominal


30 Hz AM Stability (When measuring at the distance of 300m from the antenna or above
from the antenna and within the low angle shot of 5°)

Within the 30%±2% nominal


9960 Hz AM Stability (When measuring at the distance of 300m from the antenna or above
from the antenna and within the low angle shot of 5°)

16±1
9960 Hz FM Index (When using the antenna ring diameter of 13.6m and the frequency of
113 MHz)

AM percentage of lower than 40%


9960 Hz subcarrier (When measuring at the distance of 300m from the center antenna)

Azimuth Offset Possible to set with an arbitrary value at the interval of 0.1° within the
(North Alignment)
range of 0° ~ 360°

Equipment Dimensions 1888 mm (H) *600 mm (W) * 600 mm (D)

Environmental Protection Complant with EN60529 IP54 rating

MTBF Longer than 10,000 hours (MIL-HDBK-217)


Reliability / Maintainability
MTTR Less than 15 minutes

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Chapter 1. Introduction to the System

10A or less
Max Consumption Current (AC220V, Hot standby 100W output, except for the backup battery
charging current)

Operating -10 °C ~ 55 °C (indoor)


Temperature
-40 °C ~ 70 °C (outdoor)

Relative Within 95% (Up to the temperature of 35 °C)


Environmental Conditions
Humidity
Within 60% (Above the temperature of 35 °C)

Operating
Up to 4,500m (15,000ft)
Altitude

1.5.2. Transmitter Specification

Carrier Specification
Item Specification

Frequency Range 108.000 MHz ~ 117.975 MHz


(Arbitrarily selectable in steps of 50kHz)

Frequency Tolerance ±0.001%

Frequency Stability Better than ±0.001%

Better than ± 5 degrees


Phase Stability
(measured at the transmitter output)

100 W
Power Output (When measuring at the tip of a R214 antenna sudden electricity cable with
the length of 15m)

Output Power -75% ~ +20%


Adjustment Range (Adjustable in steps of of 1W or 0.1W, selectable)

Output Impedance 50 Ω

Withstands infinite VSWR


Protection When Abnormal VSWR, alarmed and cutoff output
No excessive RF power than rated value due to failure of components

2nd Harmonic Wave: Below –60 dBc


Harmonics
3rd Harmonic Wave: Below –70 dBc

Spurious radiation Below -60 dBc

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Chapter 1. Introduction to the System

Modulation Depth of
Up to 80%
Main Carrier

Frequency: 30 Hz ±0.01% sine wave


Reference Signal of
AM Depth : 30% nominal
30 Hz
(Adjustable in steps of 0.1% within the range of 0% ~ 40%)

Frequency: 1020 Hz ±0.01% sine wave


AM Depth : 10% nominal
(Adjustable in steps of 0.1% within the range of 0% ~ 30%)
Code: International Morse code of 2~3 characters, up to 4 characters
IDENT Signal
Code Length: Dot/Pause – 125ms, Dash 374 ms, 7 words per minute
Repetition: 4 times in every 30 seconds for standalone mode
When collocated with DME or TACAN: 3 times of VOR, 1 time of DME in
every 30 seconds:

Frequency: 300 Hz ~ 3000 Hz Range


(Within 3 dB of the flatness when using 1000 Hz as the 0dB reference point)
Voice Signal AM Depth: 30 % nominal, adjustable up to 40% in steps of 0.1%
Harmonic distortion: less than -30dBc in total

Sideband Specification
Item Specification

Sideband Type
Double Side Band (DSB)

Sub-carrier Frequency 9960 Hz ±1%

Phase Stability Better than ± 5 degrees


(measured at the transmitter output)

Power Output 25 W PEP (6 W CW) nominal per sideband

Variable Output Range Adjustable -80% to +20% in steps of 0.1 W

Output Impedance 50Ω

2nd Harmonic Wave: Below –40 dBc

Harmonic Element 3rd Harmonic Wave: Below –50 dBc

4th or Higher Harmonic Wave: Below –60 dBc

Frequency: 720 Hz
Blending Modulation
Blending Function: Updated SIN wave. Possible to use other wave
Signal program

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Chapter 1. Introduction to the System

1.5.3. Monitor Specification


Item Specification

Azimuth Measuring Range: 0° ~ 359.9°, resolving power 0.1°

Measuring Accuracy: Within ±0.15°

30 Hz AM Modulation Measuring Range: 0 ~ 40%, resolving power of 0.1%


Depth Measuring Accuracy: Within ±1%

9960 Hz AM Modulation Measuring Range: 0 ~ 40%, resolving power of 0.1%


Depth Measuring Accuracy: Within ±1%

Measuring Range: 14 ~ 18, resolving power of 0.1


FM Index
Measuring Accuracy: Within 0.2

Defective Antenna Possible to detect the defects of one and two antennas at the same time
Detection

Configuration Single or Dual: ‘AND’ or ‘OR’ mode

Alarm Limit Boundary Possible to set simply through the graphic user interface(GUI).

1.5.4. Antenna Specification

Carrier Wave / Sideband Antenna Specification

Classification Item Specification

Antenna type
Type & Alford Loop
Configuration Configuration 1 carrier wave antenna + 48 sideband antennas

Electrical Frequency Range 108 MHz ~ 118 MHz, adjustable in the field
Characteristics
Voltage Standing Wave 1.2 : 1 or below, in the state adjusted to the use
Ratio (VSWR) frequency

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Chapter 1. Introduction to the System

Impedance 50 Ω, nominal

Polarization Horizontal

Vertical Polarized Element ≤ -40 dBc

Horizontal Plane Radiation


Omini-directional
Characteristics

Deviations in the Horizontal


Plane Radiation Amplitude ≤±0.5 dB, phase ≤5°
Characteristics

Max Input Power 200W

Connector Standard N-type, Female

Mechanical Diameter 0.8 m


Characteristics
Height 1.2 m ~ 1.4 m

Cover (Radome) Material Glass Fiber Reinforced Polyester (FRP)

Pedestal Material Hot dip galvanizing steel

Environmental Temperature Range -40°C ~ +70°C


Conditions
Relative Humidity 0% ~ 100%

Altitude Limit 4,500m above sea

Wind Speed Limit 60 m/sec

Salinity 5 % ±1 % @30°C

Hailstone Diameter of 1 cm

Freezing Thickness of 5 cm

Monitor Antenna Specification


Classification Item Specification

Configuration
Configuration Single antenna
& Type Antenna Type 4-element Yagi-Uda

Electrical Frequency Range 108 MHz ~ 118 MHz, adjustable in the field

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Chapter 1. Introduction to the System

Characteristics Voltage Standing Wave 1.2 : 1 or below (in the state adjusted to the use
Ratio (VSWR) frequency)

Impedance 50 Ω, nominal

Horizontal Plane Gain ≥ 7 dBi

Front to Back Ratio ≥ 12 dBi

Partiality Characteristics Horizontal partiality

Mechanical Dimension 2.3m (L) × 1.5m (W)


Characteristics
Weight

Material Stainless steel & brass

Connector Type Standard N-type, Female

Environmental Temperature Range -40 ~ +70 °C


Conditions
Relative Humidity 0 ~ 100 %

Wind Speed Limit 60 m/sec

1.5.5. Counterpoise Specification

Item Specification

Diameter 30m standard

Height 3 m, 5m, 7m, or 10m

Antenna Ring Diameter About 13.5m at f=113MHz (16 × λ / π)

Structure Material Melting hot dip galvanizing steel and stainless steel

1.5.6. Power Supply Specification


Item Specification

Configuration
Dual AC/DC converter, dual DC/DC converter
Parallel Battery Connection: Continuous charging & backup

AC/DC Converter Rated Input Voltage: 110V/220 VAC ±20%, single-phase


Input Frequency: 47Hz~63Hz
Rated Output Voltage: 28 VDC, Nominal

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Chapter 1. Introduction to the System

DC Output Voltage
DC/DC Converter
+5 V, +7 V, +15 V, -15 V, +28 V

Type: Maintenance-free lead battery


Charge/Backup Type: Parallel connection, continuous charging
Backup Battery and backup
Rated Output Voltage: 24 V
Capacity: 120AH, sustainable dual system for 4 hours

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Chapter 1. Introduction to the System

1.6. System Configuration

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Chapter 1. Introduction to the System

Figure 1-12 System Diagram


1.6.1. Hardware

The hardware of MARU 220 consists of the following 4 sub-systems.

 AES (Antenna Electronics Sub-


system)  MAS (Modulation Amplifier
Sub-system)  CMS (Control Monitor Sub-
system)  PSS (Power Supply Sub-
system)

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Chapter 1. Introduction to the System

Figure 1-13 Sub-system of MARU 220

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Chapter 1. Introduction to the System

Figure 1-14 Unit Mounting Positions


Each sub-system consists of the following line replaceable units (LRU) or assemblies.

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Chapter 1. Introduction to the System

Sub-system Name Quantity Note

PDC LRU 1

ASU LRU 1
AES

CMA LRU 2

MAS SMA LRU 4 USB -2 / LSB - 2

FAN LRU 2

MSG LRU 2

CSU LRU 1

CMS MON LRU 2

LCU LRU 1

CSP Assembly 1

AC/DC LRU 2

DC/DC LRU 2
PSS
PDU LRU 1

FAN LRU 2

1.6.2. Antenna

One antenna unit consists of 1 antenna, 48 sideband antennas and 1 monitor antenna. The
carrier antenna is installed on the center of counterpoise and the sideband antenna is installed
at an interval of 7.5°on the perimeter that is a fixed distance away around the centre of the
carrier wave antenna. Each sideband antenna is numbered in the counter clockwise direction
starting from the antenna #1 positioned on the due north to #48.

In order to monitor the transmitted signal quality, the monitor antenna is installed at the point
that is at least 80m away from the center of counterpoise.

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Chapter 1. Introduction to the System

1.6.3. Operating Software (LMMS / RMMS)

As for the user interface equipments in monitoring and maintaining various equipments, the
Remote Maintenance Monitoring System (LMMS) and Remote Maintenance Monitoring
System (RMMS) can be considered. These systems are installed and operated onto the IBM-
compatible PC by installing the Windows 2000 or higher OS.
LMMS is connected to the system console through a serial RS-232 cable and RMMS is
connected to the system remote port through a private line or dial-up modem.

1.6.4. Remote Control Unit

The remote control unit consists of Remote Control & Monitor Unit (RCMU) and Remote
Monitor Unit (RMU).

RCMU is made possible to display and control the status of equipments by attaching the
LED indicator, LCD and keypad. RMU only has the function of indicating the status of
equipments while not having the control function of changing the status of equipments.

1.6.5. System Redundancy

The redundancy of MARU 220 system is made available to the power unit, transmitter and
monitor. Therefore it is possible to test the performance and carry out servicing of standby
transmitter without impairing the operation of the main transmitter.

Redundancy in Power Supply

Since the output of two independent MARU 220 power units is connected in parallel, the
remaining one supplies the power necessary to the entire system when one of two power
units is not functioning. Since it is designed in such a load sharing structure, there exists
neither a physical switching process nor a power interruption state.

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Chapter 1. Introduction to the System

Backup
Battery#1

AC/DC DC/DC
Converter#1 Converter#1

220 VAC DC
Input Output

AC/DC DC/DC
Converter#2 Converter#2

Backup
Battery#2

Figure 1-15 Redundancy in Power Supply

Redundancy in Transmitter

The transmitter unit of MARU 220 is duplicated in a way that transmits the output of two
independent transmitters through one selected by the switch and the other added to the
dummy load to emit by heat.

If a problem occurs from the transmitter connected to the antenna, the monitor detects it and
sends a command to switch over the converter. If this command is executed, the output of
current standby transmitter is switched over to the antenna and the transmitter output
previously connected with an antenna is switched to the dummy load. It is done in the way
of shifting the roles of active and passive (standby) transmitters.

It can be classified into the types of Hot Standby and Cold Standby according to the standby
transmitter operation and one type can be selected according to the system setting. In case
of the Hot Standby type, 100% of the standby transmitter output continues to be outputted
to the dummy load. In case of the Cold Standby, it turns off the transmitter output when in
the standby mode and the output is emitted when switched to the active mode.

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Chapter 1. Introduction to the System

Redundancy in Monitor

MARU 220 uses two independent monitors and they receive, analyse and checks the signals
emitted to the air in the current system. The signal inputted to the monitor is received from
one common antenna and is distributed to two monitors. As an option, they can be
independently supplied to two monitors by using two antennas.

DVOR System

Monitor#1
Monitor Antenna
(Active)

Monitor#2 Distributor
(Standby)

Figure 1-17 Redundancy in Monitor

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Chapter 1. Introduction to the System

The operation status of the system can be judged by using the results of two redundant
monitors and it may effect on the system operation according to the result selection when
two different outputs are made from two separate monitors.

MARU 220 requires user to selectively use one of two modes “AND and OR” when judging
an error from the analysis results of two monitors.

The “AND” mode is the method of judging an error when the signal analysed by both
monitors is found to be erroneous and the “OR” mode regards it an error when either one of
them is found to be erroneous.

1.6.6. Slot Location and LRU Insertion

Each unit of MARU 220 should be installed in the correct area since the installable area is
fixed respectively. If one is installed in a different area, it may cause a permanent damage to
the circuit. In order to prevent this risk fundamentally, the CMS and MAS units are designed
as in the following.

 MAS (SMA, CMA): Since the sizes of SMA and CMA are significantly different from
each other, it is almost impossible to insert into other positions. It will not make any
problem since SMAs are compatible with each other.
 CMS (MON, MSG, CSU, and LCU): Since the connector locations connected to the
back-plane are different from each other, the units corresponding to the locations can
be mounted.

CMS Unit Classification

As shown on the figure below, since the connector locations are differently designed for
each slot, it is impossible to mount another unit on a specific slot. The same type of units
can be mounted in any slot.

For example, the MON unit can be attached either in the MON #1 slot or in the MON #2
slot. On the other hand, the MON unit can’t be attached to the MSG and CSU slots since the
connector positions are designed to be different.

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Chapter 1. Introduction to the System

96P

96P 96P 96P 96P

96P
144P

96P 96P 96P 96P

96P

MSG #1 MON #1 CSU LCU MON #2 MSG


Figure 1-18 Slot Location for CMS Units

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Chapter 2. Sub-Systems Description

Chapter 2. Sub-Systems Description


2.1. AES (Antenna Electronics Subsystem)
2.1.1. Overview

AES (Antenna Electronics Subsystem) consists of ASU and PDC units. PDC is installed in
a cabinet and ASU is installed within the equipment room as a separate structure.

Figure 2-1 External View of ASU

Figure 2-2 Location and Appearance of PDC

LRU Quantity Description

ASU 1 Sideband antenna switching

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Chapter 2. Sub-Systems Description

PDC 1 Power Detection on all RF power output paths


and transmitter changeover

2.1.2. Function

ASU (Antenna Switching Unit)

ASU switches 4 sideband outputs (USB SIN, USB COS, LSB SIN, and LSB COS) from
PDC and distributes to 48 antennas.

ASU basically consists of an RF switch that accommodates 4 inputs and 48 outputs. The
control signal of this switch is generated from MSG and supplied to ASU via CSU.

AUS, different from other units, is not included in the main cabinet and is separately installed
in the outside.

PDC (Power Detector & Changeover)

PDC does changeover of the transmitter connected to the antenna and of sampling the RF
power output level.

PDC includes an RF relay that allows selects and changing over the output from two
transmitters TX1 and TX2. By using this relay, one output of two transmitters is connected
to the antenna and the other output is connected to the dummy load.

Also, PDC samples the RF signals from each course (CAR, USB SIN, USB COS, LSB SIN,
and LSB COS), detects their magnitude and monitors the status of the antenna.

2.1.3. Interface between Units

1) ASU  ASU is positioned between PDC and sideband antenna for the RF signal
flow.
 The RF signal inputs of ASU are the 4 sideband signals (LSB COS, LSB SIN, USB
COS, USB SIN) provided by PDC.
 The RF signal outputs of ASU are the 48 signals distributed to the respective sideband
antennas.
 The switching control signal and power of ASU is provided by the CSP.

2) PDC  PDC is located between MAS and ASU (antenna in case of the carrier wave) for
the RF signal flow.
 The RF signal inputs of PDC are the carrier wave signal and 4 sideband signals, which
are supplied from both sides of CMA and SMA.

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Chapter 2. Sub-Systems Description

 Likewise, the RF signal outputs of PDC are the carrier signal and 4 sideband signals. As
for the carrier wave it is directly supplied to the antenna and in case of the sideband it is
supplied to ASU.
 The input signal for controlling the coaxial relay operation is supplied from CSU.
 The signals for the monitoring and status-control, outputted from PDC, are supplied by
MON.

Figure 2-3 AES Block Diagram

2.2. MAS (Modulation Amplifier Subsystem)


2.2.1. Overview

Modulation Amplifier Subsystem (MAS) is the subsystem that is responsible for the RF
signal oscillation, modulation and power amplification.

MAS are made of the dual redundant structure that two transmitters (TX1 and TX2) operate
independently. One transmitter includes CMA of generating the carrier wave signal, USB
SMA of generating the upper sideband signal, LSB SMA of generating the lower sideband
signal, and the cooling fan.

The locations of installing each MAS LRU are shown on the following figure 2-4.

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Chapter 2. Sub-Systems Description

Figure 2-4 Locations and Appearance of MAS LRUs

Name Quantity Description

CMA 2
CMA executes the functions of generating, modulating and
amplifying the carrier RF signal.
SMA 4 SMA executes the functions of generating, modulating and
amplifying the sideband RF signals. According to the positions
installed, the left side becomes the SMA for LSB and the right side
becomes the SMA for USB.

2.2.2. Functions

CMA (Carrier Modulation Amplifier)

CMA generates stable carrier wave RF signals by using the temperature-compensated crystal
oscillator(TCXO) and the PLL frequency synthesizer. And by using the composite

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Chapter 2. Sub-Systems Description

modulation signal supplied from MSG, it performs the amplitude modulation task and then
does the power amplification of modulated carrier wave signals.

The inner area of CMA is largely subdivided into three parts of SYN (Synthesizer), MOD
(Modulator) and CPA (Carrier Power Amplifier), as in the following.

 SYN: Generate the carrier wave RF signals. These signals are transmitted to MOD. 
MOD: Amplitude-modulate the carrier wave RF signals. The modulated signals are
transmitted to CPA.
 CPA: Amplify the modulated carrier wave RF signal.

SMA (Sideband Modulation Amplifier)

SMA generates the sideband RF signal synchronized to the reference signal received from
CMA and modulates the amplitude by using the SIN/COS blending signal supplied from
MSG. Then, it amplifies the power of modulated sideband signal.

The inner area of SMA is largely subdivided into three parts of SYN (Synthesizer), MOD
(Modulator) and SBA (Sideband Amplifier), as in the following.

 SYN: Generate the sideband RF signals. 


MOD: Amplitude-modulate the sideband RF signals. 
SBA: Amplify the modulated sideband RF signals.

2.2.3. Interface between Units

1) CMA  The modulation signal input of CMA comes from the composite audio band
signals.
This signal is supplied from MSG.
 The main signal output of CMA comes from the amplitude-modulated carrier wave RF
signals. This signal is provided to PDC.
 The control signals such as the PLL frequency setting data of CMA are supplied from
MSG.
 The status monitoring and BITE signal output of CMA is supplied to MSG.
 The reference frequency signal of CMA is supplied to SMA.

2) SMA  The modulation signal input of SMA comes from the audio band blending signals.
This signal is supplied from MSG  The main signal output of CMA comes from the
amplitude-modulated sideband RF signals. This signal is provided to PDC.
 The control signals such as the PLL frequency setting data of SMA are supplied from
MSG.
 The reference frequency signal applied to the SMA PLL is supplied from CMA.

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Chapter 2. Sub-Systems Description

MSG CMA SMA

PLL LOCK DETECTOR REF CLOCK


PLL DATA SYN CARRIER FREQ

COMPOSITE

MOD

CPA CARRIER FREQ to MON

CARRIER OUT to PDC

Figure 2-5 MAS Blocks & Interfaces

2.3. CMS (Control & Monitor Subsystem)


2.3.1. Overview

CMS (Control & Monitor Subsystem) generates each modulation signal and timing signal
and supplies them to MAS and AES, monitors the system operation status and transmission
signal quality, and controls the functions of each system component.

Figure 2-6 indicates the CMS position within the system cabinet and the respective unit
positions within the CMS rack.

Figure 2-6 Locations and Appearance of CMS LRUs

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Chapter 2. Sub-Systems Description

Name Quantity Description

MSG 2
MSG generates the carrier wave, sideband modulation signals
and the timings for the switching of sideband antenna. Also, it
controls and monitors the status of transmitter.
MON 2 MON monitors the status of transmitted signals. It checks the
major parameters while analyzing the signals sampled from the
monitor antenna and stops/switches the transmitter if an error is
found.

CSU 1 CSU selects one from the sideband antenna switching signals
generated by two MSGs, converts the level and supplies it to ASU.
Also, the TSG for the verification of MON operation status and the
interface circuit necessary for the collocation with DME/TACAN
are included.

LCU 1 LCU takes the operator’s commands through LMMS/RMMS and


RCMU and sends them to MSG and MON, and send them back
to LMMS/RMMS and RCMU/RMU after receiving the responses.

2.3.2. Functions

LCU (Local Control Unit)

LCU delivers the operator’s control commands to MSG and MON and returns the status
information received from MSG and MON to the operator.
Operator exchanges the control commands and status information through RMMS, LMMS,
RCMU and CSP.

 Process the messages received from RMMS, LMMS and RCMU. 


Control the LCD, LED indicator lamp and keypad that are attached to
CSP.  Select the test signals of TSG (Test Signal Generator). 
Monitor the voltage and current status of PSS.
 Read the current status of the environment monitoring sensors
(temperature, fire and intrusion).

MSG (Modulation Signal Generator)

The basic functions of MSG can be summarized by generating the modulation and antenna
switching signals and by controlling the transmitters.

 Generate the composite signals of 30 Hz reference phase signals, IDENT and voice,
which are the modulation signals for the carrier wave.
 Generate the SIN and COS blending signals, which are the modulation signals for the
sideband.
 Generate the control signals for antenna switching.  Set the SYN oscillating
frequencies within CMA and SMA.

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Chapter 2. Sub-Systems Description

 Set the transmission output by controlling the amplitudes of carrier wave and sideband
modulation signals.
 Control the phases of RF signal being transmitted.

MON (Monitor)

MON monitors the radiated signals and detects error. When the controlled level of signals is
not transmitted, it issues a warning and switches over to the standby transmitter to carry out
the recovery. If the signals are not recovered even after switching to the standby transmitter,
the transmission will be stopped.

The major parameters monitored by MON are followed as in the


below.  Monitor reference azimuth  Reference 30 Hz AM
depth  Index of variable 30 Hz FM  9960 Hz sub-carrier AM
depth  IDENT code and AM depth

Additionally, MON executes the following monitoring and test functions.


 Monitoring the transmission frequencies of carrier wave and
sideband  Monitoring the output power of carrier wave 
Monitoring the carrier wave and sideband antennas

CSU (Control Select Unit)

CSU, as one of the parts that cannot be included in the system redundancy, holds the
following functions.

 The interfaces for supporting the transmitter and monitor redundancies  The TSG
(Test Signal Generator) for testing and verifying a monitor
 The VOP for processing the voice signal to be included in the composite modulation
signals
 The interface with DME or TACAN equipments to be collocated

CSP (Control and Status Panel)

CSP, which is attached to the front panel, is the input/output device for indicating the system
status and for taking the control input. A graphic LCD, 12 LED indicators and 7 input keys
are included within CSP. CSP, which is connected to the I/O bus of the CPU inside of LCU,
is directly controlled by LCU.

2.3.3. Interfaces between Units

1) Interfaces to External Devices  LMMS: Connect to LCU


through RS-232C.  RMMS: Connect to LCU through a dial-
up/private-line modem.  RCMU: Connect to LCU through a
dial-up/private-line modem.
 RMU: RMU is generally connected to RCMU, but it can be directly connected to LCU
through a RS-485 line if needed.

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Chapter 2. Sub-Systems Description

2) Interfaces to MAS or AES


 MSG - CMA: Composite modulation signal, PLL frequency setting data,
BITE  MSG - SMA: Blending signal, PLL frequency setting data, BITE
 CSU - PDC: Coaxial relay control signal, output power sample, BITE 
CSU - ASU: Antenna switching control signal

3) CMS Internal Interfaces


 LCU - MSG: RS-232C serial
communication  LCU - MON: RS-232C
serial communication  LCU - CSU: TSG pattern
selection signal  MSG - CSU: Antenna
switching control signal  MON - CSU:
Changeover control signal

#2
#1
Direct cable
LMMS
RS232
RS232 Monitor signal
MON
Dial-up/leased line
RMMS MODEM

Dial-up/leased line
RCMU Composite
MODEM
RS232
LCU MSG SIN To MAS
RS485
COS

RMU TX1 TX2


Power Control
To PDC
On/off Control ANT Timing
CSU To ASU
CSP CPU I/O
Relay Control
To PDC
IDENT keying

DME/TACAN

Figure 2-7 CMS Blocks & Interfaces

2.3.4. Common Data Storage

CMS backplane, in addition to the connectors, includes the 4K-byte capacity of nonvolatile
memory that can be used for the storage of following common system data.

 IDENT
 Transmission frequency  Carrier wave and sideband output level  The
modulation depth for each signal element

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Chapter 2. Sub-Systems Description

 The permissible range for each signal parameter that is monitored by MON
 Output Power Lookup Table  Monitor correction value  Other
system configuration information

The common system memory is the EEPROM of using a 2-line serial interface. In this
EEPROM, the respective MSG and MON of TX1 and TX2 are used together. Since one
EEPROM is commonly used by several units, it may cause a problem when 2 or more units
are accessed at the same time.

In order to prevent this problem, it uses one common signal line “/EEPROMBUSY” to
control the accesses to EEPROM. Since the status of this signal line ‘L’ means that other unit
is using the EEPROM, it is needed to wait until the signal line status becomes ‘H’.

2.4. PSS (Power Supply Subsystem)


2.4.1. Overview

After converting the supplied AC power into the DC power, PSS supplies the DC voltage
and charges the backup batteries.

Figure 2-8 indicates the PSS rack position within the system cabinet and the respective LRU
positions within the PSS rack.

On the front panel of AC/DC and DC/DC, there are two LED indicators: NORMAL and
ALARM. The NORMAL LED indicates that power supply function is provided as normal,
while the ALARM LED indicates a defective unit or low input voltage or primary power
failure or switched off condition.

All the ALARM indications including mains input and battery status are associated with
local/remote monitoring and control and can be remotely monitored.

Also on the front panel of AC/DC, there is a digital current meter, which displays currents
reading measured on the DC 28V output.

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Chapter 2. Sub-Systems Description

Figure 2-8 Locations and Appearances of PSS LRUs

Name Quantity Description

AC/DC 2
After converting the AC 220V into the DC +28V, it supplies it to the
DC/DC converter and charges the backup batteries.
DC/DC 2 Convert the +28V power coming from the AC/DC converter into the
respective DC voltages (+5V, +7V, +15V, -15V, +28V).

PDU 1 Distribute the respective voltages to TX1, TX2, MON1 and


MON2.

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Chapter 2. Sub-Systems Description

2.4.2. Functions

AC/DC Converter

The AC/DC converter converts the common AC220V power into the DC +28V and supplies
it to the DC/DC converter. The AC/DC converter is designed in a plug-in structure so that it
can be easily mounted or de-mounted.
An LED indicator lamp is attached to see the power status on the front panel of the AC/DC
converter. Also, the DC output current is indicated since a digital ammeter is attached.

DC/DC Converter

The DC/DC converter is provided with the DC +28V power from the AC/DC converter and
converts into the respective DC voltages (+5V, +7V, +15V, -15V, +28V) necessary for the
system. The DC/DC converter is designed in a plug-in structure same as the AC/DC
converter.
The front panel of DC/DC converter has an LED indicator lamp to see the power status.

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Chapter 2. Sub-Systems Description

2.4.3. Interfaces between Units

1) AC/DC Converter  AC/DC is duplicated in the shape that 2 identical units are connected
in parallel. The AC/DC input is connected to the common power. The AC/DC output is
connected to the DC/DC input, connecting to the backplane in parallel.

2) DC/DC Converter
 Likewise, DC/DC is duplicated in the shape that 2 identical units are connected in parallel.
The DC/DC input is connected to the AC/DC output. Each DC/DC output is inputted to
PDU through the backplane.

3) Backup Battery
 The backup battery comprises 2 sets of the nominal voltage 24V maintenance free batteries
and each battery is separately connected to both sides of the DC/DC converter.

4) Power Distribution Circuitry on Backplane (depicted as PDU)


 Both sides of DC/DC output are inputted to PDU and distributed to each component of
the system.

BACKUP
BATTERY

+24V

AC 220V +28V
AC/DC DC/DC TX1

+5V TX2
Mains +7V
+15V PDU MON1
Input -15V
+28V MON2
+28V
AC/DC DC/DC COM
AC 220V

+24V

BACKUP
BATTERY

Figure 2-9 PSS Blocks & Interfaces

2.5. Others
2.5.1. FAN

Fans, being installed to two places as below, suck in the external air and pass it through the
internal system to prevent the abnormal operation from overheating.

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Chapter 2. Sub-Systems Description

The internal part of Fan consists of 3 modules, which sucks in the air from the rear side of
the cabinet and sends it to the upper end. When the fan switch in PDU is turned on, it is
intended to operate permanently unless an error occurs.

Figure 2-10 Location and Appearance of FAN

2.5.2. Air Baffle

Air Baffle is the sucking holes of drawing in the external air to radiate the internal air. The
air baffles are located in 3 places of MARU 220 as shown in the figure 2-11.

Figure 2-11 Location and Appearance of Air Baffle

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Chapter 3. Hardware Description

Chapter 3. Hardware Description


3.1. ASU
3.1.1. Appearance of ASU

Figure 3-1 Appearance of ASU

Ports
Port Name Description

J411 ASU input port: LSB COS is inputted from PDC.

J412 ASU input port: LSB SIN is inputted from PDC.

J413 ASU input port: USB COS is inputted from PDC.

J414 ASU input port: USB SIN is inputted from PDC.

1,3,5 ~ 45,47 ASU output port: Connected to each branched LSB / USB COS output port
antenna.

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Chapter 3. Hardware Description

2,4,6 ~ 46,48 ASU output port: Connected to each branched LSB / USB SIN output port
antenna.

CN411 Power and switch control signal input

3.1.2. ASU Block Diagram

ASU consists of 1 TM (Toggling Module) and 4 SMs (Selection Module).


The following block diagram shows the interfaces between units for the major signals.

ASU
Side Band ANT
12
12
12
SM
12

RS422 - SIN SEL A/B [3..0]


RS422 - COS SEL A/B [3..0]
CSU RS422 - SIN Toggle A/B
RS422 - COS Toggle A/B

+5V TM
+28V DC
PSU DC -24V

USB COS
LSB COS
PDC USB SIN
LSB SIN

Figure 3-2 ASU Blocks & Interfaces

3.1.3. Major ASU Parts

Part Name P/N Description

Pin Diode UM9401 Antenna Switch Diode

Inverter 74HC14 Hex Inverting Schmitt Trigger

Decoder 74HC4514D 1-of-16 Decoder


3.1.4. ASU Operations

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Chapter 3. Hardware Description

Figure 3-3 Internals of ASU

A total of 48 sideband antennas are classified into 4 groups (12 each) and are assigned to
each SM.

 SM1: Odd numbered antennas from #1 to #23 (A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23)  SM2: Odd numbered antennas from #25 to #47 (A25, A27,
A29, A31, A33, A35, A37,
A39, A41, A43, A45, A47)  SM3: Even numbered antennas from #2 to #24 (A2, A4,
A6, A8, A10, A12, A14, A16,
A18, A20, A22, A24)  SM4: Even numbered antennas from #26 to #48 (A26, A28,
A30, A32, A34, A36, A38, A40, A42, A44, A46, A48)

The 4 sideband antenna signals (LSB COS, LSB SIN, USB COS, USB SIN) inputted to ASU
are distributed to each sideband antenna according to the following rules.

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Chapter 3. Hardware Description

 For the odd-numbered antenna, only the COS signals are supplied to SM1 and SM2. 
For the even-numbered antennas, only the SIN signals are supplied to SM3 and SM4.
 Within each SM, only one sideband antenna is selected at a time.
 SM1 and SM2 are always selected at the same time and the sideband signals different
from each other are exchanged. For the first 1/60 second, the LSB signal is supplied to
SM1 and the USB signal to SM2 and for the next 1/60 second, the USB signal is supplied
to SM1 and the LSB signal to SM2.
 Likewise, SM1 and SM2 are always selected at the same time and the sideband signals
different from each other are exchanged at a fixed cycle. For the first 1/60 second, the
LSB signal is supplied to SM3 and the USB signal to SM4 and for the next 1/60 second,
the USB signal is supplied to SM3 and the LSB signal to SM4.

According to such rules, the following control signals are supplied to ASU by each SIN and
COS to distribute 4 input signals to each sideband antenna.

 Toggle Signal: The 1-bit signal supplied to TM in order to periodically swap the USB
and LSB signals inputted to SM
COS Toggle SM1 SM2 SIN Toggle SM3 SM4

0 LSB USB 0 LSB SIN USB SIN


COS COS
1 USB LSB 1 USB SIN LSB SIN
COS COS

 Selection Signal: A 4-bit signal that allows selecting a specific number of antenna within
each SM
COS SEL SM1 SM2 SIN SEL SM3 SM4

0 [00002] A1 A25 0 [00002] A2 A26


1 [00012] A3 A27 1 [00012] A4 A28
2 [00102] A5 A29 2 [00102] A6 A30
3 [00112] A7 A31 3 [00112] A8 A32
4 [01002] A9 A33 4 [01002] A10 A34
5 [01012] A11 A35 5 [01012] A12 A36
6 [01102] A13 A37 6 [01102] A14 A38
7 [01112] A15 A39 7 [01112] A16 A40
8 [10002] A17 A41 8 [10002] A18 A42
9 [10012] A19 A43 9 [10012] A20 A44
10 [10102] A21 A45 10 [10102] A22 A46

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Chapter 3. Hardware Description

11 [10112] A23 A47 11 [10112] A24 A48


12 ~ 15 x x 12 ~ 15 x x

3.1.5. USB/LSB Turnover Module (TM)

Figure 3-4 Internals of ASU-TM

ASU-TM consists of the RF switch of using the PIN diode, control signal level conversion
circuit and DC bias control signal for the pin diode.

Since the control signals received from CSU are the differential signals defined according to
the RS-422 standards, they are converted into the TTL signal level within the level
conversion circuit.

According to the level converted control signals, either +5V or -24V bias voltage is outputted
from the DC bias circuit.

The RF path corresponding to this voltage is formed in the PIN diode RF switch.
Configuration of SIN Path

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Chapter 3. Hardware Description

Figure 3-5 Internals of SIN Path

Configuration of COS Path

LSB COS

Figure 3-6 Internals of COS Path

TM Operations

ASU-TM delivers the 4 sideband signals supplied from PDC to the 4 SMs through a toggling
process.
This phrase explains about the delivery process of the 2 SIN signals from the 4 signals and
the delivery process of COS signals is skipped as it is similar to that of COS signals.

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Chapter 3. Hardware Description

1) According to the timing signal supplied from MSG, CSU transmits the control signal for
selecting the sideband antenna pair to ASU. The level of this signal, as a differential
signal, is identical to the RS422 signal level.
2) The RS422 receiver U5 of ASU receives the control signal.
3) The signals that have passed U5 is changed to the TTL level of signals and the toggle
signal among these signals is inputted as the Schmidt trigger inverter IC U1.
4) According to the inputted TTL level, Q4 and Q1 or Q5 and Q2 outputs either +5V or 24V
and supplies the bias voltages to the D3, D4, D7, and D8 diodes.
5) When the toggle signal is ‘0,’ Q2 is toggled off as the bias voltage is not applied to Q5.
Accordingly, -24V is outputted from the Q2 collector. Contrarily when the toggle signal
is ‘1,’ +5V is outputted from the Q2 collector as Q5 and Q2 are toggle on.
6) On the other hand, the logic is toggled by the inverter U1C in the input terminal.
Therefore, the Q2 output becomes -24V if the Q1 output +5V and reversely, the Q2 output
becomes +5V if the Q1 output is -24V.
7) The following table shows the RF paths and switching statuses according to the toggle
signals.

TR
Toggle RF Path Input Diode Status Output Diode Status
Output
Signal
USB LSB Q1 Q2 D1 D2 D5 D6 D3 D4 D7 D8

-
0 RFA RFB +5V 24V ON OFF OFF ON ON OFF OFF ON
-
1 RFB RFA +5V OFF ON ON OFF OFF ON ON OFF
24V

3.1.6. Selection Module (SM)

Each SM consists of the 1-input and 12-output PIN diode switch circuits. One of 12 paths is
selected according to the selected control signals. The phases of RF paths are the same no
matter what path is selected.

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Chapter 3. Hardware Description

Figure 3-7 Internals of ASU-SM

The signal flows of ASU-SM circuit will be the same as below.


1) The 4 binary selection signals (A0, A1, A2 and A3) that have passed through the RS422
receiver of TM are converted to the TTL signal levels and inputted to SM.
2) The 4 signals received from SM are decoded on U4 and converted to the 12 switching
control signals (S1~S12).
3) Each PIN diode is biased according to the switch control signals and one path selected out
of the 12 RF paths is toggled on and the rest are toggled off.

3.1.7. Antenna Selection Signal Decoding

The on/off operations of ASU-SM switching circuit are controlled by the selection signals
supplied from CSU. The sideband antenna number selected according to the timing generated
from MSG is binary-encoded. This selection signal is separately supplied each with 4-bits
for the odd number (for COS) and 4-bits for the even number (for SIN).

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Chapter 3. Hardware Description

ASU-SM decodes the binary-coded antenna selection signal by using the 4-to-16 binary
decoder IC U4.

Figure 3-8 Antenna Selection Signal Decoding

The following shows the Truth Table for the selection of signals.

A0 0 1 0 1 0 1 0 1 0 1 0 1

A1 0 0 1 1 0 0 1 1 0 0 1 1

A2 0 0 0 0 1 1 1 1 0 0 0 0

A3 0 0 0 0 0 0 0 0 1 1 1 1

Select S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12

3.1.8. Input Signal Timing

The antenna selection is made by the COS and SIN antenna selection signals according to
the sequence of the following figures.

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Chapter 3. Hardware Description

COS Antenna SIN Antenna


Select Select

COS SEL Ant. Pairs SIN SEL Ant. Pairs

0000 1, 25 0000 2, 26

0001 3, 27 0001 4, 28

0010 5, 29 0010 6, 30

0011 7, 31 0011 8, 32

0100 9, 33 0100 10, 34

0101 11, 35 0101 12, 36

0110 13, 37 0110 14, 38

0111 15, 39 0111 16, 40

1000 17, 41 1000 18, 42

1001 19, 43 1001 20, 44

1010 21, 45 1010 22, 46

1011 23, 47 1011 24, 48

COS Antenna Pairs SIN Antenna Pairs

Figure 3-9 Switching Signals and Antenna Selections


The following figure shows the timings of the toggling signals and antennal selection signals
for the COS paths.

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Chapter 3. Hardware Description

Figure 3-10 Timings of the COS Antenna Switching Signals

The following figure shows the toggling signals and antenna selection signals for the SIN
paths.

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Chapter 3. Hardware Description

Figure 3-11 Timings of the SIN Antenna Switching Signals

3.2. PDC
3.2.1. Appearance of PDC

PDC Front Panel

Figure 3-12 shows the front panel of PDC.

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Chapter 3. Hardware Description

Figure 3-12 Front Panel of PDC

LED Descriptions
LED Name Color Description

ON: When power is normally supplied


POWER Green
OFF: When power is interrupted

ON: When the TX1 output is connected to the antenna


TX1 Green
OFF: When the TX1 output is connected to the dummy load

ON: When the TX2 output is connected to the antenna


TX2 Green
OFF: When the TX2 output is connected to the dummy load

Test Ports
Port Name Description

USB COS The test port that has coupled the USB COS path signals

LSB COS The test port that has coupled the LSB COS path signals

USB SIN The test port that has coupled the USB SIN path signals

LSB SIN The test port that has coupled the LSB SIN path signals

CAR FWD The incident wave test port that has coupled the carrier wave path signals

CAR RVS The reflected wave test port that has coupled the carrier wave path signals

PDC Back Panel

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Chapter 3. Hardware Description

Figure 3-13 PDC Back Panel

OUTPUT
Port Name Description

LSB SIN As the connector that the LSB SIN signals of Active TX, connected to ASU.

USB SIN As the connector that the USB SIN signals of Active TX, connected to ASU.

LSB COS As the connector that the LSB COS signals of Active TX, connected to ASU.

USB COS As the connector that the USB COS signals of Active TX, connected to ASU.

CAR OUT As the connector that the carrier wave signals of Active TX, connected to the
carrier wave antenna.

DUMMY LOAD As the connector that the carrier wave signals of Standby TX, connected to the
dummy load.

TX1/TX2 INPUT
Port Name Description

USB COS As the USB COS signal input connector, connected to the COS output of the USB
SMA.

USB SIN As the USB SIN signal input connector, connected to the SIN output of the USB
SMA.

CAR As the carrier wave signal input connector, connected to the CMA output of the
TX.

LSB COS As the LSB COS signal input connector, connected to the COS output of the LSB
SMA.

LSB SIN As the LSB SIN signal input connector, connected to the SIN output of the LSB
SMA.

INTERFACE
Port Name Description

CN401 As the PDC control signal interface connector, connected to CSU.

Adjust Points
Name Description

CAR Adjust the sensitivity of the circuit that detects the abnormality of carrier wave
antenna.

SIN Adjust the sensitivity of the circuit that detects the abnormality of even numbered
(SIN) sideband antenna.

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Chapter 3. Hardware Description

COS Adjust the sensitivity of the circuit that detects the abnormality of odd numbered
(COS) sideband antenna.

3.2.2. Major PDC Parts

Part Name P/N Description

Coaxial Relay C1-2-LSI Insertion Loss: 0.2dB max


Isolation: 90dBHandling
Power: 200 W max
Impedance: 50 Ohm
Actuator Voltage: +28V DC
Switching Type: Latching, Including Indicator function

RF Relay ARE104H Insertion Loss: 0.2dB max


Isolation: 60dB min
Handling Power: 200 mW max
Impedance: 50 Ohm

Isolator VFB1170 Insertion Loss: 0.5dB max


Isolation: > 20dBc
Handling Power: 25 W max
Impedance: 50 Ohm

Isolator VFB1171 Insertion Loss: 0.5dB max


Isolation: > 20dBc
Handling Power: 250 W max
Impedance: 50 Ohm

RMS Detector AD8361 Input range: 30dB


Supply operation: +2.7 ~ +5.5V

3.2.3. PDC Operations

Figure 3-14 shows the internal Configuration of PDC.

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Chapter 3. Hardware Description

Figure 3-14 PDC Internals


3.2.4. PDC-CAR

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Chapter 3. Hardware Description

Figure 3-15 PDC-CAR Internals

The signal flow of PDC-CAR circuit shall be followed as below.

1) The carrier wave signals generated on each CMA of two TXs (TX1 and TX2) is supplied
respectively to the CAR input connectors.
2) One of two carrier wave signals is sent to the isolator passing through the coaxial relay
and the other one is sent to the external high power dummy load. The coaxial relay
operates in the double-pole double-throw (DPDT) method to exchange these signal paths.
3) The signals that have passed through the isolator are sent to the carrier power detector
(CPD). Isolator only allows the traveling wave passing through while removing the
reflective wave.
4) The carrier wave signals sent to CPD are sent to the antenna after passing through the
35dB dual directional coupler and low pass filter circuit.
5) One pair (forward and reverse) of the signals sampled from the coupler is supplied to the
test port on the front panel of PDC.
6) Another pair of the signals sampled from the coupler is converted to the DC signal after
passing through the RMS detectors U6 and U15 and is outputted as a maximum of 5V DC
via the OP AMP buffer U1 (FWD DET and RVS DET in the above figure).
7) The FWD DET and RVS DET signals are sent to MSG and MON through the IF board.
The FWD DET signal is used to measure the carrier wave output level and the RVS DET
signal is used to detect the antenna problem.

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Chapter 3. Hardware Description

3.2.5. PDC-SB
Sideband
Isolator
In Out

LPF 30 dB CPL
SB1 (TX1) RY1
Output
RVS DET
U2 U8 U3-B

SB2 (TX2) RY2 U5


10 KHz Signal
U6 U7
50 ohm
Term1 Term

U1 FWD CPL
FWD DET
U3-A

Figure 3-16 Internals of PDC-SB

The signal flow of PDC-SB circuit can be explained as below.


A total of 4 PDC-SBs are used by the respective sidebands (USB-SIN, USB-COS, LSBSIN,
LSB-COS) and all 4 of them are constructed with the same circuit. Here, it is explained while
referring to one PDC-SB.

1) The sideband signals generated on each SMA of two TXs (TX1 and TX2) is supplied
respectively to the back plane of PDC.
2) One of two sideband signals is sent to the isolator passing through the HF relays RY1 and
RY2 and the other one is sent to the internal small power dummy load. Two RF relays
RY1 and RY2 constructs a switch of using the double-pole double-throw (DPDT) method
to exchange these signal paths.
3) The sideband signals that have passed through the isolator are sent to the sideband power
detector (SPD). Isolator only allows the traveling wave passing through while removing
the reflective wave.
4) The sideband signals sent to SPD are sent to ASU via LPF.
5) The reflective wave signals sampled from the coupler RVS port are amplified on the
MMIC AMP U8 and converted to the DC level on the RMS detector IC U2. The
DCconverted signals are sent to the abnormal antenna detection circuit via the OP-AMP
buffer U3B. The abnormal antenna detection circuit compares the level of this reflective
wave signal with the pre-defined reference value and checks the status of sideband
antenna.
6) The traveling wave signals sampled from the coupler FWD port are divided into two after
passing through the 2-way divider. One of two divided signals is supplied to the test port
on the front panel of PDC. The other one is converted to the DC level on the RMS detector
IC U1. The signals converted to DC are outputted via the OP AMP U3A (FWD DET in
the above figure).
7) These signals are sent to MSG and MON via the IF board and used to measure the
sideband output level.

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Chapter 3. Hardware Description

3.2.6. Antenna Fault Detection Circuit

The status of an antenna can be checked by converting each reflective wave signal sampled
from the 3 paths of CAR, USB COS and USB SIN into DC while using the coupler within
PDC and by comparing this DC level with the reference voltage while using a voltage
comparator. Carrier wave divides the FWD DET voltage to use it as the reference voltage
and sideband divides the fixed DC voltage to use it as the reference voltage.

The abnormal antenna detection circuit is constructed on the respective I/F (interface) and
ADJ (adjust) boards as in the below.
 I/F board: Include the voltage comparator IC and output level conversion circuit.
 ADJ board: Include the potentiometer that can vary the voltage applied to the
comparator by dividing the reference voltage and the LED indicator circuit that indicates
the antenna status.

The potentiometer on the ADJ board should be adjusted so that it turns off the LED when
connected to the antenna with the VSWR 1.5:1 or below.

Figure 3-17 Internals of Antenna Fault Detection Circuit

3.3. CMA
3.3.1. Appearance of CMA

Front Panel of CMA

Figure 3-18 shows the front panel of CMA.

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Chapter 3. Hardware Description

Figure 3-18 Front Panel of CMA

LED Indicator Lamp


LED Name Color Description

ON: When power is normally supplied


POWER Green
OFF: When power is interrupted

ON: When the PLL of SYN is not normally operating


PLL FAIL Red
OFF: When the PLL of SYN is normally operating

ON: When the RF signal is normally outputted


CAR ON Green
OFF: When the RF signal is not normally outputted

Port
Port Name Description

FREQ The test port for measuring the carrier wave oscillating frequency as a SYN output

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Chapter 3. Hardware Description

CAR ENV The test port for checking the carrier wave modulation status as the Envelop
output of the carrier wave RF output

Rear Panel of CMA

Figure 3-19 Rear Panel of CMA

Input/Output Port
Port Name Description

J311 Connect to PDC as the RF output of CMA.


CAR OUT

J312 CAR The test port combined with the RF output of CMA
CPL

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Chapter 3. Hardware Description

J313 As the reference clock of the carrier wave, it is used in generating the upper
sideband RF signal synchronized at this reference clock after being sent to the
USB SMA.

J314 As the reference clock of the carrier wave, it is used in generating the lower
sideband RF signal synchronized at this reference clock after being sent to the
LSB SMA.

J315 As the RF output signal of SYN, it is used as the reference signal for the upper
sideband RF phase synchronization after being sent to the USB SMA.

J316 As the RF output signal of SYN, it is used as the reference signal for the lower
sideband RF phase synchronization after being sent to the LSB SMA.

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Chapter 3. Hardware Description

3.3.2. CMA Block Diagram

Figure 3-20 Internal Blocks of CMA and SMA

3.3.3. Major CMA Parts


Part Name P/N Description

TCXO TX-C1-1.0F1 TCXO, 5V, 20MHz, 1.0ppm

Prescaler MC12080 1/40 Frequency Prescaler

PLL Module KSP-113E Phase Locked Loop, LMX2326, 108 MHz ~ 118 MHz

Phase Shifter JSPHS-150 Mini-Circuits

Phase Detector SYPD-2 Mini-Circuits

MMIC AMP AM1 60-3000 MHz, 14 dB Gain, 2.4 dB NF, +39 dBm OIP3

MMIC AMP AH31 50-1000MHz, 19 dB Gain, +22dBm P1dB, +42dBm OIP3

PIN Diode HSMP-3814 AM Modulator

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Chapter 3. Hardware Description

MOS FET MRF136 Pre-Drive

MOS FET MRF171A Drive

MOS FET BLF248 Final PA

IC MAX4272 Hot-Swap Control, Positive, Low-Voltage

IC MAX5900 Hot-Swap Control, Negative, High-Voltage

IC MAX5902 Hot-Swap Control, Positive, High-Voltage

IC DS1620 Digital Temperature Sensor

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Chapter 3. Hardware Description

3.3.4. Frequency Synthesizer (SYN)

Figure 3-21 Internals of SYN

Generate the reference 20 MHz clock signal by using TCXO X1. The PLL module U1 creates
the carrier wave RF signal that holds the frequency range of 108 MHz~118 MHz by using
this signal. The output frequency of PLL can be set in a unit of 50 kHz.

For the frequency synchronization between CMA and both side SMAs, the 20 MHz clock
signal generated on TCXO X1 is sent to the LSB SMA and USB SMA units via the 2-way
divider. Each SMA receives this clock signal and uses it as the reference signal source of the
PLL circuit to synthesize the USB and LSB frequencies.

The output signal of the PLL module U1 is amplified by 15dB on the MMIC AMP U2 after
passing through the LPF circuit consisted of LC in order to remove the harmonic element.

The U2 output is amplified by +15dB on the MMIC Amp U4 after passing through the 2way
divider and BPF F1. F1 is the band pass filter (BPF) that has the center frequency of 113MHz
and the pass bandwidth of 10 MHz.

The output signal of U4 is divided into two parts via the 2-way divider and one of them is
sent to MOD. This is a clean carrier wave RF signal with the size of 10 dBm. The other one
is further divided into three parts via two 2-way dividers after being amplified by +15 dB on
the MMIC AMP U5. Two of these are sent to the LSB SMA and USB SMA for the phase
synchronization and the one left is outputted to the test port (BNC connector) on the front
panel for the repair/maintenance purpose.

In order to monitor the oscillating frequency of SYN, the PLL output signal is sent to the
MON unit after dividing it into 40 demultiply on the Frequency Prescaler IC U3. The MON
unit checks the output frequency of SYN by using this signal. Since the MON unit can’t
count the VHF frequency directly, it transmits by dividing it into 40 demultiply without
sending the PLL output frequency in that way.

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Chapter 3. Hardware Description

.
The carrier wave RF signals (108~118 MHz) from SYN is divided into three parts via the 3-
way divider after inputting to MOD. Each divided signal is used in the following ways.

 The 1st signal is delivered to CPA after passing through the phase adjust circuit and
modulation circuit and the filter circuit and amplification circuit. This flow is the main
RF path of MOD.
 As the automatic phase adjust reference signal, the 2nd signal is applied to the phase
detector U16 input via the MMIC AMP U15.
 The 3rd signal is used for checking the circuit (internal T/P).

The RF main path signal is amplitude-modulated on the PIN diode D1 and D2 after being
phase-adjusted to the Phase Shifter U7. The AM-modulated signal is filtered on the BPF F2
after being amplified by +15 dB on the MMIC U9. The BPF output signal is sent to CPA
after being amplified by +20 dB on the MMIC U10 and filtered on the LPF consisted of LC.

While the phase error may occur in the modulation or power amplification process on the RF
main path, this error can be compensated by using the automatic phase adjust circuit. The
automatic phase adjust circuit uses the Closed-Loop Control method and consists of the phase
detector U16 and phase detector U7. There are two signals within the phase detector U16.
One is the reference signal for comparison and the other is the RF signal fed back from the
CPA output. The voltage corresponding to the phase difference of two RF signals are
outputted on U16. This voltage is supplied to the Phase Shifter U7 to correct the phase error.

The amplitude modulation process is also made by using a similar the Closed-Loop Control
method. The modulation circuit consists of the PIN diode D1 and D2. Only by this signal,
signals are greatly distorted due to the nonlinear characteristics of PIN diode. In order to
repair it, the control signal made through the feedback circuit is applied to the PIN diode
circuit rather than directly applying the modulation signal to the PIN diode circuit. The

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Chapter 3. Hardware Description

feedback circuit consists of the Envelope detection circuit D4 and OP AMP U12. The
Envelope Detector D4 detects the carrier wave Envelope from the RF signal sampled from
the final CMA output. This Envelope signal is inputted to the comparator consisting of OP
AMP U12 and compared with the modulation signal. Here, the modulation signal is a
composite signal that is generated on MSG and supplied to CMA. The voltage corresponding
to the amplitude error is outputted on U12. This signal is inputted to the PIN diode and used
as the control signal of modulation circuit.

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Chapter 3. Hardware Description

3.3.6. Carrier Power Amplifier (CPA)

Figure 3-23 Internals of CPA

The signal modulated from MOD is inputted to CPA. CPA consists of a 3-terminal amplifier
and its overall gain is approximately 38 dB.
The input signal is amplified by 15dB on the 1st RF driver Q9 via the -3dB attenuator. After
passing through the -1dB attenuator for matching the impedance between terminals, it is
amplified by 16dB on the 2nd amplifier Q10.

The output signal of Q10 is power-amplified on the 3rd amplifier U1 and U2. The final power
amplification is done in parallel on two amplification circuits consisted of U1 and U2. U1
and U2, as the composite elements that are included in one package of two MOSFETs, which
are symmetric from each other, they construct their respective push-pull amplification
circuits.

Two parallel signals that have the phases differing by 180° are needed in the push-pull
amplification circuit. Since the signals outputted from the 2-way divider are the unbalanced
signals, they are converted into the balanced signals by using the Float Balun consisted of a
coaxial cable. In the same way, the amplified output is merged and outputted in the 2-way
combiner after being respectively converted into the unbalanced signals via the
balanceunbalance conversion Float Balun.

The final power-amplified signal is outputted to the external part of CMA via the -40 dB
Directional Coupler. The directional coupler is used to obtain the feedback signal necessary
for the modulation circuit.

3.3.7. Other Circuits

As for the CMA power source, DC +28V, +7V, +15V and -15V are used. +28V is supplied
to the power amplification circuit of CPA. +15V and -15V are supplied to the analog circuit
such as the OP AMP. +7V is supplied simultaneously to the MMIC amplification circuit and

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Chapter 3. Hardware Description

part of it is supplied to the rest of circuits after being converted via the 3-way terminal
constant-voltage IC.

For the On/Off control of the carrier wave output, it turns On/Off the +7V power for the
MOD MMIC amplification circuits U9, U10, U15 and U29 and the +28V power for the
respective MOSTFET Q9, Q10, Q11 and Q12 bias voltages of CPA. The On/Off control of
the power is made through using the On/Off control signal input of the Hot-Swap control
circuits U19 and U23.

The digital temperature sensor U24 is used to monitor the internal temperature of power
amplifier. The measured temperature data is sent to MSG via the 3-lined serial interface
(SPI).

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Chapter 3. Hardware Description

3.4. SMA
3.4.1. Appearance of SMA

Front Panel of SMA

Figure 3-24 shows the front panel of SMA.

Figure 3-24 Front Panel of SMA

LED Indicator Lamp


LED Name Color Description

ON: When power is normally supplied


POWER Green
OFF: When power is interrupted

ON: When the PLL circuit is not locked


PLL FAIL Red
OFF: When the PLL circuit is normally locked

ON: When the COS RF signal is normally outputted


COS ON Green
OFF: When the COS RF signal is not outputted

ON: When the SIN RF signal is normally outputted


SIN ON Green
OFF: When the SIN RF signal is not outputted

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Chapter 3. Hardware Description

I/O Ports
Port Name Description

FREQ The port for measuring the sideband RF frequency

COS ENV The port for measuring/testing the Envelope of COS RF output signal

SIN ENV The port for measuring/testing the Envelope of SIN RF output signal

Rear Panel of SMA

Figure 3-25 Rear Panel of SMA

Ports
Port Name Description

J321 COS OUT - COS output port. Connected to the COS input of PDC.

J322 COS CPL – The test port coupled to the COS output

J323 SIN OUT - SIN output port. Connected to the SIN input of PDC.

J324 SIN CPL – The test port coupled to the SIN output

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Chapter 3. Hardware Description

J325 REF CLK – PLL reference clock signal 20 MHz. Connected to the TCXO output
of CMA.

J326 CAR PHASE – Phase comparator input port. Connected to the SYN output of
CMA.

3.4.2. SMA Configuration

PSU

+28V, +15V, +7V, -15V GND

MSG SMA CMA

PLL LOCK DETECTOR


REF CLOCK
PLL DATA
SYN
BLENDING CARRIER FREQ.

10KHz

ALARM DATA
MON
ENABLE MOD

SIDEBAND F/D
LCU
SBA

PRESENCE
DETECTOR

SIDEBAND OUT

PDC

Figure 3-26 Blocks and Interfaces of SMA

3.4.3. Major SMA Parts


Part Name P/N Description

PLL Module KSP-113E Phase Locked Loop, LMX2326, 108 MHz ~ 118 MHz

Phase Shifter JSPHS-150 Mini-Circuits

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Chapter 3. Hardware Description

Phase Detector SYPD-2 Mini-Circuits

MMIC AMP AM1 60-3000 MHz, 14 dB Gain, 2.4 dB NF, +39 dBm OIP3

MMIC AMP AH31 50-1000MHz, 19 dB Gain, +22dBm P1dB, +42dBm OIP3

PIN Diode HSMP-3814 AM Modulator

Mixer ESMD-C50H Double Balanced Mixer

Prescaler MC12080 1/40 Frequency Prescaler

MOS FET MRF136 Pre-Drive

MOS FET MRF171A Drive

IC MAX4272 Hot-Swap Control, Positive, Low-Voltage

IC MAX5900 Hot-Swap Control, Negative, High-Voltage

IC MAX5902 Hot-Swap Control, Positive, High-Voltage

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Chapter 3. Hardware Description

The SYN for SMA is basically identical to the SYN used for CMA except for some part.
Hence, only the differences are described. Please refer to the paragraph 3.3.4 for the detailed
circuit theory.

While the CMA SYN uses the signal self-oscillated within TCXO as the reference clock,
SMA doesn’t hold its built-in oscillating circuit and uses it as the reference clock of the PLL
circuit after receiving the signal generated within CMA. This is to make the output
frequencies of CMA and SMA to be exactly synchronized with each other.

The SMA SYN is programmed so that the output frequency always becomes 10kHz higher
(USB) than or lower (LSB) than the setting frequency of CMA. Hence, the carrier wave
output frequency and sideband output frequency of MARU 220 DVOR are always keeping
10 kHz intervals. Although it differs by 40 Hz from the sub-carrier center frequency of 9960
Hz that is stipulated from the ICAO Annex 10, there is no problem in its practical use since
it falls within the permissible range of below 1%, which is set by the ICAO Annex 10.

The Doppler VOR that uses Double Sideband (DSB) requires maintaining not only the
synchronization of two sideband signal frequencies but also the phase synchronization
between two signals. SMA includes the circuit for the phase synchronization. The output
signal of SMA-SYN is mixed with the output signal of CMA-SYN on the double balanced
mixer (DMB) U8 and is frequency-converted to the intermediate frequency (IF) signal of 10
kHz. Through the above process, two 10 kHz intermediate signals obtained respectively from
USB SMA and LSB SMA are sent to MSG and phase-compared from each other. If the result
differs from the reference value set previously, the control software of MSG adjusts the
voltage value applied to the phase adjusters U4 and U5 and automatically corrects the errors.

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Chapter 3. Hardware Description

3.4.5. Modulator (MOD)

As for the SMA modulator (MOD), the bandwidth modulation circuit constructed in the same
way is used respectively for COS and SIN. Two modulators are exactly identical and it is the
same as the one used in CMA. Hence, only the differences are described here.
Please refer to the paragraph 3.3.5 for more detailed circuit theory.

The RF signals applied to the COS and SIN modulators of SMA are exactly the same. Two
signals divided by using the 3-Way Divider from the output of SMA SYN are applied
respectively to the COS and SIN modulators. Two signals are identical in their phases and
bandwidths.

The modulation signal applied to SMA is the blending signal supplied from MSG. Blending
is used to obtain electrically the continuous rotating effects of sideband antenna and is
divided into those of SIN and COS. The sideband RF signal is amplitude-modulated near to
the modulation depth 100% by the blending signal from SMA MOD.

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Chapter 3. Hardware Description
3.4.6. Sideband Amplifier Unit
SMA_COS OUT
(SBA) 108 ~ 118MHz / +33 ~ +43cBm

SBA_COS
Feedback In
Drv. PA To USB_COS FEEDBACK
MRF136 MRF171A 113.51MHz / 23 ~ 13dBm
+15dB +16 dB
From MOD_COS 40dB
108 ~ 118MHz / +5 ~ +15dBm
Q9 Q10

DC Enable
SMA_COS OUT
108 ~ 118MHz / +33 ~
+43cBm

SBA_SIN
Feedback In
Drv. PA
MRF136 MRF171A To USB_SIN FEEDBACK
+15dB +16 dB 113.51MHz / 23 ~ 13dBm
40dB
From MOD_SIN
108 ~ 118MHz / +5 ~ +15dBm
Q11 Q12

DC Enable

Figure 3-29 Internals of SBA

The sideband signals modulated on two MODs of COS and SIN are inputted respectively to
the COS SBA and SIN SBA. The COS SBA and SIN SBA are constructed with the identical
circuit. Hence, it is explained here only with the SBA for SIN.

SBA is constructed with a 2-way amplifier and the total gain of the respective amplifiers is
31dB. The inputted sideband RF signal is amplified by 15dB on the 1st RF driver Q11. Then,
it is amplified on the 2nd amplifier Q12 by 16dB to have its maximum signal of +43dBm.

The final power-amplified signal is outputted to the external part of SMA via the -40 dB
Directional Coupler. The directional coupler is used to obtain the feedback signal necessary
for the modulation circuit.

3.4.7. Other Circuits

As for the SMA power source, DC +28V, +7V, +15V and -15V are used. +28V is supplied
to the power amplification circuit of SBA. +15V and -15V are supplied to the analog circuits
like OP AMP. While +7V is supplied to the MMIC amplification circuit, a part of it is
converted to +5V via the 3-way terminal constant voltage IC and supplied to the rest of
circuits.

In the same way as the carrier wave, the +7V power of U13, U14, U7, U26, U27 and U30
and the gate bias +28V power of MOSFET Q9, Q10, Q11 and Q12 are controlled for the

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Chapter 3. Hardware Description

On/Off control of sideband output. The power On/Off control is made by using the On/Off
control signal input pin of the hot-swap control circuits U19 and U23.

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Chapter 3. Hardware Description

3.5. LCU
3.5.1. Appearance of LCU

Front Panel of LCU

Figure 3-30 Front Panel of LCU

LEDs
LED Name Color Description

ON: When the power is normally supplied


POWER Green
OFF: When the power is interrupted

TxD Green When LCU is transmitting data to LMMS

RxD Green When LCU is receiving data from LMMS

FAULT Red When a reset or trouble of LCU has occurred

Switches
Name Description

RESET The switch that resets LCU CPU

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Chapter 3. Hardware Description

3.5.2. LCU Functions

Local Control Unit (LCU) is responsible for the communication interfaces among user and
the respective control/monitor units ((MSG1, MSG2, MON1, and MON2) within the system.

User through the interfaces such as LMMS / RMMS, RCMU or CSP sends a control/query
command to LCU and LCU sends it to the corresponding MSG or MON unit. The executed
result is sent to the user in the opposite path.

The information such as the alarm detected from the system or the system parameters
collected and analyzed is also sent to LMMS/RMMS, RCMU/RMU via LCU for the display
or indicated directly on the CSP attached on the system cabinet.

The interfaces between the external devices such as LMMS / RMMS or RCMU / RMU and
the respective control/monitor units are made through the asynchronous serial data
communication. However, the CSP attached on the system cabinet is directly controlled by
LCU without going through these communication interfaces.

Additionally, LCU carries out the following functions.


 Collect and record system logs
 Control the graphic LCD, LED lamp and keypad, which are attached on CSP 
Select the Test Signal Generator (TSG) test signal  Measure and
monitor the voltage and current of PSS
 Measure the MAS temperature and control the FAN according to the
temperature  Monitor the attachment/detachment of each unit attached on
the system cabinet  Generate the warning sound and play the IDENT
tone

Figure 3-31 Internals of LCU

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Chapter 3. Hardware Description

3.5.3. Major LCU Parts


Part Name P/N Description

CPU MC68302 M68000 Core, Integrated Multiprotocol Processor

RAM K6T4016 256k x 16 bit Low Power CMOS Static RAM

EPROM M27C4002 4 Mbit (256Kb x 16) UV EPROM

Flash Memory M29F016 16 Mbit (2Mb x 8, Uniform Block) 5V Supply Flash Memory

UART TL16C552 Dual Asynchronous Communications Element with FIFO

EPLD EPM7128 128 Macrocells, 100 I/O pins, Programmable Logic Device

RTC M48T02 Real Time Clock,16 kbit (2kb x 8) SRAM

Microprocessor ATmega16 8-bit AVR microprocessor with 16k Bytes ISP Flash

Modem MT5634 Socket Modem, V.92/56k V.34/33.6k Embedded Modem

Reset IC DS1232 Micro Monitor, Reset, Watchdog Timer / Monitor

3.5.4. Microprocessor and Peripheral Circuits

Figure 3-32 LCU Microprocessor

U300 is the microprocessor for the main control of LCU. U300 is based on the M68000 core
and the 1152-byte dual port RAM, programmable timer, serial communication controller
(SCC), and 24-bit general GPIO are integrated within the chip. The data and address buses
of U300 are connected to the peripheral devices through the 3-state buffer U500-U504.

The crystal oscillating circuit X300 supplies a clock of 29.4912 MHz to U300.

U301, as the microprocessor monitor circuit IC, includes the reset signal generation circuit,
power monitor circuit and the watchdog timer. U301 supplies a reset signal to the
microprocessor U300 and at the same time, it monitors whether U300 operates normally.
The cases that U301 outputs a reset signal follow as below.

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Chapter 3. Hardware Description

1) When power is turned on


2) When the reset switch is pressed for 250ms or more
3) When the Address Strobe (AS) of U300 is not outputted for 1.2 seconds or more
(Watchdog timer – microprocessor error)
4) When the Vcc voltage goes below 4.5V (abnormal power voltage)

When the reset signal of U301 is outputted, the FAULT LED lamp of LCU front panel is
lighted.
Since the /RESET output signal of U301 is connected to the /OE pin of the bus switches
U1400 ~ U1408 via Q1400, the LCU input/output signal line is separated from the backplane
during the reset period.

LCU uses the following storage devices different from each other. All the rest of storage
devices except for the serial EEPROM are positioned within the memory space of the
microprocessor U300.

 EPROM U600 and U601: Store the program code and data 
SRAM U602: Store the temporary data used during the program execution 
FLASH Memory U603 and U604: Store the log data  EEPROM U605:
Store the non-volatile parameters

When the microprocessor U300 is initialized after receiving the reset signal, U300 executes
the program code saved in the EPROM U600 and U601.

U400 is a programmable logic device (PLD). It includes the logic circuits such as the address
decoder and GPIO port. The address decoder inside of U400 decodes the addresses for each
memory and I/O device and generates the Chip Selection Signals. The GPIO port of U400
consists of the latch circuit for the output port and the digital switch circuit for the input port.

U1105, as the Real Time Clock (RTC) IC that has built-in crystal oscillator and backup
battery, provides the standard time to the system. LCU, when saving a log data, reads the
current time from RTC IC U1105 and records the event and time of occurrence together with
the data.

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Chapter 3. Hardware Description

3.5.5. Serial Communication Control


UARTCLOCK:
14.7456MHz RS232 MSG1Communication
Driver
Data UART U900
TXD1 TXD_LOCAL Device
RS232Driver /CS_MSG1,2
RXD1 U1001 U800 RS232 MSG2Communication
Driver
U901
LMMSCommunication
Microprocessor TXD2 TXD_MON1 MSG1/2Communication
RXD2 RS232Driver RXD_MON1
U1000 UARTCLOCK:
TXD3 TXD_MON2 14.7456MHz RS232DriverU902 REM1Communication
RXD3 RXD_MON2
MON1/2Communication Data
MODEM1
/CS_REM1,2 UART
Device
Buffer U801
RS232DriverU903 REM2Communication
EPROM MODEM2
UARTCLOCK:
14.7456MHz
SRAM EPLD /CS_MSG1,2
REM1/2Communication
U400 /CS_REM1,2
PLDCLOCK: /CS_REM3,4
29.4912MHz
UARTCLOCK:
14.7456MHz RS485 REM3Communication
Driver
Data UART U1002
MicroprocessorPart PeripheralLogic Device
/CS_REM3,4
U802 RS485
REM4Communication
Driver
U1003

REM3/4Communication

Figure 3-33 Communication Port

LCU, in addition to the 3 SCCs included in U300, has asynchronous serial communication
controllers (UART) U800, U801 and U802. Hence, a total of 9 serial communication ports
are available. The usage of each port follows as below.

 U300 SCC1: RS-232C console port for LMMS


 U300 SCC2 and SCC3: Internal RS-232C communication with MON1 and MON2 
U800 UART0 and UART1: Internal RS-232C communication with MSG1 and MSG2
 U801 UART0 and UART1: Remote control through internal MODEM or RS-232C
(REM1, REM2)  U802 UART0 and UART1: Remote control through RS-
485 (REM3, REM4)

U300 SCC1 is the RS-232C port exclusively for LMMS. Although the communication speed
is initially set to 57600bps, it can be changed by user. To see visually whether the data
communication between LCU and LMMS is normally made, two LED lamps are attached
on the front panel of LCU. These LEDs are lighted on whenever U300 SCC1 transmits (TxD)
or receives (RxD) data.

Although the UART0 and UART1 of U801 is connected to the built-in socket MODEM, they
can interface directly to the RS-232C without using the built-in MODEM by a user setting.
In this case, set SW900 and SW901 to the ‘RS232C’ position and remove the builtin socket
MODEMs U1103 and U1104. In order to use the MODEM again, set SW900 and SW901 to
the ‘MODEM’ position and install the socket MODEMs U1103 and U1104.

The operation of the asynchronous serial communication controllers U800, U801 and U802
can be made by receiving the 14.7456 MHz power output from U400.

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Chapter 3. Hardware Description

The I/O process of serial communication data is made asynchronously by using an interrupt
method. If data is received from the outside, the corresponding UART requests an interrupt
from the microprocessor U300. If the interrupt request is received, the microprocessor U300
stops the code in execution for a moment and reads the data from UART by executing the
interrupt processing routine. The interrupt request signals are inputted respectively to the
microprocessor via the PB8 and PB9 pins of U300 for U800, via the PB10 and PB11 pins for
U801, and via the IRQ6 and IRQ7 pins for U802.

The microprocessor U300 monitors the RXRDY and TXRDY pins of each UART via U700
and U701. If one of these pins becomes the ‘L’ status, the microprocessor U300 executes
reading and writing the data by judging that the corresponding UART is in the state of
receiving or transmitting.

3.5.6. CSP Control

Data CSP_DATA
Buffer
/CSP_DATA_EN U1101

BUSSignal
Microprocessor /CS_Switch Buffer CSPControlSignal
BUS_Signal CS_LED1 U1102
CS_LED2
EPLD /CSP_DATA_EN
U400 /CS_Switch
PLDCLOCK: CS_LED1
CSPInterface
29.4912MHz CS_LED2
Buffer CS_LED2
/CS_RTC
Data
EPROM PeripheralLogic RTC
/CS_RTC
U1105
SRAM

RealTimeClock

MicroprocessorPart

Figure 3-34 Internals of CSP Control

LCU directly controls the LED lamp, graphic LCD and keypad on CSP.

These devices are directly connected to the lower 8-bits D0 – D7 of the CPU data bus through
the 3-state data buffer U1101.

EPLD U400 decodes the address signals of U300 and generates the respective chip selection
signals /CSLCD, /CDSWITCH, /CSLED1 and /CSLED2 for the I/O devices included within
the CSP.

The chip selection signals and other control signals from U300 is connected to CSP via the
3-state data buffer U1102.

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Chapter 3. Hardware Description

3.5.7. Generating Audible Alert and IDENT Tone Playback

Alarm MSGSPK1
MSGSPK2
MONSPK1
MONSPK2
Microprocessor
IDSound SPKOUT
AnalogMUX Amp
U1106

Data Latch
U707
CS_CALSIG
AudioAMP
Buffer

EPROM

MicroprocessorPart IDSoundSelection

Figure 3-35 Generating Audible Alert and IDENT Tone Playback

If an alarm occurs from the system, LCU detects it and outputs a warning sound through the
speaker attached on CSP. LCU generates a warning sound signal of 1000 Hz by using the
Timer2 of the microprocessor U300. This signal is outputted to the TOUT2 pin of U300 and
is amplified in the audio amplification IC U1107, and is played through the speaker of CSP.

In order to check the IDENT signal being correctly transmitted, The IDENT tone generated
from MSG or the IDENT tone received via MON can be played through a speaker. The
IDENT signals coming from MSG1, MSG2, MON1 and MON2 are inputted to the Analog
MUX U1106 and one of these is outputted according to the user’s setting. The selected signal
is amplified in the audio amplification IC U1107 and played through the speaker on CSP.
The magnitude of the alarm warning sound and IDENT tone, being played through the
speaker, can be adjusted by turning the volume VR1101.

3.5.8. Sub-Processor

Figure 3-36 Sub-Processor Circuit


The sub-processor U1200, as an 8-bit micro-controller, has the built-in 32KB flash memory,
4KB RAM, serial communication device, timer, and 8-channel 10bit A/D converter. U1200
exchanges data through the SPI interface to the main CPU U300.

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Chapter 3. Hardware Description

The sub-processor U1200 monitors the output voltage and current of power unit, internal
temperature, internal temperature of CMA and temperature of the equipment room and at the
same time controls the cooking FAN for the radiations of PSS and CMS.

While the respective output voltage and current of DC/DC unit is detected from the PDU
sensor and sent to LCU via the Analog MUX, it is inputted again to the ADC of U1200 via
the buffer U1201. The items measured from U1200 are shown on the following table.

SN Signal Name Comment ADC Input Channel

1 AC1_+28V_V AC/DC1 Output +28V Voltage Value ADC1

2 AC1_+28V_A AC/DC1 Output +28V Current Value ADC1

3 AC2_+28V_V AC/DC2 Output +28V Voltage Value ADC1

4 AC2_+28V_A AC/DC2 Output +28V Current Value ADC1

5 DC_+5V_V DC/DC Output +5V Voltage Value ADC1

6 DC_+5V_A DC/DC Output +5V Current Value ADC1

7 DC_+7V_V DC/DC Output +7V Voltage Value ADC1

8 DC_+7V+_A DC/DC Output +7V Current Value ADC1

9 DC_-15V_V DC/DC Output -15V Voltage Value ADC1

10 DC_-15V_A DC/DC Output -15V Current Value ADC1

11 DC_+15V_V DC/DC Output +15V Voltage Value ADC1

12 DC_+15V_A DC/DC Output +15V Current Value ADC1

13 DC_-24V_V DC/DC Output -24V Voltage Value ADC1

14 DC_-24V_A DC/DC Output -24V Current Value ADC1

15 DC_+28V_V DC/DC Output +28V Voltage Value ADC1

16 DC_+28V_A DC/DC Output +28V Current Value ADC1

17 BAT1_+28V_V Battery 1 Output +28V Voltage Value ADC2

18 BAT1_+28V_A Battery 1 Output +28V Current Value ADC2

19 BAT2_+28V_V Battery 2 Output +28V Voltage Value ADC2

20 BAT2_+28V_A Battery 2 Output +28V Current Value ADC2

The internal temperature of power unit is measured by the digital temperature sensor being
in the AC/DC unit and read from U1200 via the serial data interface.

The FAN control signal is outputted from the parallel I/O ports PD4, PD5, PD6 and PD7.
This signal operates the P-channel power MOSFET Q1100, Q1101, Q1102 and Q1103. The

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Chapter 3. Hardware Description

gates of MOSFET Q1100, Q1101, Q1102 and Q1103 are pulled up to +28V by R1104,
R1105, R1106 and R1107. Hence when the U1100 output is off, the VGS of MOSFET
becomes ‘0’ and the FAN stops as the drain current is cut-off. When the U1100 output is
turned on, the VGS of MOSFET rises more than 4V and the FAN operates as the drain current
flows.

FAN can be controlled in two ways of automatic or manual by the software.


When in the manual control mode, user turns ON/OFF the respective FAN individually
according to the user setting.
When in the automatic control mode, the FAN is automatically controlled according to the
temperatures of CMA1 and CMA2. The temperature data measured from the temperature
sensor built within CMA are read from U1200 through the serial data interface. If one ore
more of two measured temperature values rise beyond the threshold, U1200 operates the
FAN. Even though the temperatures of CMA1 and CMA2 goes down below the threshold,
the FAN doesn’t stop immediately until the temperature fall 2℃ below the threshold. In case
of the automatic mode, all the FANs of the system are simultaneously turned ON/OFF.

The temperature measuring function inside of the equipment room is optional and it is
provided when the PT100 temperature sensor is installed within the equipment room. The
signal outputted from the temperature sensor is converted into the DC voltage via U1203 and
inputted to the ADC2 of U1200 and read.

3.5.9. Other Functions

Data Latch TestSignalSelection Data Buffer


U707 U705
CS_CALSIG /CS_PD_ALM UnitDetect
TestSignalSelection Buffer
U706

Microprocessor UnitDetect

Data Buffer PSUAlarmInput


U702
/CS_ALM

Buffer
Buffer U703

EPROM UARTCLOCK: PSUAlarmDetect


14.7456MHz
EPLD CS_CALSIG
SRAM U400 /CS_PD_ALM
PLDCLOCK: Data Latch ShelterAlarm&Reserved
/CS_ALM U707
29.4912MHz
/CS_RSV_IN /CS_RSV_IN
Shelter&Reseved

MicroprocessorPart PeripheralLogic

Figure 3-37 LCU Other Circuits

Additionally, LCU selects the test signals of TSG, monitors the attachment/detachment of
each system unit, and checks the trouble of power unit.

TSG, as the part that generates the test signal used for monitoring the operating status of
monitor, is physically included in CSU. TSG can output a total of 16 test signals. LCU

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Chapter 3. Hardware Description

generates the 4-bit test signal selection signals via the LATCH IC U707 and provides them
to CSU.

LCU monitors the attachment/detachment status of each LRU of the system. Here, MSG
1/2, MON 1/2, CSU, CMA 1/2, LSB SMA 1/2, USB SMA 1/2, AD/DC 1/2 and DC/DC 1/2
are included. The detachment/attachment monitoring signal of each LRU is sent to the 3state
buffer IC U704 and U705 and read by the microprocessor U300. Since each signal is pulled
up with the resistors R712 ~ R722 and R725 ~ R728, HIGH (+5V) is inputted when no unit
is attached and LOW (GND) when a unit is attached.

Also, LCU monitors the trouble of power unit. The power unit alarm signals include the unit
trouble alarm, AC input alarm and battery problem alarm. These alarm signals are sent to the
3-state buffer IC U702 and U703 and read by the microprocessor U300.

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Chapter 3. Hardware Description

3.6. MON
3.6.1. Appearance of MON

Front Panel of MON

Figure 3-38 Front Panel of MON

LEDs
LED Name Color Description

POWER Green ON: When power is normally supplied


OFF: When power is cut-off

TxD Green When MON is transmitting data to LCU

RxD Green When MON is receiving data From LCU

FAULT Red When a RESET or trouble occurs from MON

IDENT Green When it receives the IDENT signal

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Chapter 3. Hardware Description

Switch
Name Description

RESET The switch for resetting the LCU CPU

Ports
Port Name Description

DEMOD The composite VOR signal that is received from the field monitor antenna and
decoded

REF 30Hz The reference phase (REF 30 Hz) signal that is received from the field monitor
antenna and decoded

VAR 30Hz The variable phase (VAR 30 Hz) signal that is received from the field monitor
antenna and decoded

3.6.2. Interfaces between Units

Figure 3-39 Monitor Interface

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Chapter 3. Hardware Description

3.6.3. MON Overview

Signal Monitor

MON monitors the radiated signal and detects any abnormality. The radiated signal is
received with the monitor antenna and supplied to MON. MON, after amplifying and
decoding the received signal, converts into the digital data and measures each signal
parameter. The major signal parameters that the monitor watches will be followed as below.
 Monitor reference azimuth  Reference 30Hz AM modulation degree 
Variable 30Hz AM modulation index  9960Hz sub-carrier wave AM modulation
degree  IDENT code and AM modulation degree

When the measured signal parameter goes beyond the fixed allowed range, it generates a
warning alarm. When the alarm persists for a certain period of time, it transfers to the standby
TX and tries the recovery. If the same alarm persists for a certain period of time after
transferring to the standby TX, it halts the signal transmission to prevent the wrong signal
from transmitting.

The conditions that transfers to the standby TX or halts the transmission shall be followed as
below.  When the error of monitor reference azimuth goes beyond the allowable range 
When the deviation of reference 30Hz AM modulation degree goes beyond the allowable
range
 When the deviation of 9960Hz sub-carrier wave AM modulation degree goes beyond
the allowable range
 When the IDENT signal is omitted or the transmission is not made according to the
stipulated code or interval
 When the MON unit itself has a trouble
 When the deviation of variable 30Hz AM modulation index goes beyond the allowable
range
 When the deviation of carrier wave frequency goes beyond the allowable range 
When the carrier wave and sideband antennas have errors (VSWR > 1.2:1)

Monitor Configuration

Two MONs of MARU 220 can be configured to the OR Mode or AND Mode according to
the user’s selection.  OR Mode: If an alarm is detected from either one of two, it is
transferred to the standby TX or halts the transmission.
 AND Mode: If alarms are detected from both MONs, it is transferred to the standby TX or
halts the transmission

Self-Diagnosis Function

It uses the Test Signal Generator (TSG) for the self-diagnosis of MON. The VOR test signals
from TSG are processed and read by MON in the same way as the signals received from the
monitor antenna. Since the VOR test signals generated from TSG are synthesized by a digital
method according to a pre-fixed number of reference modulation elements, they are quite

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Chapter 3. Hardware Description

accurate. When a normal number is outputted after MON measures this signal, the
corresponding MON can be judged as be normal.

MON Calibration

MON is calibrated by using a standard measuring instrument before sending out from the
factory. The calibration factor is saved to the EEPROM of each MON. However, the VOR
signal parameter that MON monitors can be variable according to the setup environment and
it can differ from the actual navigation check result. The MARU 220 Doppler VOR has the
function of calibrating these differences so that the MON monitoring results can be matched
with the navigation check data. This calibration factor is saved to the system EEPROM so
that it can be retained even though the MON unit is replaced.

Others

Additionally, MON executes the following monitoring and diagnosis functions.


 Monitor the carrier wave and sideband transmission frequencies 
Monitor the carrier wave output power
 Monitor the signal level received from the monitor
antenna  Monitor the carrier wave antenna and sideband
antenna  Monitor the DC voltage supplied to each unit

The following figure shows the MON block diagram.

3.6.4. Major Parts of MON


Part Name P/N Description

CPU MC68302 M68000 Core, Integrated Multiprotocol Processor

RAM K6T4016 256k x 16 bit Low Power CMOS Static RAM

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Chapter 3. Hardware Description

EPROM M27C4002 4 Mb (256Kb x 16) UV EPROM

Reset IC DS1232 Micro Monitor, Reset, Watchdog Timer / Monitor

EPLD EPM7064 64 Macrocells, Programmable Logic Device

A/D Converter ADC12041 12-bit Parallel Analog-to-Digital Converter

D/A Converter AD7945BR 12-bit Parallel Digital-to-Analog Converter

MMIC AMP AM1 60-3000 MHz, 14 dB Gain, 2.4 dB NF, +39 dBm OIP3

Detector AD8361 LF to 2.5 GHz RMS Power Detector

3.6.5. Microprocessor and Peripheral Circuit

Microprocessor and Memory

U300 is the primary control microprocessor of MON. U300, based on the M68000 core, is
integrated with the 1152B dual port RAM, programmable timer, SCC, and 24-bit general
GPIO. The data and address buses of U300 are connected to the peripheral devices through
the 3-state buffer U500-U504.

The crystal oscillating circuit X300 supplies a clock of 18.432 MHz to U300.

U301, as the microprocessor monitor IC, includes the reset signal generation circuit, power
voltage monitoring circuit and watchdog timer circuit. U301 supplies the reset signal to the
microprocessor U300 and at the same time monitors the operation status of U300. The
followings are the cases that U301 outputs a reset signal.

1) When power is turned on


2) When the reset switched is pressed for a minimum of 250ms
3) When the Address Strobe (AS) signal of U300 is not outputted for over 1.2 seconds
(Watchdog timer – Microprocessor error)
4) When the Vcc fall below 4.5V (abnormal power voltage)

When the reset signal of U301 is outputted, the FAULT LED on the front panel of MON is
lighted on.
Since the /RESET output signal of U301 is also connected to the /OE pins of bus switches
U1800 ~ U1805 via Q1800, the I/O signal line of MON is separated from the backplane
during the reset period.

MON uses several different types of storage devices as below. All the rest of storage devices
except for the serial EEPROM are positioned within the memory space of the microprocessor
U300.
 EPROM U506: Save the program code and data
 SRAM U505: Save the temporary data used when executing a program
 EEPROM U507: Save non-volatile parameters

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Chapter 3. Hardware Description

Additionally, MON uses the public EEPROM attached to the backplane.

When the microprocessor U300 is initialized after receiving the reset signal, U300 executes
the program code saved in the EPROM U506.

U400 is a programmable logic device (PLD). It includes the logic circuits such as the address
decoder and GPIO port.
The address decoder inside of U400 decodes the addresses for each memory and I/O device
from the address and control bus signals of U300 and generates the Chip Selection Signals.

The GPIO port of U400 consists of the latch circuit for the output port and the digital switch
circuit for the input port.
Also, U400 receives the reference clock of 7.86432 MHz from the X400 crystal oscillator, is
divided into 1/8192 and generates the 960 Hz sampling signals for A/D converter.

The serial communication port SCC1 of U300 is used to exchange the LCU status
information and control data. SCC2 is not used during a normal operation and is reserved for
debugging.

DAC and ADC

The D/A converter of MON is used to automatically adjust the gains of RF signal processing
circuit.

U700 is a 12-bit current output and multiplying D/A converter. The output of U700 is
converted into the voltage signal from the current-voltage conversion circuit consisted of OP
AMP U701. This signal is applied to the variable voltage attenuator of a RF signal processing
circuit via the non-reversal buffer consisted of U702 and Q700.

U900, as a precise reference voltage IC, supplies the 10V reference voltage to DAC U700.

The A/D converter of MON is used to sample each VOR signal element and at the same time
used to measure the carrier wave output power and power voltage.

U703 is a 13-bit (data 12-bit and sign 1-bit) parallel A/D converter. Although U703 itself is
a single channel, it is multiplexed by the analog switches IC U803, U800 and U1201 to
process several inputs.

The A/D conversion timing, when analyzing the VOR signal element, is obtained by
synchronizing it to the 960 Hz sampling signal supplied from U400. The A/D conversion is
asynchronously made to the microprocessor U300 control, when measuring the carrier wave
output and power voltage.

U703, as a precise reference voltage IC, supplies the 5V reference voltage to ADC U703.

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Chapter 3. Hardware Description

Hot-Swap Control

U1700, U1701 and U1702 are the hot-swap ICs. These control ICs are electrically separated
from the backplane of power supply lines while in the process of attaching or detaching a
unit and prevent the unstable voltage being applied to the internal circuits of the unit.

U1800, U1801, U1802, U1803, U1804 and U1805 are 10-bit bus switches. These bus
switches are electrically separated from the backplane of each I/O signal line while in the
process of attaching or detaching a unit and prevent the system from an erroneous operation.

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Chapter 3. Hardware Description

3.6.6. RF Signal Processing Circuit

Figure 3-41 RF Signal Processing Circuit

The internal RF signal processing circuit of MON filters the frequency band needed from the
RF signal received from the field monitor antenna, RF-amplifies and converts it with a fixed
level of about -5 dBm, and extracts the audio band VOR signal after detecting that.

The signal received from the antenna is supplied to the Band Pass Filter (BPF) F1101 via the
impedance matching circuit. The pass frequency band of F1101 lies in the range of 108 ~
118 MHz. The noise signals in addition to the frequency band assigned to VOR are cutoff
from F1101.

The signals that have passed BPF F1101 are supplied to the RF amplification circuit consisted
of the voltage control attenuation circuit made with the PIN diode D1100~D1105 and of the
MMIC amplifiers U1100, 1101, 1102 and 1103 and are then amplified. The total gain of RF
signal processing circuit is automatically controlled by the MON software so that -5dBm is
constantly outputted for the input signal level range -45 dBm ~ +5 dBm. The control voltage
applied to the voltage attenuation control circuit has the range of 1 V ~ 8 V.

The signal amplified to -5 dBm is detected from the AM demodulation circuit U1104 and the
VOR composite signal of audio band that has removed the carrier wave is obtained. This
signal includes the DC and reference 30Hz signal proportional to the magnitude of carrier
wave, variable 30Hz signal frequency-modulated to the 9960 Hz sub-carrier wave, and

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Chapter 3. Hardware Description

IDENT signal. The decoded VOR signal is supplied to the analog signal processing circuit
for the signal analysis by each modulation element.

3.6.7. Reference 30 Hz Signal Processing

Figure 3-42 Reference 30Hz Signal Processing

Figure 3-42 shows the processing steps of a reference 30 Hz signal.

The foremost one from the analog signal processing system is a signal selection switch
U1201 (MUX1). Although U1201 is the analog switch that can select one of 8 inputs, only
two of them are used here. The signals applied to U1201 are the VOR composite signal
decoded within the RF signal processing circuit and the test signal generated from the test
signal generator (TSG). U1201 is controlled by the MON software and one of these two are
selected and passed.

The signal that has passed U1201 is supplied to the 150Hz low pass filter (LPF) via the non-
reversal amplification circuit of OP AMP U1300. 150Hz LPF consists of R1305, R1306 and
MC1300 and the signal elements below 150 Hz are passed and the rest are cutoff. Part of this
signal is outputted to the test BNC connector (REF 30Hz) attached on the front panel of
MON via the OP AMP buffer U802-B.

The extracted signals pass through the 1-of-8 analog switch U800 (MUX2) and again, are
supplied to 60Hz LPF. 60Hz LPF, as an active one, consists of OP AMP U801, R826, R830,
MC801 and MC802 and allows passing the signals below 60 Hz. Therefore, only the pure
reference 30Hz signals are obtained from the VOR composite signals.

Finally, the reference 30Hz signals pass through the 1-of-16 analog switch U803 (MUX3)
and are converted into the digital data after being sampled from the A/D converter U703. At
this time, the sampling frequency is 1/ 960 second. In other words, the data is sampled at the
rate of 32 for one cycle of 30Hz signal (32 samples/cycle ≡ 960 samples/sec).

The amount of data sampled for one time of signal processing is the amount for two cycles
of 30Hz signal processing, which are 64 samples. From these, the 32 data in the back are
used in processing the Fast Fourier Transform (FFT). Since it is possible to have incorrect

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Chapter 3. Hardware Description

data for a certain period of time until the signal is stabilized after the path corresponding to
the respective analog switches of MUX1, MUX2 and MUX3 is selected, the first 32 data are
not used.

Since the sampling frequency is 960Hz and the used data are 32, the magnitude shown in a
complex number with the respective frequency elements in the interval of 30Hz from the
range of 0 Hz (DC) ~ 480 Hz is obtained from the FFT result. By taking the DC and 30Hz
elements from these, the band modulation degree of reference 30Hz signal can be calculated
according to the equation below.

A30Hz
m30Hz =
A0Hz

Also by taking the real number part and imaginary number part of 30Hz elements, the phase
of reference 30Hz signal can be calculated according to the equation below.
Im(A30Hz )
φREF = arctan
Re(A30Hz )

3.6.8. Variable 30 Hz Signal Processing

Figure 3-43 Steps of Variable 30Hz Signal Processing

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Chapter 3. Hardware Description

The figure 3-43 above shows the processing steps of variable 30Hz signal.

Same as the processing steps of other analog signals, the demodulated VOR composite signal
in the RF signal process circuit and the test signal generated from the test signal generator
(TSG) are applied to U1201. U1201 is controlled by the MON software and one of these two
is selected and passed.

The signal that has passed U1201 passes through the limiter circuit consisted of D1400,
D1401 and Q1400 and the amplitude-modulated elements are removed.

This signal is filtered from the 9960 Hz band pass filter U1401 via the OP AMP buffer
U1400-A. U401, as a switched capacitor filter, receives the 491520 Hz clock signal from
U400 and constructs the band pass filter circuit below the pass bandwidth 1 kHz of the
intermediate frequency 9960 Hz.

After the filtered signal is amplified to the approximate magnitude of peak-to-peak 5V from
U1400-B, it is supplied to the frequency discriminator circuit via the differential amplifiers
Q1402, Q1403, Q1404 and Q1405. The frequency discriminator consists of the diodes D1404
~ D1411, the capacitors MC1405 and MC1406, and the integrator constructed with the OP
AMP U1403-A and capacitor MC1407.

The variable 30Hz signal frequency-modulated to the 9960 Hz sub-carrier wave via the
frequency discriminator is demodulated. Since this signal includes the unnecessary DC
elements, the pure variable 30Hz elements are extracted by using the attenuator circuit
consisted of OP AMP U1403-B.

Part of this signal is outputted to the test BNC connector (VAR 30 Hz) attached on the front
panel of MON via the OP AMP buffer U1404-A.

The detected variable 30Hz signal is supplied to the 60Hz active low pass filter U801-B via
the 1-of-8 analog switch (MUX2) U800 and buffer circuit U801-A. Here, the unnecessary
signal elements more than 60Hz are removed.

Finally, the variable 30Hz signals pass through the 1-of-16 analog switch U803 and are
converted into the digital data after being sampled from the A/D converter U703. At this
time, the sampling frequency is 1/ 960 second. In other words, the data is sampled at the rate
of 32 for one cycle of 30Hz signal (32 samples/cycle ≡ 960 samples/sec).

The amount of data sampled for one time of signal processing is the amount for two cycles
of 30Hz signal processing, which are 64 samples. From these, the 32 data in the back are
used in processing the Fast Fourier Transform (FFT). Since it is possible to have incorrect
data for a certain period of time until the signal is stabilized after the path corresponding to
the respective analog switches of MUX1, MUX2 and MUX3 is selected, the first 32 data are
not used.

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Chapter 3. Hardware Description

Since the sampling frequency is 960Hz and the used data are 32, the magnitude shown in a
complex number with the respective frequency elements in the interval of 30Hz from the
range of 0 Hz (DC) ~ 480 Hz is obtained from the FFT result. By taking the real number part
and imaginary number part of 30Hz elements, the phase of variable 30Hz signal can be
calculated according to the equation below.

Im(A30Hz )
φVAR = arctan
Re(A30Hz )

Since the phase of reference 30Hz is calculated from the section 3.6.8, the azimuth can be
calculated according to the equation below if the phase of variable 30Hz can be known.

θ=φVAR −φREF

The output signal magnitude from the transmission characteristics of frequency discriminator
is proportional to the deviation of instantaneous frequency. Therefore, the amplitude of
output signal is proportional to the maximum frequency deviation of original signal.

A30Hz ∝Δfmax

Also since the variable 30Hz signal is fixed with the frequency 30Hz at the time of being
modulated, the FM index (β) from the magnitude of 30Hz elements can be calculated.

β= Δfmax = Δfmax = K ⋅ A30Hz fmod 30

3.6.9. Measuring AM depth of 9960 Hz Sub-Carrier Signal

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Chapter 3. Hardware Description

Figure 3-44 Measuring AM depth of 9960 Hz Sub-carrier signal

Figure 3-44 shows the steps of measuring the amplitude modulation degree of 9960 Hz FM
sub-carrier wave signal.

Same as the processing steps of other analog signals, the demodulated VOR composite signal
in the RF signal process circuit and the test signal generated from the test signal generator
(TSG) are applied to U1201. U1201 is controlled by the MON software and one of these two
is selected and passed.

The VOR composite signal that has passed U1201 includes the reference 30Hz signal and
1020Hz IDENT in addition to the 9960 Hz FM sub-carrier wave. Since these unnecessary
signal elements need to be eliminated to obtain the 9960 Hz AM modulation degree, the high
pass filter (HPF) is used. U1601, as an active HPF, allows only the 9960 Hz subcarrier wave
elements passing through.

The signal that has passed through the U1603 HPF is converted to the DC signal from the
precise full-wave AM demodulation circuit consisted of D1600 and D1601.

This DC signal is supplied to the 60Hz active low pass filter (LPF) U801 after passing
through the analog switch U800 (MUX2). Since the unnecessary AC elements from the
signals converted into DC can be left over, U801 eliminates these and allows only the DC
elements passing through.

The pure DC elements obtained through the above described process again pass through the
analog switch U803 (MUX3), are sampled from the A/D converter U703, and are converted
into the digital data.

The amplitude modulation degree of the 9960 Hz FM sub-carrier wave signal can be
calculated according to the equation below.

A9960Hz VDC
m9960Hz = =
A0Hz A0Hz

Here, VDC as the elements corresponding to the 9960 Hz sub-carrier wave has the magnitude
of DC elements obtained above and A0Hz as the elements corresponding to the primary carrier
wave signal has the magnitude of DC elements obtained from the processing steps of
reference 30Hz signal.

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Chapter 3. Hardware Description

3.6.10. 1020 Hz IDENT Signal Processing

Figure 3-45 Measuring AM Depth of 1020 Hz IDENT Signal

Figure 3-45 shows the steps of measuring the amplitude modulation degree of IDENT signal.

As shown in the figure, the VOR composite signal demodulated from the RF signal
processing circuit is inputted to the analog switch U1201 for other analog signal processing
and at the same time is supplied to the OP AMP buffer U1200-A for the IDENT signal
processing.

The composite signal that has passed through the OP AMP buffer U1200-A is applied to the
1020 Hz band pass filter (BPF) U1500. U1500, as a switched capacitor filter, operates after
receiving the clock signal of 61440 Hz from U400. While the IDENT signal of the frequency
1020 Hz passes through this BPF, the rest of unnecessary signals are filtered here.

The IDENT signal that has passed BPF is converted into the DC signal from the precise full-
wave AM demodulation circuit consisted of the diodes D1500 and D1501 and the OP AMP
U1502, via the OP AMP buffer U1501-A.

The signals converted into DC can include the signals of high frequency elements in addition
to the Morse code IDENT signal that is keyed at the rate of 7 words per minute (≒ 350
baud/min, 58.1 baud/sec). Since these elements can interfere in processing the IDENT signal,
they are filtered by using the LPF with the cut-off frequency of about 10 Hz. The OP AMP
U1503 consists the active low pass filter (LPF) circuit that is used here.

Same to the processing steps of other signal elements, the signals that have passed 10 Hz LPF
are inputted to the A/D converter U703 via the analog switch U803 (MUX3), 60 Hz LPF
U801, and again analog switch U803 (MUX3).

The A/D converter U703 samples the inputted signal and converts into the digital data, and
this data is processed by the MON software to get the amplitude modulation degree of IDENT
signal.

In addition to the modulation degree of IDENT signal, the code carried with the IDENT
signal in a form of Morse code needs to be decoded to check whether the code and repetition
cycle is transmitted according to the rules.

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Chapter 3. Hardware Description

Figure 3-46 shows the steps of decoding the codes of IDENT signal.
Figure 3-47 shows the timing of Morse code IDENT signal.

Figure 3-46 IDENT Signal Code Decoding

The IDENT signal that has passed the 10 Hz LPF U1503 is inputted to the A/D converter for
measuring the amplitude modulation degree and at the same time converted in to the TTL
level from the level conversion circuit consisted of the OP comparator U1503 and transistor
Q1500 for the code decoding. Together with these, the ‘IDENT’ LED on the front panel is
operated by using Q1501 to indicate the IDENT visually.

The IDENT signal converted into the TTL level is sent to the microprocessor U300 via the
3-state data buffer IC U605. The microprocessor U300 reads the TTL level IDENT signal
status that is entered to U605 every 1.04ms by using the timer interrupt of 960 Hz cycle.

MON software detects the time that this level is changed from the state of ‘L’ to ‘H’ and
measures the time between these two. By doing so, calculate the merit (DOT) and demerit
(DASH) and the interval and order mix of PAUSE, and then decode the Morse code from
that.

Figure 3-47 Timing of Morse Code IDENT

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Chapter 3. Hardware Description

3.6.11. Measuring the SYN Output Frequency

Figure 3-48 Measuring the SYN Output Frequency

The signals dividing each output frequency into 40 from the SYN of CMA and SMA are all
transmitted to MON and inputted to the 8-input multiplexer IC U1001. U1001 is controlled
by the MON software and selects the signal to be measured.

The selected signal is applied to the input TIN1 of the microprocessor U300 programmable
timer 1. The output TOUT1 of timer 1 is cascaded to the input TIN2 of timer 2 and constructs
a 24-bit programmable counter as a whole.

MON software opens the gate of this counter for exactly 400ms and counts the signals
inputted. Hence, the actual frequency is obtained by multiplying 2.5 (= 1 sec / 400 ms) to the
number read by the counter.

MON software generates an alarm when the measured frequency goes beyond the allowable
setting range.

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Chapter 3. Hardware Description

3.6.12. Monitoring Status of Transmit Antenna

Figure 3-49 Timing Diagram for Monitoring the Status of Transmission Antenna

MARU 220 DVOR checks the abnormality by monitoring the status of the carrier wave
antenna and each sideband antenna in operation and can indicate which antenna is having a
trouble when an abnormality exists among the sideband antennas.

Monitoring the Status of Carrier Wave Antenna

PDC compares the magnitude of the reflective wave voltage generated from the carrier wave
path with that of the reference and sends the result to MON. This status signal is inputted to
the 3-state data buffer U604 and is read by the microprocessor U300.

MON software, if this signal level is maintained with ‘L’ for a certain period of time, judges
that the carrier wave antenna is having a trouble and generates the antenna alarm.

Monitoring the Status of Sideband Antenna

PDC compares the magnitude of the reflective wave voltage generated from the sideband
path with the fixed reference voltage and sends the result to MON. This status signal is
inputted to the 3-state data buffer U604 and is read by the microprocessor U300.

MON software, if this signal level is maintained with ‘L’ for a certain period of time, judges
that the sideband antenna is having a trouble and generates the antenna alarm.

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Chapter 3. Hardware Description

In order to detect the antenna number that is having a trouble among the 48 sideband
antennas, it is provided with the 30Hz trigger signal synchronized to the antenna rotation
cycle from MSG via CSU and the 2880Hz clock signal.

More or less, it issues an interrupt to the microprocessor U300 whenever the antenna
switching occurs by using the 2880Hz clock signal. Also, it issues another interrupt to the
microprocessor U300 at the rotation cycle start point of the sideband antenna by using the
30Hz trigger signal.

MON software defines and uses the variables of indicating the sideband antenna number that
is internally selected. Whenever an interrupt is issued by the trigger signal, this variable is
initialized and this variable’s value is increased whenever the interrupt by the 2880 Hz clock
occurs. By doing so, MON software can recognize the antenna number selected at the point
whenever the sideband antenna is switched.

MON software, whenever a periodic interrupt occurs, checks the level of sideband antenna
status signal at that point from PDC and detects the sideband antenna number with a trouble.

3.6.13. Measuring Carrier Output Level

The output level of sideband wave is detected from PDC and sent to MON.

The carrier wave output detection signal sent to MON passes through the analog switch U803
(MUX3) and is converted into the digital data from the A/D converter U703.

Since the carrier wave output signal, sampled to detect the output level from PDC, is an
amplitude-modulated signal, the magnitude of the signal sent to MON gets changed
periodically. At least one cycle of modulated signal data is taken and averaged to indicate the
average output power.

MON software in this signal takes 64 data samples at a time and calculates the average of the
last 32 samples. A software type of lookup table is used to get the output power shown in
watts from this calculated value. Since this lookup table is saved to the non-volatile memory
attached on the system backplane, it can be shared by MSG and MON.

3.6.14. Interface between MONs

MARU 220 DVOR uses two independent monitors. The data exchange between two
monitors is essential to determine the executive action such as switching to the standby TX
or interrupting the TX by detecting the abnormality of a monitor.

The data exchanged at this time are the status values that show whether or not the
monitoring result of each monitor is right. This data are exchanged from each other through
U602 and U603.

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Chapter 3. Hardware Description

The current system status that has monitored each monitor is outputted to the 8-bit data latch
IC U602. The output of U602 is connected to the 3-state data buffer U603 of the other party.
U602 and U603 is connected to the data bus of the microprocessor U300 and controlled by
the MON software.

The lowest bit (b0) among the 8-bit data exchanged between two monitors indicates whether
the signal radiated is right or not and if this bit is ‘L,’ it means that the radiated signal is not
right and an alarm has occurred.

3.6.15. Measuring Power Supply Voltages

Apart from the voltage and current measured internally within PSS by LCU, the respective
voltages supplied to the backplane of CMS and MAS are monitored by MON.

Since the maximum input voltage of the A/D converter U703 that includes MON is 5V, the
input voltage should be divided to be less than 5V to measure each power voltage. Each
voltage on two backplanes are divided into the voltages of 3~4V through the resistors
R905~R934 and they are applied to the A/D converter U703 via the OP AMP buffer U903
and analog switch U803.

If the respective voltages measured in this way goes beyond a setting range, the
corresponding alarm is generated.

3.6.16. Self Test

The foremost one in the analog signal processing system is the signal selection switch U1201
(MUX1). The signals applied to U1201 are the demodulated VOR composite signal in the
RF signal processing circuit and the test signal generated from the test signal generator
(TSG).

U1201 is controlled by the MON software and allows passing through by selecting one of
two signals. The signal processing steps from then on are identical.

TSG generates the test signals by synthesizing in a digital method according to the equation.
Hence, the respective parameters of these test signals are fixed in advance and precise signals
are obtained without an error.

TSG can output one among the 16 test signals numbered from 0 to 16 as shown in the
following table. In the normal times, only the one with ‘0’ is used and it is used to check the
monitor in the preventive maintenance process. Operator judges which test signal TSG is to
output and operator controls it through LCU.

MON software periodically analyzes the test signals generated from TSG and calculates each
signal parameter and checks whether or not the error is within the allowable range. When the

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Chapter 3. Hardware Description

analysis result of this test signal exceeds the allowable range, it judges that the monitor itself
is having an trouble.

Table 3-1 Test Signals Outputted from TSG

9960Hz
30Hz AM 30Hz FM
No. AM Azimuth Remarks
Depth Mod-Index
Depth

0 30% 30% 16 180° REF

1 30% 30% 16 178.5° Azimuth Alarm

2 30% 30% 16 181.5° Azimuth Alarm

3 20% 30% 16 180° 30Hz AM Depth Lower Limit Alarm

4 40% 30% 16 180° 30Hz AM Depth Upper Limit Alarm

5 30% 20% 16 180° 9960Hz AM Depth Lower Limit Alarm

6 30% 40% 16 180° 9960Hz AM Depth Upper Limit Alarm

7 30% 30% 14.5 180° 30Hz FM Index Lower Limit Alarm

8 30% 30% 17.5 180° 30Hz FM Index Upper Limit Alarm

9 30% 0% 16 0° 30Hz Only

10 0% 30% 16 0° 10kHz Only

11 30% 30% 16 0° Calibration

12 30% 30% 16 45° Calibration

13 30% 30% 16 270° Calibration

14 30% 30% 15 0° Calibration

15 30% 30% 17 0° Calibration

3.6.17. Transmitter Changeover Control

The changeover function from the primary transmitter (TX) to the standby transmitter is
controlled by MON and the interface circuits related to it are all included in CSU. The outputs
of two transmitters are either sent to the antenna by the coaxial relay and RF relay included
in PDC or connected to the dummy load.

Hence, the steps of changing over to the transmitter are to reverse the routine by controlling
the relay. However, it is not advisable for several reasons to change over the relay contact

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Chapter 3. Hardware Description

point while the high-power RF signal is applied. Therefore, it is advisable to cut-off the RF
output temporarily before changing over the relay contact point. However since MSG
controls the RF output, MON can’t directly cut-off the transmission output. Hence, this
process is made in the way of signaling indirectly to MSG by using the hard flag included in
CSU.

There are two cases that the transmitter is changed over. One is that it is automatically
changed over by detecting a serious problem when the monitor is in the active state or user
manually changes over regardless of the monitor status. According to the cases, the process
that the transmitter is changed over is somewhat different.

Changeover by a Manual Operation

In this case, the path connected to the antenna is changed while maintaining the ON/OFF
state of the transmitter.

1) Judge which one is active or standby first by reading the contact point status of the PDC
coaxial relay from CSU.
2) MON sets the hardware flag within CSU.
3) MSG reads this hardware flag periodically and cuts-off the transmitter output temporarily
if it is set.
4) MON monitors the transmission output and MSG waits until the transmission output is
temporarily cut-off.
5) If the cut-off of the transmission output is confirmed, MON sends the relay changeover
signal to CSU.
6) MON checks whether or not the relay is changed over by reading the contact point status
from CSU.
7) MON clears the hardware flag in CSU to recover the transmission output again.
8) Each MSG waits for the hardware flag in CSU to get cleared and restores that to the
original transmission output.

Automatic Changeover When the Monitor Is in the Active State

In this case, the path connected to the antenna is changed over while the transmitter active
up until now becomes off and the transmitter in the standby state becomes on.

1) Judge which one is active or standby first by reading the contact point status of the PDC
coaxial relay from CSU.
2) MON sets the hardware flag within CSU.
3) MSG reads this hardware flag periodically and cuts-off the transmitter output temporarily
if it is set.
4) MON monitors the transmission output and MSG waits until the transmission output is
temporarily cut-off.
5) If the cut-off of the transmission output is confirmed, MON sends the relay changeover
signal to CSU.

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Chapter 3. Hardware Description

6) MON checks whether or not the relay is changed over by reading the contact point status
from CSU.
7) When the relay changeover is confirmed, the standby transmitter waiting up until now
becomes on.
8) Reversely, the primary transmitter that has been active becomes off.
9) MON clears the hardware flag in CSU to recover the transmission output again.
10)Each MSG waits for the hardware flag in CSU to get cleared and restores that to the
original transmission output.

If a serious problem occurs even after the transmitter is changed over, the transmitter
currently in an active state becomes off. In other words, two transmitters become off and the
system gets shutdown.

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Chapter 3. Hardware Description

3.7. MSG
3.7.1. Appearance of MSG

Front Panel of MSG

Figure 3-50 Front Panel of MSG

LEDs
LED Name Color Description

POWER Green ON: When power is normally supplied


OFF: When power is cut-off

TxD Green When MSG is transmitting data to LCU

RxD Green When MSG is receiving data from LCU

FAULT Red When a reset or trouble of MSG has occurred

Switches
Name Description

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Chapter 3. Hardware Description

RESET The switch that resets the MSG CPU


3.7.2. Features of MSG

MSG generates the respective modulation signal and antenna switching control signal and
supplies them to ASU. Also, it controls the system variables such as transmission output and
modulation degree.  Generate the composite signal that consists of the carrier wave
modulation signal that is the 30Hz reference phase signal, IDENT and voice. This signal is
supplied to CMA. The function of keying the fixed IDENT code into the Morse code includes
of generating the IDENT signal. The voice signal is included into the composite signal by
receiving an external input.
 Generate the SIN blending signal and COS blending signal, which are the sideband
modulation signals. These signals are supplied to each SMA.
 Control the amplitudes of carrier wave and sideband modulation signals and set the
respective transmission outputs.
 Generate the control signal for switching the antenna. This signal is supplied to ASU
via CSU.
 Automatically control the phase of RF signal to be transmitted. By measuring the phase
error between carrier wave and two sideband signals, it adjusts the voltage applied to
the phase regulator of SMA to correct it.
 Set the oscillating frequency of SYN in CMA and two SMAs, which is the transmission
frequency of the system.
 Measure each transmission output and monitor the internal temperature of MSG.

U1504-1505

U1703

Figure 3-51 Internals of MSG


3.7.3. Major Parts of MSG
Part Name P/N Description

CPU MC68302 M68000 Core, Integrated Multiprotocol Processor

RAM K6T4016 256k x 16 bit Low Power CMOS Static RAM

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Chapter 3. Hardware Description

EPROM M27C4002 4 Mb (256Kb x 16) UV EPROM

Reset IC DS1232 Micro Monitor, Reset, Watchdog Timer / Monitor

EPLD EPM7128 128 Macrocells, Programmable Logic Device

EPLD EPM7192 192 Macrocells, Programmable Logic Device

A/D Converter AD7888 8-Channel, 125 kSPS,12-bit Serial, Analog-to-Digital Converter

D/A Converter AD7945BR 12-bit, Parallel, Digital-to-Analog Converter

3.7.4. Microprocessor and Peripheral Circuits

U300 is the microprocessor for the main control of LCU. U300 is based on the M68000 core
and the 1152-byte dual port RAM, programmable timer, serial communication controller
(SCC), and 24-bit general GPIO are integrated within the chip. The data and address buses
of U300 are connected to the peripheral devices through the 3-state buffer U500-U504.

U301, as the microprocessor monitor circuit IC, includes the reset signal generation circuit,
power monitor circuit and watchdog timer circuit. U301 supplies a reset signal to the
microprocessor U300 and at the same time, it monitors whether U300 operates normally.
The cases that U301 outputs a reset signal follow as below.

The crystal oscillating circuit X1001 supplies a clock of 29.4912 MHz to U300.

1) When power is turned on


2) When the reset switch is pressed for 250ms or more
3) When the Address Strobe (AS) of U300 is not outputted for 1.2 seconds or more
(Watchdog timer – microprocessor error)
4) When the Vcc voltage falls below 4.5V (abnormal power voltage)

When the reset signal of U301 is outputted, the FAULT LED lamp on the front panel of LCU
is lighted on.
Since the /RESET output signal of U301 is also connected to the /OE pin of the bus switches
U1903 ~ U1907 via Q300, the I/O signal line of LCU is separated from the backplane during
the reset period.

MSG uses the following storage devices different from each other. All the rest of storage
devices except for the serial EEPROM are positioned within the memory space of the
microprocessor U300.

 EPROM U600 and U601: Store the program code and data 
SRAM U601: Store the temporary data used during the program execution 
EEPROM U603: Store the non-volatile parameters
Additionally, MSG uses the public EEPROM attached to the backplane.

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Chapter 3. Hardware Description

The EEPROM U603 inside of MSG and the public EEPROM attached to the backplane are
multiplexed by the analog switch U1802. The analog switch U1802 is controlled by the
microprocessor U300 so that the MSG software can access the data of two EEPROMs.

The 3 serial communication ports included in U300 are used for the following purposes. 
SCC1: The RS-232C serial communication for exchanging data with LCU  SCC2:
The RS-232C serial communication for software debugging and factory test  SCC3:
The 3-lined serial data interface (SPI) for controlling the A/D converter U1404

U400 is a programmable logic device (PLD). It includes the logic circuits such as the address
decoder and GPIO port.

The address decoder inside of ELPD U400 decodes the addresses for each memory and I/O
device and generates the Chip Selection Signals, from the address bus and control bus signals
of the microprocessor U300.

The GPIO port of U400 consists of the latch circuit for the output port and the digital switch
circuit for the input port.

3.7.5. Modulation Signal Generation for Carrier Wave

The modulation signal for carrier wave is the composite signal that the 30Hz reference phase
signal, IDENT and voice are overlapped on a fixed magnitude of DC.

 The carrier wave level in the modulation process is determined according to the
magnitude of DC elements included here. The amplitude modulation degree of each
element is individually controlled by adjusting the magnitude of the corresponding
elements included within the composite signal.
 The 30Hz reference phase signal, as the reference signal of measuring the azimuth, is
synchronized to the control signal for switching the antenna.
 IDENT is obtained by keying the 1020Hz sine wave into the preset Morse code.
 Voice, as the audio signal of 300 ~ 3000 Hz, is included to the composite modulation
signal when having an external input.

The 30Hz reference phase signal and 1020Hz IDENT should have an accurate sine wave and
at the same time, the frequency should be highly stabilized. Also, the 30Hz reference phase
signal should be phase-synchronized to the antenna switching signal and the phase offset
should be precisely controlled.

The 30Hz and 1020Hz signals are digitally synthesized by using the Direct Digital Synthesis
(DDS) technology for these. DDS is the technology of generating the sine wave of having
accurate frequencies by reading the numeric data of the wave saved within the memory and
by sending them to the D/A converter. The phase of generated signals can be precisely

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Chapter 3. Hardware Description

controlled digitally by controlling the timing of taking out the wave data from the memory
by using the DDS technology.

The numeric data of 30Hz and 1020Hz signal waves are saved in the EPROM U701. U701
is separated by the odd-numbered addresses and even-numbered addresses and the 30Hz
signal wave data are saved to the even-numbered addresses and the 1020Hz signal wave data
to the odd-numbered addresses.

The 30Hz signal wave data read from U701 are sent to the D/A converter U800 and the
1020Hz signal wave data to the D/A converter U803 and they are converted into the analog
signals.

The address signals of EPROM U701 and the write signals of D/A converters U800 and U803
are made by the EPLD U700. The trigger signal for the phase-synchronization between 30Hz
reference phase signal and antenna switching signal are made within U700 in the same way.
In order to generate these signals, U700 receives the 7.864320 MHz clock from the crystal
oscillator X700 and uses it.

The phase control of 30Hz reference phase signal is made by supplying the phase offset value
from the microprocessor U300 to the EPLD U700. Since the phase offset data have the 14-
bit length, it can be adjusted by 0.1 ° in the range of 0 ° ~ 359.9 °. Accordingly, the 30Hz
reference phase signal is accurately delayed to the offset set by the synchronization trigger
signal and outputted.

The D/A converter U800 and U803 receive an accurate +10V power from the reference
voltage U1106 and use it as the reference voltage. Since U800 and U803 are the currentoutput
type of D/A converters, they are converted into the voltage output by using the precise
operation amplifiers U801 and U802.

The output of U801 or 30Hz reference phase signal is inputted to the reference voltage input
(VREF) pin of D/A converter U900 for the control of modulation degree. Since U900 is a
multiplying D/A converter, the signal inputted to the VREF pin is amplitude-adjusted by the
inputted data value and appears on the output pin (IOUT1). The current output of U900 is
converted to a voltage by U901.

In the same way, the output of U802 or 1020Hz signal is inputted to the reference voltage
input (VREF) pin of D/A converter U903 for the control of modulation degree. Since U903
is a multiplying D/A converter, the signal inputted to the VREF pin is amplitude-adjusted by
the inputted data value and appears on the output pin (IOUT1). The current output of U903
is converted into a voltage output by U902.

This signal is inputted to the analog switch U909 for keying the Morse code again. The Morse
code keying is either controlled by the MSG software in the microprocessor U300 or mad by
receiving the keying signal from the collocated DME. The signal keyed by the MSG software
and the keying signal are all inputted to the EPLD U700. One of two keying signals is

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Chapter 3. Hardware Description

selected according the system setting within the internal logic circuit of U700 and the selected
signal controls the ON/OFF functions of the analog switch U909.

The voice signal is inputted through the microphone jack or line input on the front panel of
CSU and is provided to MSG via the voice signal processing circuit (VOP) within the CSP
unit. The voice signal supplied to MSG is inputted to the reference voltage input (VREF) pin
of the D/A converter U906 for the control of modulation degree. Since U906 is a multiplying
D/A converter, the signal inputted to VREF is amplitude-adjusted according to the inputted
data value and appears on the output (IOUT1) pin. The current output of U906 is converted
into a voltage output by U904.

Each modulation signal made through the process described above becomes the composite
signal for the modulation of carrier wave, which is combined with the addition circuit
consisting of the operation amplifier U1000 together with the precise +10V reference voltage
(DC).

This signal is inputted again to the reference voltage input (VREF) pin of the D/A converter
U1002 for the amplitude control. Hence, the amplitude-adjusted composite signal is
outputted to the output (IOUT1) pin of U1002. The current output of U1002 is converted into
a voltage output by U1003.

3.7.6. Modulation Signal Generation for Sideband

The modulation signals for sideband are two 720Hz blending signals. The blending signal is
used to obtain the continuous rotation effect of sideband antenna and it can be divided into
the COS blending signal and SIN blending signal that are supplied to the oddnumbered
antenna and even-numbered antenna respectively. The basic blending signal holds the
rectified sine wave form as shown in the figure 3-52 and the COS blending signal and SIN
blending signal have a 90°phase difference from each other.

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Chapter 3. Hardware Description

Figure 3-52 Blending Signal Waveforms

The amplitude of blending signal determines the sideband output power and this fixes the
amplitude modulation degree of 9960Hz sub-carrier wave. Therefore, the sideband output
power can be adjusted by controlling the amplitude of blending signal and as the result the
amplitude modulation degree of 9960Hz sub-carrier wave can be adjusted.

The frequency of blending signal, same to the 30Hz reference phase signal, should be highly
stabilized and phase-synchronized to the control signal of switching the antenna.

In order to accomplish it, the blending signal uses the DDS technology in the same way as
the carrier wave modulation and is digitally synthesized.

The numeric data of blending signal wave is saved in EPROM U702. U702 is separated by
the odd-numbered and even-numbered addresses and the COS signal waveform data is in the
odd-numbered addresses and the SIN signal waveform data in the even-numbered addresses.
Since 4 types of blending waveform data are saved in U702 and one of them can be selected
and used.

The COS signal waveform data read from U702 is sent to the D/A converter U1100 and the
SIN signal waveform data to the D/A converter U1103 and they are converted into the analog
signals.

The address signal of EPROM U702 and the write signal of D/A converters U1100 and
U1103 are made by the EPLD U700 together with the carrier wave modulation signal.
However in order to generate the blending signal unlike the carrier wave modulation signal,
it receives the 11.796480 MHz clock from the crystal oscillator X701 and uses that.

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Chapter 3. Hardware Description

The D/A converter U1100 and U1103 receive an accurate +10V power from the reference
voltage IC U1106 and use it as the reference voltage. Since U1100 and U1103 are the current-
output type of D/A converters, they are converted into the voltage output by using the precise
operation amplifiers U1101 and U1102.

The output of U1101 and U1103 or the COS blending signal and SIN blending signal are
divided into LSB and USB. Each blending signal is inputted respectively to the reference
voltage input (VREF) pine of D/A converter U1200 (USB COS), U1203 (LSB COS), U1300
(USB SIN) and U1303 (LSB SIN). Since U1200, U1203, U1300 and U1303 are all the
multiplying D/A converter, the signal inputted to the VREF pin is amplitude-adjusted by the
inputted data value and appears on the output (IOUT1) pin. The current output is converted
into the voltage output range of 0 V ~ -10 V by U1201, U1202, U1301 and U1302.

Figure 3-53 shows the timing of basic COS and SIN blending signals. The reason that the
blending signal waveform is reversed from the figure is because SMA requires the ‘-’
modulation signal.

1/60 1/60
sec sec

1/720
1/720
1/1440 sec
sec
COS Blending sec SIN Blending

Figure 3-53 COS/SIN Blending Signal

3.7.7. Switching Signal Generation for Antenna

The antenna switching signal is the signal to control the switching operation of ASU to obtain
the rotation effect of sideband antenna.

The antenna switching signal is supplied separately by the odd-numbered (COS) signal and
even-numbered (SIN) signal. Each switching signal consists of the LSB/USB toggling signal
1-bit and selection signal 4-bits for selecting one of 12 antennas within one group (refer to
the paragraph 3.1.4.

The frequency and timing of antenna switching signal should be very accurate and should be
precisely phase-synchronized with the 30Hz reference phase signal and blending signal.

In order to accomplish these, the antenna switching signal is generated within the internal
logic circuit of EPLD U700 by receiving the 11.796480 MHz clock from the crystal oscillator
X701.

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Chapter 3. Hardware Description

Figure 3-54 shows the timing of antenna switching signal.

For the phase synchronization, the trigger signal with the pulse width of 127ns is accurately
generated at every 1/30 second within the EPLD U700. The sequential logic circuit for the
generation of antenna switching signal and blending signal is initialized at the rising point of
this trigger signal. Also, the sequential logic circuit for the generation of 30Hz reference
phase, after the time delay corresponding to the azimuth offset set from this point, is
initialized.

As shown in the figure, the phase of even-numbered (SIN) switching signal is delayed by
1/1440 second from that of odd-numbered (COS) switching signal.

U700, in addition to the signal supplied to ASU, generates two timing signals that are
supplied to MON for monitoring the status of sideband antennas, which are the 30Hz trigger
signal and 2880Hz clock signal that are synchronized to the antenna rotation cycle.

One of the antenna switching signals generated respectively from the MSG of TX1 and TX2
is selected by the selection circuit in CSU and the level is converted and supplied to ASU.

Figure 3-54 Timing of Antenna Switching Signal

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Chapter 3. Hardware Description

SIN Antenna Select

SIN Antenna Pairs

Figure 3-55 COS Antenna Switching

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Chapter 3. Hardware Description

COS Antenna Select

COS Antenna Pairs

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Chapter 3. Hardware Description

Figure 3-56 SIN Antenna Switching

3.7.8. RF Phase Control

Figure 3-57 is the phasor diagram that shows the RF phase relationship of a carrier wave and
two sidebands.

Φ CAR

ΦLSB Φ USB
θ2
θ1

Figure 3-57 Phasor Diagram showing RF Phase Relationship

In the Doppler VOR of using double sidebands (DSB), it is important to maintain the RF
phase relation of carrier wave and two sidebands so that θ1 and θ2 are always equal (that is
θ1 - θ2 = 0).

It has only regarded the signal radiated in the air and the value of θ1 - θ2 may not be ‘0’ since
there would be a phase difference in the actual equipment by each path.

Therefore for the signal generated from CMA and SMA, ΦCAR, ΦUSB and ΦLSB need to be
adjusted so that it becomes θ1 - θ2 = k (a fixed offset value).

To accomplish it, MSG automatically adjusts the voltage applied to the Phase Shifter
included in LSB SMA and USB SMA. In reality, a fixed voltage is applied to USB SMA and
the difference (that is the voltage corresponding to the phase error) between θ1 - θ2 and k
value is applied to have the control.

Two sideband signals from LSB SMA and USB SMA are mixed with the carrier wave signal
and are converted respectively to the intermediate frequency signal of 10 kHz. Hence, the
phase of two 10 kHz intermediate frequency signals holds the values (θ1 and θ2)
corresponding to the difference between carrier wave and two sideband phase.

MSG inputs two 10 kHz signals supplied from LSB SMA and USB SMA to the Time
Interval Counter and calculates the value of θ1 - θ2.

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Chapter 3. Hardware Description

Since the 10 kHz intermediate frequency signals supplied from two SMAs are the sine wave
type of analog signals, they are first inputted to the IN2- and IN3- pins of the voltage
comparator U1504 and converted into the TTL level of square wave.

The time interval counter, as a digital logic circuit, is implemented within the EPLD U400.
The measured results are read by the microprocessor U300.

MSG software periodically reads the values measured from the time interval counter,
converts them into the phase values, and calculates the phase error value which is the
difference in the preset RF phase offset. Calculate the voltage to be applied to the phase
regulator of LSB SMA and USB SMA from this value and automatically adjust the RF phase
by setting the value to the D/A converters U1702 and U1704.

3.7.9. Other Control and Monitor

In addition to the contents described above, MSG sets the oscillating frequency of SYN
which is the transmission frequency of the system, controls the ON/OFF of SMA and CMA,
and monitors the operation status by measuring the output power of carrier wave and
sideband and its internal temperature.

MSG, in order to set the transmission frequency of the system, transmits the frequency data
to the PLL circuit included within the SYN of CMA and SMA through the 3-line serial data
interface.

The 3-line serial data interface consists of three signals DATA, CLOCK and ENABLE and
all of them are controlled through the GPIO A of the microprocessor U300. DATA and
CLOCK are used publicly by CMA and two SMAs and are connected respectively to the
PA2 and PA3 pins of U300. ENABLE is used individually to all. CMA is connected to the
PA4 pin of U300, USB SMA to PA5, and LSB SMA to PA6.

U1404, as the A/D converter equipped with the SPI serial data interface, is controlled through
the SCC3 of the microprocessor U300. The precise reference voltage IC U1405 supplies a
precise +5V reference voltage to U1404. U1404 has the 8-channel input and each input is
used in the following ways.

 CH 1 (AIN1): Measure the forward directional (traveling wave) power of carrier


wave  CH 2 (AIN2): Measure the reverse directional (reflective wave) power of carrier
wave  CH 3 (AIN3): Measure the USB COS output power  CH 4 (AIN4): Measure
the LSB COS output power  CH 5 (AIN5): Measure the USB SIN output power 
CH 6 (AIN6): Measure the LSB SIN output power  CH 7 (AIN7): Not used 
CH 8 (AIN8): Not used

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Chapter 3. Hardware Description

Each measured signal is sampled and detected from PDC and sent to MSG and they are
supplied to the respective inputs of A/D converter via the buffer of having used the OP AMP
U1400, U1401, U1402 and 1403. The allowable voltage range of each input is 0 V ~ 5 V.

When measuring the carrier wave power, the amplitude varies periodically since the signal
sampled from PDC is amplitude-modulated by the 30Hz sine wave. In order to indicate the
average output power, 24 data are taken and averaged to get the average power for the cycle
(1/30 second) of modulated signal.

To accomplish it, the trigger signal of indicating the start point of modulation signal and the
synchronized sampling clock signal are supplied to the GPIO port of the microprocessor
U300 from the EPLD U700. The microprocessor U300 issues an interrupt whenever a pulse
is inputted to the corresponding port and calculates the average of inputted carrier wave
power.

The digital temperature sensor U1801 included in the MSG board uses the 3-line serial data
interface and is connected to the GPIO A of the microprocessor U300. MSG software
periodically reads the temperature from U1801 and monitors the status.

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Chapter 3. Hardware Description

3.8. CSU
3.8.1. Appearance of CSU

Front Panel of CSU

Figure 3-58 shows the front panel of CSU.

Figure 3-58 Font Panel of CSU

LEDs
LED Name Color Description

POWER Green ON: When power is normally supplied


OFF: When power is cut-off

TX1 Green When power is normally supplied to TX1

TX2 Green When power is normally supplied to TX2

MON1 Green When power is normally supplied to MON1

MON2 Green When power is normally supplied to MON2

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Chapter 3. Hardware Description

Switches
Switch Description

TX1 ON Not used

TX1 OFF Not used

TX2 ON Not used

TX2 OFF Not used

Ports
Port Description

MIC The microphone input of voice to be included in the composite modulation signal
of carrier wave

TSG OUT Test output for the Test Signal Generator (TSG)

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Chapter 3. Hardware Description

3.8.2. CSU Overview

Although the power, transmitter and monitor are all duplicated to improve the system
availability, there are few parts that can’t be or not practical to be redundantly constructed.
CSU, as one of these parts, includes the following functions.

The Interfaces of Supporting the Transmitter and Monitor Redundancies

Although the transmission part is redundant, the antenna itself can’t be duplicated. Hence,
there should be a function of switching over to the standby transmitter while one transmitter
has the connection.

The function of changing over to the standby transmitter is determined first by the monitor.
Since the monitor itself is duplicated, there must be an interface function that two monitors
are linked together for the control of transmitter changeover.

For the transmitter redundancy, its selection and changeover control is necessary since not
only the respective RF output signals (CAR, LSB COS, LSB SIN, USB COS and USB SIN)
but also the antenna switching control signals supplied to ASU are duplicated.

The changeover of each RF output signal is made by the coaxial relay and RF relay that are
included in PDC. The changeover of the antenna switching control signals supplied to ASU
is made by the digital multiplexing (MUX) circuit included in CSU. CSU also includes the
circuit for monitoring and driving the relays included in PDC.

Test Signal Generator (TSG)

For the self-diagnosis and integrity checking of a monitor, the precise test signal that has
accurately defined the parameter values of each modulation signal is necessary. The test
signal generator circuit for this purpose is included in CSU.

The signal generated from the test signal generator are not only distributed to both monitors,
but also supplied to the outside through the test BNC connector (T/P) attached on the front
panel.

Voice Processor (VOP)

As an option, a voice signal can be included in the composite modulation signal of carrier
wave. The voice signal is either directly connected to the microphone jack attached on the
front panel of CSU or inputted through the line input terminal on the upper side of the
equipment cabinet.

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Chapter 3. Hardware Description

Both cases are distributed to both of TX1 and TX2 MSGs while passing through the signal
processing steps such as amplification, filtering and compression. CSU includes the analog
signal processing circuit necessary for these.

Interface to the Collocated DME (or TACAN) Equipment

Generally, VOR is collocated and operated together with the DME or TACAN equipment.
The collocated VOR/DME or VOR/TAC uses the same IDENT and transmits the IDENT
consisting of the Morse code 4 times every 30 seconds according to the rules of ICAO Annex
10. Of these, the transmission is made 3 times by VOR and 1 time by DME or TACAN.

To accomplish these, it is necessary to have the function of linking the equipment to IDENT.
CSU includes the interface circuit necessary for these, such as the Morse code keying circuit.

Analog Opto IDENT KEYING Line Input Line VOICE1


Source Amp Amp
Switch Coupler Receiver
Driver
EPLD Analog Compressor BPF
MUX
Opto IDENT KEYING
Coupler VOICE2
MIC Input
Amp Amp
Changeover Part DME Interface

Voice Input

Hot Plug-In Hot SWAP


Control
Test Signal Multi Source Relay Selection
Control
EPLD EPROM DAC Amp Vibrator Driver

Hot Plug-In / SWAP Part Test Signal Generation EPLD

RS485 Antenna Selection Timing


Driver

Changeover & Timing

Power [+28V, +15V, -15V, +5V]

Figure 3-59 Interface Signal to DME/TACAN

3.8.3. Major Parts of CSU


Part Name P/N Description

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Chapter 3. Hardware Description

EPLD EPM7192 192 Macrocells, Programmable Logic Device

EPLD EPM7064 64 Macrocells, Programmable Logic Device

D/A Converter AD7945BR 12-bit, Parallel, Digital-to-Analog Converter

Analog Filter LMF100 High Performance Dual Switched Capacitor Filter

Analog IC SSM2166 Microphone Preamplifier with Variable Compression

Interface IC MAX3045 ±10 kV ESD-protected, Quad 5V RS-485/RS-422 Transmitters

Interface IC TD62783AP 8CH High-Voltage Source Driver

3.8.4. Redundancy Support Interface of Transmitter and Monitor

AERIAL MON1 AERIAL A Coaxial Relay SEL A


Multi Vibrator Source Driver
AERIAL MON2 AERIAL B Coaxial Relay SEL B
U500 U501

AERIAL MON1
AERIAL MON2
Changeover Status
Antenna Timing MSG1 RF Power Status
Antenna Timing MSG2 PLD
U400
RS485 Driver
DCLK U401

RS485 Driver Antenna Timing


U402

RS485 Driver
U403

Figure 3-60 Control Signal Switching Block Diagram

The digital logic circuits for supporting the redundancy of transmitter and monitor are all
implemented in the EPLD U400.

Of these two duplicated transmitters, the monitor determines which side is on the aerial state
by connecting the antenna or which side is on the standby state by connecting to the dummy
load. Monitor decides the transmitter to be connected to the antenna according to a user’s
command or by judging from the monitoring result of transmission signal and transmits a
short pulse type of control signal (TX1_AERIAL or TX2_AERIAL) to CSU for the
corresponding transmitter selection.

Since the monitor itself is duplicated, this control signal is supplied from both of the monitors.
These signals are all inputted to EPLD U400 and they select the transmitter chosen first in
the priority selection circuit to be connected to the antenna. The selection result is not only
supplied to the actual transmitter changeover circuit, but also sent to both MONs and both
MSGs for confirming the selection result.

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Chapter 3. Hardware Description

According to the transmitter selection result, the RF relay drive circuit and antenna switching
signal selection circuit inside of EPLD U400 are controlled.

The RF relay drive circuit consists of the Mono-stable Multi-vibrator U500 and highvoltage
Source Driver U501. The latch-type of RF signal changeover relay included in PDC requires
a +28V pulse. U500 generates a pulse of about 100ms in length at the drop point of selection
control signal from EPLD. U501 converts this pulse signal to the voltage +28V necessary to
operate the relay and supply it to PDC.

The antenna switching signal selection circuit is implemented as a logic circuit inside of
EPLD U400. Each 10-bit antenna switching signal supplied from both MSGs is inputted to
the digital switch (MUX) circuit inside of U400. According to the transmitter selection result
described above, this switch selects the antenna switching signal supplied from the
corresponding transmitter and makes the output. The selected signal is converted to the TTL
compatible level or differential signal in the RS-485/RS-422 line drive IC U401, U402 and
U403 and sent to ASU.

3.8.5. Test Signal Generator (TSG)

Test Signal Selection


Test Signal MON1
Amp
DAC
U602
PLD ROM Address EPROM DAC Data Amp Amp
7.864320
MHz U600 U601 LPF Test Signal MON2
Amp
U700

Test Signal BNC


Amp
V Ref
U603

Figure 3-61 Block Diagram of Test Signal Generator

Test Signal Generator, same to MSG, uses the DDS technology and generates the precise test
signal accurately defined for the signal parameter of each element.

The DDS control circuit for the generation of test signals is implemented within EPLD U600.
U600 operates by receiving a clock of 7.86432 MHz from the crystal oscillator X600.

The waveform data of test signals is saved in EPROM U601. U601 can save up to 16 different
test signal waveforms. Of these one test signal is selected according to the control signal from
LCU and supplied to both monitors.

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Chapter 3. Hardware Description

The waveform data saved to U601 are sequentially sent to the D/A converter and converted
into the analog signals. Since U601 is a current output type of D/A converter is converted
into the voltage signal from the conversion circuit consisted of OP AMP U604 and outputted
via the OP AMP buffer U605.

U603, as a precise voltage generator IC, supplies the +5V precision voltage as the reference
voltage of U602.

Since the test signal generated from the DDS circuit includes the high-frequency quantization
noises, they can be removed by passing through the analog filter U700. U700, as a
programmable Switched Capacitor Filter (SCF), consists of the 4th Chebyshev low pass filter
with the cut-off frequency of 20 kHz. The clock signal necessary for U700 is supplied with
98.034 kHz in EPLD U601.

The signals that have passed through the filter U700 are supplied respectively to the test BNC
connectors attached on the front panel of both monitors via the OP AMP buffer U701 and
U702.

3.8.6. Voice Signal Processing

Line Line
Amp Voice
Input U1100
Receiver
Amp MSG1
1020 Hz 300~300Hz
Analog Compresso
Notch 0 BPF
U110
MUX r U1103
MIC U1200
Filter U1201,
Amp 2
Input U1202 Voice
Amp MSG2

LINE/MIC
Selection

Figure 3-62 Block Diagram of Voice Signal Processor

The voice signal is inputted to the voice processing circuit of CSU via the microphone jack
attached on the front panel or the line input terminal on the upper side of the cabinet.

Since the line input is a 600 Ω balanced differential signal, it is converted into the common
unbalanced single-ended signal and inputted to the amplifier U1101-B analog switch U1102
via the I/O separated transmitter TR1100 and line receiver U1100.

The microphone input signal is directly inputted to the analog switch U1102 via the amplifier
U1101-A.

U1102 outputs one of two inputs according to the control signal from LCU. The output signal
of U1102 is inputted to the IC U1103 for the voice compression and compressed by 15:1.

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Chapter 3. Hardware Description

The compressed voice signal passes through the active band reject filter consisted of U1200.
The 1020Hz element that can cause interference to the Morse code IDENT by this filter is
rejected.

The voice signal that has passed through U1200 again passes through the 4-layer active band
pass filter consisted of U1201 and U1202. The noise signals beyond the 300~3000 Hz voice
signal band is rejected by this filter.

The voice signals that have passed the filter are distributed to the MSGs of both transmitters
via the OP AMP buffer U1203.

3.8.7. Interface with the Collocated DME or TACAN

When operating by linking with VOR or DME (or TACAN), it can be divided by the master
unit that transmits the IDENT by generating the keying signal and the slave unit that transmits
the IDENT by receiving the keying signal.

When VOR operates as the master, DME operates as the slave. Oppositely when DME
operates as the master, VOR operates as the slave. MARU 220 can be set to operate as a
master or slave with the software.

Also, it can be divided into two according to the circuit configuration, when the master is the
sink current (Figure 3-63) or the source current (Figure3-64). MARU 220 supports above 2
cases and the setting can be changed with the software.

Figure 3-63 When the Master is the Current Sink and the Slave is the Current Source

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Chapter 3. Hardware Description

Master Slave

to MSG
KEY
Vbias R

Current Source Current Sink

Figure 3-64 When the Master is the Current Source and the Slave is the Current Sink
When VOR Is Keying

First, IDENT generation occurs from MSG. At this time, the keying signals of IDENT not
only key the IDENT of VOR within MSG, but also supply it to DME via CSU.

CSU receives the keying signals from the MSGs of two transmitters TX1 and TX2 and input
them to the analog switch U300. U300 selects the keying signals from the corresponding
transmitter and switches the transistor Q304, according to the selection signals.

Q304 operates the Photo-coupler PT300-B and generates the signal that is separated by power
and ground. This signal switches the Darlington-connected transistors Q300 and Q301 and
operates the keying circuit of DME, by using the power on the side of DME.

The VOR status signals supplied to DME are also inputted and selected as the analog switch
U300 in both MSGs and supplied to the transistors Q302 and Q303 after being separated into
power and ground through the transistor Q305 and Photo-coupler PT300-A.

When DME Is Keying

The keying signals from DME are converted into the TTL control signals from CSU and
distributed to the MSGs of both transmitters.

CSU operates the Photo-coupler PT-301 by receiving the keying signals from DME.

Both are supported through the selection relay REY300. REY300 operates the Photocoupler
PT301-A directly when the keying signal is a current source and selects to operate the PT301-
A by using the +15V power when the current is a sink. The control of the relay REY300 is
driven through the logic reversal circuit U301-E and transistor Q308 according to the
selection signal of LCU.

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Chapter 3. Hardware Description

The signal separated by power and ground through PT-301 is supplied to both MSGs after
passing through the switching transistor Q306, logic reversal circuit U301-A and U301-B.
The status signal of DME is also supplied to both MSGs via Q307 and logic reversal circuit
U301-C and U301-D after passing through the current sink/source selection relay REY301
and Photo-coupler PT301-B.

VOR ID/OP MSG1 Opto Coupler VOR ID KEYING


PT300
VOR ID/OP MSG2 Analog Switch
U300
Opto Coupler VOR Status
CHOV
PT300

DME ID/OP MSG1 DME ID KEYING


Inverter Opto Coupler
DME ID/OP MSG2 U301 PT301 DME Status

Figure 3-65 Block Diagram of DME Interface

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Chapter 3. Hardware Description

3.9. CSP
3.9.1. Appearance of CSP

Figure 3-66 Appearance of CSP

Keypad
Classification Name Description

CONTROL MENU Key to enter to MENU or exit from MENU

LOCAL Key to switch between LOCAL and REMOTE

C/O Key to initiate CHANGEOVER

◄ Key to move to PRIOR item

► Key to move to NEXT item

SEL Key to SELECT item

SPEAKER SILENCE Key to MUTE alerting sound

LED Lamp
TRANSMITTER ACTIVE Indicates that the TX is in Active state, i.e. on Aerial

STANDBY Indicates that the TX is in Standby state, i.e. on Dummy Load

FAULT Indicates that the TX is in Faulty state

MONITOR ACTIVE Indicates that the MON is in Active state

BYPASSED Indicates that the MON is in Bypassed state

ALARM Indicates that the MON is in ALARM condition

3.9.2. Internals of CSP

CSP is a user interface device attached on the upper side of the equipment cabinet. CSP is
the I/O device connected to the primary microprocessor of LCU.

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Chapter 3. Hardware Description

CSP consists of 1 240x64 mono-graphic LCD, 12 LED lamps, 7 manipulation keys, and 1
warning sound generation speaker. The connection between CMS backplane and CSP is
made through the 25P DB25 connector attached on the fixture inside of the equipment
cabinet.

Almost all the system functions, such as the status indication and parameter setting changes
of the system, can be controlled by using CSP without needing separate LMMS and RMMS.

3.9.3. Major Parts of CSP


Name P/N Description

LCD GM246401GNCWA 240x64 Graphic LCD

LED HLMP-2655 Light Bar LED, RED

LED HLMP-2755 Light Bar LED, YELLOW

LED HLMP-2855 Light Bar LED, GREEN

Tact Switch PMS-SW-4 Tact Switch

DC/AC Inverter CXA-L10A Inverter for CCFL, In: +5V, 600mA / Out: 300Vrms, 5mA

Analog IC MAX685 CMOS charge-pump DC/DC Converter

3.9.4. Circuit Description

Figure 3-67 Internals of CSP

LCD Operation

The graphic LCD is directly connected to the lower 8-bits of the microprocessor U300 data
bus of LCU.

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Chapter 3. Hardware Description

For the LCD bias in addition to the +5V power supplied to CSP, a negative DC power is
needed. This power is supplied from the DC/DC converter U404. U404 generates the -10 V
DC power and this power is divided through the variable resistor VR300 for the brightness
adjustment and supplied to LCD.

The graphic LCD used to CSP uses the Cold Cathode Florescent Lamp (CCFL) as the back
light. In order to operate CCFL, a high-voltage of high frequency AC power is needed. This
power is supplied from the DC/AC inverter U301. U301 generates the 300 Vrms and 30 kHz
AC power needed for CCFL from the +5V DC power.

Notice
Since there is a risk of an electric shock, please be careful not to touch the output poles
of the inverter when power is applied.

Key Input Area

The 7 key inputs are sent to LCU through the buffer U300. Since each key line has the pull-
up resistors of R300 ~ R306, it maintains the high status when having no input and outputs
the low signal when having a key input. The prevention of key chattering is implemented by
software.

LED Control

LED is controlled by LCU, the High or Low is outputted on the latches U402 and U403, and
this signal is inputted to the sink drivers U400 and U401 to have the On/Off control of LED.

3.10. AC / DC Converter

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Chapter 3. Hardware Description

3.10.1. Appearance of AC/DC Converter

Figure 3-68 Front Panel of AC/DC

LED Lamp
Name Color Description

NORMAL Green When AC/DC is normally operating

FAIL Red When AC/DC is in abnormal condition

Adjust Point
Name Description

V-ADJ No output voltage adjustment

LOAD SHARE No load balance adjustment

Switch
Name Description

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Chapter 3. Hardware Description

INPUT Input power switch

3.10.2. AC/DC Overview

AC/DC, as a Switch Mode Power Supply (SMPS), converts the inputted commercial AC
power into DC 28V.
AC/DC is constructed with a highly-efficient high-frequency conversion method and has the
hot plug-in structure that allows attaching/detaching it on the front side of the cabinet.

Since a digital ammeter is attached on the front side of the unit, the current load can be easily
checked.

Notice
Since there is a risk of an electric shock, please be careful not to touch the output poles
of AC/DC when power is applied.

3.10.3. Operations

Figure 3-69 shows the internal configuration of AC/DC converter.

Figure 3-69 Internals of AC/DC Converter

The AC power of +220V is supplied for the input of AC/DC. The allowable variation of input
voltage is in the range of AC 187 V ∼ AC 253 V and the allowable variation of input

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Chapter 3. Hardware Description

frequency is in the range of 47 Hz ~ 63 Hz. The maximum output current of DC 28V is 78A
per unit.
The surge protection circuit of using Varister is included in the input part of AC/DC. This
circuit, when the surge current is flowed into the power input line due to the lightning strikes,
prevents the system from a breakdown by absorbing them.

The input filter in the back of the surge protection circuit rejects the noise elements included
in the input power. The power that has passed through the input filter soon goes through the
inrush current limiting circuit. The inrush current limiting circuit restricts the excessive
current at the time of applying power to a certain extent. This prevents the operation of a
circuit breaker in the power transmission system due to the inrush current at the time of
applying power.

The AC power that has passed through the protection circuit and filter is rectified by the full-
wave rectification circuit of using a bridge diode. Then, the AC elements are rejected by a
smoothing capacitor and it is converted into a complete DC power.

Right behind the rectification circuit, there is a Power Factor Correction (PFC) circuit. This
circuit, by controlling the power factor nearing to ‘1,’ leaves the resistor elements only in the
transmission side. Through these, the occurrence of harmonic noise is reduced and the
efficiency of power use is improved.

The DC voltage that has passed through the PFC control circuit is applied to the Pulse Width
Modulation (PWM) circuit. The PWM circuit consists of the switching MOSFET,
transformer and feedback circuit.

PWM circuit samples the output voltage, compares it with the reference voltage, and varies
the pulse width applied to the switching MOSFET in comparison to the voltage error. If the
output voltage is lower than the reference voltage, the pulse width is increased and if the
output voltage is higher than the reference voltage, the pulse width is decreased.

The transformer converts the pulse power switched by the switching MOSFET to a low AC
voltage. The output of transformer is inputted again to the rectifier of using a high-speed
diode and converted into DC.

Since the switching noise and ripple elements are included much in the output of the 2 nd
rectifier, they are removed through the output filter.

The output voltage and the detection circuit for measuring the current are included in the
output area of AC/DC.
The detected voltage is sent to the PWM control circuit through the feedback circuit. If an
excessive voltage or current is detected, the PWM control circuit breaks an alarm and cuts
off the output to protect the circuit. Since the PWM control circuit has the built-in
temperature sensing circuit, it is also protected from overheating.

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Chapter 3. Hardware Description

3.11. DC / DC Converter
3.11.1. Appearance of DC/DC Converter

Figure 3-70 Front Panel of DC/DC Converter

LED Lamp
Name Color Description

NORMAL Green Indicates that AC/DC is normally operating

FAIL Red Indicates that a alarm is occurred in the AC/DC

Adjust Point
Name Description

5V-ADJ No adjustment for +5V output voltage

Switch
Name Description

INPUT Input power switch

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Chapter 3. Hardware Description

BATTERY Switch for connecting/breaking the backup battery


3.11.2. DC/DC Overview

DC/DC converts the DC +28V power supplied by AC/DC into five other voltages (+5V,
+7V, +15V, -15V and +28V) needed for the system.

DC/DC is connected to the backup battery. When the DC 28V power is not supplied from
AC/DC, the power is supplied from this battery. Also when the backup battery is discharged,
it charges the backup battery by using the DC 28V power supplied from AC/DC.

Same as AC/DC, DC/DC is basically consisted of the switch mode power supply (SMPS)
circuit. Also, it has the hot-swap structure that allows attaching/detaching a part easily from
the front side.

3.11.3. Operations

The following figure shows the overall block diagram of a DC/DC converter.

Figure 3-71 Internals of DC/DC Converter

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Chapter 3. Hardware Description

An input line filter is included within the input part of DC/DC. This filter removes the
noise included within the power supplied.

In addition to the +28V primary power, DC/DC outputs the DC voltage of +5V, +7V, +15V,
-15V, and -24V necessary for the system. The circuit block that generates each voltage is
identical in the operating principle to the output voltage except for the difference in their
polarity. Therefore, the explanations below are made while basing on one circuit block.

The DC voltage that has passed through the input filter is applied to the Pulse Width
Modulation (PWM) circuit. The PWM circuit consists of the switching MOSFET,
transformer and feedback circuit.

PWM circuit samples the output voltage, compares it with the reference voltage, and varies
the pulse width applied to the switching MOSFET in comparison to the voltage error. If the
output voltage is lower than the reference voltage, the pulse width is increased and if the
output voltage is higher than the reference voltage, the pulse width is decreased.

The transformer converts the pulse power switched by the switching MOSFET to a low AC
voltage. The output of transformer is inputted again to the rectifier of using a high-speed
diode and converted into DC.

Since the switching noise and ripple elements are included much in the output of the 2 nd
rectifier, they are removed through the output filter.

The output voltage and the detection circuit for measuring the current are included in the
output area of DC/DC.
The detected voltage is sent to the PWM control circuit through the feedback circuit. If an
excessive voltage or current is detected, the PWM control circuit breaks an alarm and cuts
off the output to protect the circuit.

3.12. RCMU
3.12.1. Appearance of RCMU

Figure 3-72 Appearance of RCMU

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Chapter 3. Hardware Description

Keypad
Classification Name Description

CONTROL MENU Key to enter to MENU or exit from MENU

LAMP TEST Key to TEST indicator LAMPs

SILENCE Key to MUTE alerting sound

◄ Key to move to PRIOR item

► Key to move to NEXT item

SEL Key to SELECT item

LED Lamp
Classification Name Description

TRANSMITTER ACTIVE Indicates that the TX is in Active state, i.e. on Aerial

STANDBY Indicates that the TX is in Standby state, i.e. on Dummy Load

FAULT Indicates that the TX is in Faulty state

MONITOR ACTIVE Indicates that the MON is in Active state

BYPASSED Indicates that the MON is in Bypassed state

ALARM Indicates that the MON is in ALARM condition

3.12.2. RCMU Overview

RCMU is a remote control monitor unit. All the status monitoring and controlling the MARU
220 DVOR system can be accomplished at a remote place by using RCMU.

RCMU is connected to the LCU of the equipment cabinet through a communication circuit.
RCMU sends major system information to the RMU that RCMU is connected.

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Chapter 3. Hardware Description

UART
RS232 RS232 /1, RS232/2
UART Clock : Driver
ROM 14.7456MHz
MPU DATA Socket Modem1
MODEM
RS232
SRAM UART Driver RS232
SCC1

Buffer
RS232 RS485/1 , RS485/2
UART Driver

EPLD RS232 (Not Used)


RS232 Driver

DVOR Status
Microprocessor Part

Communication Part

Alarm Sound Speaker out DATA Buffer


Graphic LCD KEY & LED +5V SMPS
Amp
Buffer
R-CSP Power [+5V]
Alarm Sound
R-CSP I/F

Figure 3-73 Block Diagram of RCMU

Remote Control Monitor Unit (RCMU) is a remote control and monitor unit. RCMU is
equipped with the graphic LCD, LED lamp and keypad that are identical to those attached
on the equipment cabinet. Since the menu configuration shown on the graphic LCD screen
is identical to that of CSP, the system monitoring and controlling function can be executed
at a distance.

RCMU, connected to the LCU of the system cabinet through a dialup or private line,
exchanges the data necessary for the system control and monitor.

Also, it relays the system status monitoring data received from LCU to RMU. RCMU and
RMU are connected from each other via the RS-422/485 compatible 4-line communication
circuit and as many as two RMUs can be connected to one RCMU.

Additionally, it has an expansion output port that indicates a brief status of the system. This
port can be used to interface with the centralized monitoring system.

RCMU is physically consisted of the main board, the R-CSP (RCMU CSP) board of having
LCD, KEY and LED, the RCMI (RCMU Interface) board for the interface to external
systems, and a small switching power supply (SMPS).

3.12.3. Major Parts of RCMU


Part Name P/N Description

CPU MC68302 M68000 Core, Integrated Multiprotocol Processor

RAM K6T4016 256k x 16 bit Low Power CMOS Static RAM

EPROM M27C4002 4 Mb (256Kb x 16) UV EPROM

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Chapter 3. Hardware Description

UART TL16C552 Dual Asynchronous Communications Element with FIFO

EPLD EPM7128 128 Macrocells, 100 I/O pins, Programmable Logic Device

Modem MT5634 Socket Modem, V.92/56k V.34/33.6k Embedded Modem

Reset IC DS1232 Micro Monitor, Reset, Watchdog Timer / Monitor

LCD GM246401 240x64 Graphic LCD

LED HLMP-2655 Light Bar LED, RED

LED HLMP-2755 Light Bar LED, YELLOW

LED HLMP-2855 Light Bar LED, GREEN

Tact Switch PMS-SW-4 Tact Switch

DC/AC CXA-L10A Inverter for CCFL


Inverter In: +5V, 600mA / Out: 300Vrms, 5mA

Analog IC MAX685 CMOS charge-pump DC/DC Converter

SMPS CS15-5 AC/DC Switch Mode Power Supply, 5V/3A

3.12.4. 3.12.4 Processor

U300 is the primary control microprocessor of RCMU. U300 is based on the M68000 core
and the 1152-byte dual port RAM, programmable timer, serial communication controller
(SCC), and 24-bit general GPIO are integrated within the chip. The data and address buses
of U300 are connected to the peripheral devices through the 3-state buffer U500-U504.

The crystal oscillating circuit X300 supplies a clock of 29.4912 MHz to U300.

U301, as the microprocessor monitor circuit IC, includes the reset signal generation circuit,
power monitor circuit and watchdog timer. U301 supplies a reset signal to the microprocessor
U300 and at the same time, it monitors whether U300 operates normally.
The cases that U301 outputs a reset signal follow as below.

1) When power is turned on


2) When the reset switch is pressed for 250ms or more
3) When the Address Strobe (AS) of U300 is not outputted for 1.2 seconds or more
(Watchdog timer – microprocessor error)
4) When the Vcc voltage falls below 4.5V (abnormal power voltage)

LCU uses the following storage devices different from each other. All the rest of storage
devices except for the serial EEPROM are positioned within the memory space of the
microprocessor U300.

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Chapter 3. Hardware Description

 EPROM U600 and U601: Store the program code and data 
SRAM U602: Store the temporary data used during a program execution 
EEPROM U605: Store the non-volatile parameters

When the microprocessor U300 is initialized after receiving the reset signal, U300 executes
the program code saved in the EPROM U600 and U601.

U400 is a programmable logic device (PLD). It includes the logic circuits such as the address
decoder and GPIO port. The address decoder inside of U400 decodes the addresses for each
memory and I/O device from the address bus and control bus signals of U300 and generates
the Chip Selection Signals. The GPIO port of U400 consists of the latch circuit for the output
port and the digital switch circuit for the input port.

Figure 3-74 RCMU Processor

Expansion Port Output

This port outputs the status value that shows the normality of the system. When this system
is normal, the PB8 of U300 outputs the High (5V).
3.12.5. Serial Communication Control

RCMU, in addition to the 3 SCCs included in U300, has the synchronous communication
controllers (UART) U800, U801 and U802. Accordingly, a total of 9 serial communication
ports are available. The usage of each port shall be followed as below.

 U300 SCC1: Reserved (for


debugging)  U300 SCC2, SCC3:
Reserved (not used)
 U800 UART0, UART1: Remote
control through RS-232C (REM1 and REM2)

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Chapter 3. Hardware Description

 U801 UART0, UART1: Remote control


through internal MODEM or RS-
232C (REM3 and REM4)  U802 UART0, UART1: Remote
control through RS-485 (RMU1, RMU2)

The SCCs of U300 are reserved and hence, not used.

The UART0 and UART1 of U801 can either be connected to the default built-in socket
MODEM or use the direct RS-232C interface without using an internal MODEM by user’s
setting. In this case, set SW900 and SW901 to the ‘RS232C’ position and remove the internal
socket MODEMs U1103 and U1104. In order to use the MODEMs again, set SW900 and
SW901 to the ‘MODEM’ position and install the socket MODEMs U1103 and U1104.

The asynchronous serial communication controllers U800, U801 and U802 operate by
receiving the output 14.7456 MHz from U400.

UART CLOCK:
14.7456MHz RS232 RS232/1 Communication
Driver
Data UART U900
TXD1 RS232 Driver
TXD Device
/CS_MSG1,2 U800 RS232/2
RXD1 U1001 RS232
Driver Communication
U901
RS232 (Not Used)
Microprocessor MSG1/2 Communication

UART CLOCK:
14.7456MHz RS232 Driver U902 MODEM1
Data
MODEM1
/CS_REM1,2 UART
Device
Buffer U801
RS232 Driver U903
MODEM2
EPROM UART CLOCK: MODEM2
14.7456MHz
SRAM EPLD /CS_MSG1,2
REM1/2 Communication
U400 /CS_REM1,2
PLD CLOCK: /CS_REM3,4
29.4912MHz
UART CLOCK:
14.7456MHz RS485
RS485/1 Communication
Driver
Data UART U1002
Microprocessor Part Peripheral Logic Device
/CS_REM3,4 U802 RS485
Driver RS485/2 Communication
U1003

REM3/4 Communication

Figure 3-75 RCMU Communication Part

The I/O process of serial communication data is made asynchronously by using an interrupt
method. When a data is received from the outside, the corresponding UART requests an
interrupt from the microprocessor U300. When an interrupt request is submitted, the
microprocessor U300 temporarily stops the code in execution, executes the interrupt
processing routine and reads the data from UART. The interrupt request signal of U800 is
inputted to the microprocessor through the PB8 and PB9 pins of U300, the interrupt request
signal of U801 through the PB10 and PB11 pins, and the interrupt request signal of U802
through the IRQ6 and IRQ7 pins.

The microprocessor U300 monitors the RXRDY and TXRDY pins of each UART through
U700 and U701. If one of these pins becomes the ‘L’ state, the microprocessor U300 judges

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Chapter 3. Hardware Description

that the corresponding UART is in the state possible to receive data and executes reading and
writing the data.

3.12.6. Controlling the LED Lamp, Graphic LCD and Keypad

RCMU directly controls the LED lamps, graphic LCD and keypad on the front panel.

These devices are directly connected to the 8-bit lower data buses D0 - D7 of the CPU
through the 3-state data buffer U1101.

EPLD U400 decodes the address of U300 and generates the respective chip selection signals
/CSLCD, /CDSWITCH, /CSLED1 and /CSLED2 for the I/O devices included in CSP.

The chip selection signals and other control signals of U300 are connected to the front panel
through the 3-state data buffer U1102.

3.12.7. Generating the Audible Alerts

RCMU generates the warning signals of about 1000 Hz by using the timer-2 of the
microprocessor U300. This signal is outputted to the TOUT2 pin of U300, amplified in the
audio amplification IC U1107, and played through the speaker on the front panel.

The magnitude of the alarm sounds and IDENT tone can be adjusted by turning the volume
VR1101.

3.12.8. Power Supply Unit (SMPS)

The power supply unit (SMPS) supplies the power of +5V to RCMU.

3.13. RMU

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Chapter 3. Hardware Description

3.13.1. Appearance of RMU

Figure 3-76 Appearance of RMU

Button Switch
Name Description

SILENCE Key to MUTE alerting sound

LAMP TEST Key to TEST indicator LAMPs

LED Lamp
Name Description

TX1 Indicates that the TX1 is in Active state, i.e. on Aerial

TX2 Indicates that the TX2 is in Active state, i.e. on Aerial

NORMAL Indicates that the DVOR is in NORMAL operation

BYPASSED Indicates that the DVOR is in Bypassed state

ALARM Indicates that the DVOR is in ALARM condition

COMM Indicates that Communication error is occurred

3.13.2. Block Diagram of RMU

RMU receives the status information of the system from LCU or RCMU and indicates them
on the 6 LED lamps on the front side. Also, it generates the warning sound when an alarm
occurs.

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Chapter 3. Hardware Description

The major functions of RMU shall be followed as below.

 Indicate the major status of the system  Generate the warning


sound when an alarm occurs

The block diagram of RMU shall be followed as below.

TXD RS485_TXD
RS485 Driver
RXD U301 RS485_RXD Alarm Sound Speaker out
Amp
RS485 Driver
Alarm Sound

MPU LED Control


Sink Driver LED Bar
U400 LED400~LED405
U300

LED Drive

+5V SMPS

Silence Lamp Test


KEY Input KEY KEY Power [+5V]
Microprocessor Part
Key Input

Alarm Sound

Figure 3-77 Internals of RMU

RMU can be constructed as below.

 Microprocessor & peripherals: Control the RMU


 LED lamps and switch interface: Operate the LED lamps on the front
side and interface the button switches
 Power supply unit: Supply the power of +5V to RMU from SMPS
 RS-485 interface: Convert the TTL/RS485 level

3.13.3. Major Parts of RMU


Part Name P/N Description

Microcontroller ATmega16 8-bit AVR microprocessor with 16k Bytes ISP Flash

Interface IC MAX485 RS-485/RS-422 Transceiver

LED HLMP-2655 Light Bar LED, RED

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Chapter 3. Hardware Description

LED HLMP-2755 Light Bar LED, YELLOW

LED HLMP-2855 Light Bar LED, GREEN

SMPS CS15-5 AC/DC Switch Mode Power Supply, 5V/3A

3.13.4. Circuit Description

Microprocessor U300 executes most of the controls for RMU. U300 operates by receiving
the clock of 14.7456 MHz from the crystal oscillator X300.

The communication to RCMU or LCU is made through the RS485 serial communication.
The serial communication ports built into U300 are used. The TTL output signals of U301
are converted into the RS485 level.

The control of LED lamps is made through the GPIO ports PC0~PC5 of U300.

RMU operates by receiving the power of 5V from the built-in power supply unit (SMPS).

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Chapter 4. Antenna

Chapter 4. Antenna
4.1. Overview
Figure 4-1 shows the antenna system of MARU 220.

Sideband Antenna

Carrier Antenna DME Antenna

Figure 4-1 DVOR Antenna System

Counterpoise

Counterpoise has a circular metal structure. The signals radiated below the horizontal plane
of an antenna radiation element from the general installation environment are randomly
reflected on an uneven surface and causes multiple path interferences. Counterpoise prevents
the random reflection by functioning as a uniform reflection object on the horizontal plane.

Counterpoise, as the support structure for the antenna mechanically installed, plays the role
of a reflective object electrically.
The parts of counterpoise are made of the melted zinc galvanizing iron and steel. Although
its height on the surface generally ranges from 2.4m to 6m, it can be changed according to
the environmental conditions. The radius is about 30m and this also can be changed according
to the conditions.

The carrier wave antenna and sideband antenna as shown in the figure 4-2 are arranged on the
counterpoise. When collocated with DME or TACAN, the DME or TACAN antenna is also
installed on the counterpoise.

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Chapter 4. Antenna

Figure 4-2 Antenna Arrangement on the Horizontal Plane of Counterpoise


Carrier Wave Antenna

Carrier wave antenna is used to radiate the carrier wave signals in the air.

In order to radiate Omni-directionally on a horizontal plane, the carrier wave antenna uses
the Alford loop type and is installed in the middle of the counterpoise.

When DME or TACAN is collocated, the DME or TACAN antenna can be installed above
the carrier wave antenna. When it is not appropriate to install the DME antenna due to the
installation position, the DME antenna can be installed on the side of the counterpoise.

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Chapter 4. Antenna

Sideband Antenna

Sideband antenna is used to radiate the 9960Hz sub-carrier wave sideband signals in the air.

Same to the carrier wave antenna, the Alford loop type of sideband antenna is used to radiate
Omni-directional on the horizontal plane.

Forty-eight sideband antennas are installed in the interval of 7.5°on the circle perimeter
6.76m (113 MHz standard) away from the carrier wave antenna.

In case of the sideband antenna, power is fed sequentially in the counter-clock direction to
have the rotational effect. Each sideband antenna, according to the sequence of power feed,
is numbered 1 to 48, starting from the antenna to the magnetic north with ‘1.’

Field Monitor Antenna

Field monitor antenna is used to monitor the aerial radiation of VOR signal.

As for the monitor antenna, the partially horizontal 4-element Yagi antenna is used.

Monitor antenna, due to the characteristics of Doppler VOR, should be installed a minimum
of 80m away from the carrier wave antenna.

4.2. Transmit Antenna


4.2.1. Characteristics of Alford Loop Antenna

MARU 220 DVOR uses the Alford loop antenna for the transmission of carrier wave and
sideband signals.

Alford loop antenna is partially horizontal and Omni-directional within the horizontal plane.
Also, it has higher radiation efficiency than other generic loop antennas, due to its wide
radiation face.

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Chapter 4. Antenna

Figure 4-3 Vertical Radiation Pattern When h=λ/2


+90°

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Chapter 4. Antenna

-90°

Figure 4-4 Vertical Radiation Pattern in a Free Space

Figure 4-5 Horizontal Radiation Pattern

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Chapter 4. Antenna

4.2.2. Appearance of Transmission Antenna

Same to the sideband antenna, carrier wave antenna uses the Alford loop antenna. Two pipes
of supporting the DME antenna are penetrated from above the Radome to the floor.

Carrier Antenna Sideband Antenna

Figure 4-6 Appearance of Transmission Antenna

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Chapter 4. Antenna

Radome

Radome is an antenna protection cover. Since it is made of the Fiber Reinforced Plastic
(FRP), Radome protects radiation elements and other fixtures from snow, rain and wind.

The Radome shape of sideband antenna is circular from the horizontal plane and conic from
the side. The Radome for carrier wave antenna differs from the sideband antenna in that two
pipes of supporting the DME antenna are penetrating and the upper cover is flat.

The lower cover is fixed to the pedestal together with the radiation elements and the upper
cover laid on top of the lower cover is fastened with 6 screws.

Pedestal

Pedestal is the structure of supporting and fixing the antenna. Since it is made of the melted
zinc galvanizing steel, it is not easily corroded and is designed to stand against a strong wind
of max 200km/h.

The lower end of pedestal is fixed to the ring above the counter and the upper end supports
the Radome cover. The Balun cable and matching stub is positioned in the empty space of
the pedestal.

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Chapter 4. Antenna

4.2.3. Electric Structure of Transmission Antenna

Radiation Element

The Alford loop antenna consists of 4 elements in a half-wave (λ/2) length. Each radiation
element is folded in a triangular shape as shown in the following figure.
The respective parts of a-b and a’-b’ form the folded half-wave (λ/2) dipole antenna. Two
half-wave dipole antennas are faced from each other.
The electric connection of two dipole antennas is crossed so that the electric distribution
makes a circular direction. As shown in the figure, a is connected to a’ and be is connected
to b’.

The electric distribution makes a circle from the outside that forms 4 sides of the Alford loop.
It is because two half-wave elements are offset as the direction from the inner folded part
becomes opposite to each other. Accordingly, only the outside current distribution forms the
radiation pattern and the inner current distribution doesn’t affect much on the radiation
pattern.

Figure 4-7 Electric Distribution of Alford Loop Antenna Radiation Elements

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Chapter 4. Antenna

Disc Capacitor

Disc capacitor is a parallel circular plate attached respectively near to the rapid electricity
application points of two dipole antennas that makes up the radiation element. The resonant
frequency can be finely adjusted by turning the circular disc to the left and right.

Matching Stub

Matching stub is used to match the impedance of antenna transmission line.


Generally, there are the short-circuited and open-circuited types of stubs and MARU 220
DVOR uses the open-circuited stub.

Figure 4-8 Matching Stub Assembly

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Chapter 4. Antenna

The impedance matching job can be done by adjusting the length ‘11’ of positioning piece
and the length ‘l2’ of tuning stub. Since the lengths are adjusted to the installation frequency
from the factory, it is not recommended to adjust it from the field.

Balun

Balun is the device that converts the unbalanced transmission line to the balanced
transmission line and vice versa.

Since Alford loop antenna has a dipole antenna structure that is basically symmetric, it has
to use the balanced transmission line. However, the coaxial cable used commonly has the
unbalanced characteristics. Therefore, the Balun of converting the unbalanced to the balanced
is needed.

MARU 220 uses the RG-214 coaxial cable Balun with the length λ/2. The signal that has
passed through λ/2 transmission line will have the phase reversed by 180°from the original
signal. The signal reversed by 180°can be obtained from the provided signal by using these
characteristics.

Also, since this Balun holds the 4:1 impedance conversion characteristics, it can convert the
antenna input impedance 300 Ω to 75Ω. By doing so, matching to the standard transmission
line impedance 50 Ω becomes easier.

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Chapter 4. Antenna

Figure 4-9 4:1 Coaxial Cable Balun


4.3. Monitor Antenna

Boom

Director Reflector

Director
Radiator
Mast

Figure 4-10 Monitor Antenna

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MARU 220
Doppler VHF Omni-directional Radio Range

Technical Manual

Volume I

EQUIPMENT DESCRIPTION
Copyright© 2005-2007 MOPIENS, Inc.
All rights reserved

This document contains copyrighted and proprietary


information, which may not be disclosed to others for any
purposes without written permission from MOPIENS, Inc.