PY Eca Digi 2017

U1A
A 5 1 W
B 6
74S86N U2B
2 X
C 4
U3C
74S86N 7 Y
D
74S86N
3 Z
CIRCUITO FÍSCO (EN PROTOBOARD) CIRCUITO LÓGICO (SÍMBOLOS)
^ caret.
OBSERVE LA IMAGEN. 4 LEDs Rojos (entrada), 4 LEDs Azules (Salida)

ENTRADA(S): 1001. Prendido-apagado-apagado-prendido
SALIDA(S): 1101 Prendido-prendido-apagado-prendido
4 LED´S ROJOS PARA INDICAR LAS ENTRADAS ACTIVADAS (HIGH,

PRENDEN), DESACTIVADAS (LOW, APAGADAS).
LAS ENTRADAS ESTÁN NORMALMENTE CONCECTADAS A CERO VOLTS
(LOW) A TRAVES DE UN RESISTOR DE 1KΩ PARA QUE PRENDAN LOS
LED’S AL ACTIVAR EL INTERRUPTOR (MINI DIP) CORRESPONDIETE.
LAS ENTRADAS NO DEBEN DEJARSE FLOTANDO (SIN CONEXIÓN).
EL MINI-INTERRUPTOR CONECTA LOS +5 VOLTS PARA ACTIVAR
ENTRADAS. 4 LES AZULES PARA INDICAR EL ESTADO DE LA SALIDAS..
LOS RESISTORES SON PARA LIMITAR LA CORRIENTE DE LOS LED´S.
R≥ 220Ω EN SALIDAS.
LA ALIMENTACIÓN PARA LA FAMILIA DE INTEGRADOS TTL SERIE 74LSXX
ES DE +5V.
ESTE ES UN SISTEMA DIGITAL COMBINACIONAL (COMBINATORIO )
REVISIÓN 2017- II PROF. G. ACOSTA M.
1
Reglas generales 3
Programa 4
Niveles de voltaje 5
Hojas de seguimiento 6
Relación de Prácticas y Proyectos 10
Ejercicios básicos 12
Relación de Prácticas y Proyectos (parte II) 14
Ejemplos de Programación C++ Arduino 26
Modelos de reactivos de evaluación. 36
Digital electronics concepts 44
Flip-flop (summary) 56
2
Reglas generales:
1.- Del Reglamento: El alumno debe ser puntual y constante. Se dará una tolerancia de 5
minutos en la entrada. Se considerarán 3 retardos equivalente a una falta.
2.- Cada falta será sancionada con 3 puntos menos del promedio general que obtenga el
alumno.
3.- En consecuencia:
Con más de 10 faltas cualquier promedio el alumno estará reprobado.
4.- Los alumnos podrán disponer de 3 permisos durante el semestre para no asistir,
preferentemente notificándolo previamente.
5.-La evaluación del curso será de la siguiente tabla.
(a) Proyecto(s) de la unidad. 40 puntos
(b)Asistencia, puntualidad, participación, actitud, tareas, etc. 10 puntos
(c) Evaluación teórica 50 puntos
6) Los proyectos deben de incluir:
(a) Reporte escrito en computadora, Word u otro software. Circuitos hechos
con los paquetes de programación (Multisim, Hotwire, Proteus, etc.)
(b) Objetivo del proyecto. Introducción teoría básica (marco teórico) breve. Conclusiones
al final. ¿Qué verifiqué? ¿Qué aprendí? ¿Cuánto aprendí? Etc.
(c) Cálculos. Diagramas físico de conexiones, diagrama esquemático.
(d) Fotos escaneadas de la evidencia del buen funcionamiento del proyecto.
Con el visto bueno (o aprobación del profesor).
(e) Costos parciales de cada componente y el total del proyecto
7. Los proyectos pequeños son individuales.
8.- Se aplican las reglas conocidas. Si no se presenta en la fecha indicada, la entrega del
proyecto, pasa a segunda oportunidad.
9.- Subir en cuenta YOUTUBE (opcional) todas las prácticas y proyectos (haga su guión
primero)
10.- La asesoría por parte del profesor, será de acuerdo a las necesidades del alumno.
11.- El profesor hará la revisión, el seguimiento y registro de los proyectos.
12.- En todos los proyectos puede consultar Internet para ideas o consulta de hojas de
datos de los dispositivos. Si baja algún circuito asegúrese de que venga explicado y/o
calculado, de lo contrario usted tendrá que hacerlo.
13.- En todo caso primero verifique el estado de la sonda (o punta de prueba) del equipo
de medición y prueba y después arme su circuito.
Atentamente.
Prof. Guillermo Acosta Montiel.
P R O G R A M A.
3
UNIDAD I FUNDAMENTOS DE SISTEMAS DIGITALES
1.1 Fundamentos de los sistemas digitales

1.2 Sistemas numéricos
1.3 Operaciones básicas
1.4 Códigos
1.5 Aplicaciones
EVALUACIÓN
UNIDAD 2 FUNCIONES Y COMPUERTAS LÓGICAS

2.1 Compuertas lógicas
2.2 Tablas de verdad
2.3 Compuertas simples y compuertas
2.4 Álgebra de Boole
2.5 Leyes y postulados
2.6 Minimización de funciones
2.7 Familias lógicas
EVALUACIÓN
UNIDAD III LÓGICA COMBINACIONAL

3.1 Mini y Maxi términos
3.2 Simplificación de funciones K-Maps
3.3 Método Quine McClusky (tabular)
3.4 Diseño con SSI.
3.5 Mux y deMultiplexores
3.6 Codificadores y decodificadores.
3.7 Diseño con MSI
EVALUACIÓN
UNIDAD IV
4.1 Introducción. Diseño de Pulsos de reloj (parámetros de éstos.)
4.2 Flip Flops: R-S; J-K;4.2 Flip Flops: R-S; J-K; T y D.
4.3 Tipos de registros.
4.4 Contadores y secuenciadores.
4.5 Síncronos y Asincrono
4.6 Memorias RAM y ROM, EEPROM (Agregado)
4.7 Arreglos PAL y GAL (Agregado)
4.8 Introducción μControl (Agregado)
EVALUACIÓN
4
NIVELES DE VOLTAJE. SON IMPORTANTE PARA QUE FUNCIONE
CORRECTAMENTE EL CIRCUITO INTEGRADO. (I.C. EN INGLES)
La información binaria se representa en un sistema digital por cantidades físicas

denominadas señales, Las señales eléctricas tales como voltajes existen a través
del sistema digital en cualquiera de dos valores reconocibles y representan una
variable binaria igual a 1 o 0. Por ejemplo, un sistema digital particular puede
emplear una señal de 3 volts para representar el binario "1" y 0.5 volts para el
binario "0". La siguiente ilustración muestra un ejemplo de una señal binaria.
Como se muestra en la figura, cada valor binario tiene una desviación aceptable
del valor nominal. La región intermedia entre las dos regiones permitidas se cruza
solamente durante la transición de estado. Los terminales de entrada de un
circuito digital aceptan señales binarias dentro de las tolerancias permitidas y los
circuitos responden en los terminales de salida con señales binarias que caen
dentro de las tolerancias permitidas.
Competencias genéricas y específicas
Competencias básicas. Son la combinación de destrezas, conocimientos y

actitudes que se aplican para adaptarse en diferentes contextos sociales.
Competencias genéricas. Se refieren al conjunto de conocimientos, actitudes,

valores y habilidades que están relacionados entre sí, ya que en combinación,
permiten el desempeño satisfactorio de la persona que aspira a alcanzar metas
superiores a las básicas.
Competencias específicas. Las competencias específicas se adquieren con la

transmisión y asimilación por parte de la persona, a partir de una serie de
contenidos relativos a las áreas básicas del saber humanístico; conceptos, teorías,
conocimientos instrumentales, habilidades de investigación, formas de aplicación o
estilos de trabajo que definen una disciplina concreta. Competencias que resultan
necesarias para dominar un conocimiento, para después aplicarlo a un área
específica.
5
ELECTRÓNICA DIGITAL
AL ENTREGAR UN PROYECTO AL PROFESOR SE

REQUIERE PRESENTAR.
 EL ANÁLIS MATEMÁTICO CORRESPONDIENTE.
UNIDAD I: FUNDAMENTOS DE SISTEMAS DIGITALES

 EL DIAGRAMA ELÉCTRICO
 LA SIMULACIÓN
 EL CIRCUITO FÍSICO.
 MEDICIONES PREVIAS HECHAS POR EL ALUMNO.
6
 Formato de seguimiento de prácticas y proyectos
 SI TODO ES ACEPTABLE, EL PROFESOR FIRMA EL
AVANCE.
SI LO COPIÓ DE INTERNET, QUE INTERNET SE LO
CALIFIQUE.
Pre-práctica o
% Avance
PROYECTO MODALIDAD
Fecha de Fecha de
PUNTOS
entrega 1 entrega 2 Firma y comentarios
del docente
PY1 (1-Bit full adder)
Sumador completo de
Individual
1 BIT. Sistema
mecánico o
electromecánico
PY2
Sumador completo de En equipo

1 BIT. Compuertas
básicas NOT and OR
PY3
Sumador completo de1 En equipo

Bit, con compuertas
universales EXOR
PY4
Sumador completo
En equipo
de1 Bit programado
Arduino u otra
plataforma
Preprácticas:
Ejercicio 1
Ejercicio 2
Ejercicio 3
7
UNIDAD II: FUNCIONES Y COMPUERTAS LÓGICAS
% Avance
Pre-práctica o Fecha de Fecha de
MODALIDAD PUNTOS
PROYECTO entrega 1 entrega 2
Firma y comentarios
del docente
PY1
Compuertas lógicas
Individual
de dos entradas 1
salida (vea y lea
información abajo)
PY2
Convertidor de En equipo
Binario a código
Gray 4 BIT’s
PY3
Decodificador de En equipo
BCD a 7 Segmentos
PY4
Función Lógica
z(A,B) En equipo
(vea y lea
información abajo)
PY4
Sumador / Restador
de 4 BIT’s En equipo
8
UNIDAD III: LÓGICA COMBINACIONAL
% Avance
MODALIDAD PUNTOS
Firma y comentarios
del docente
PY1
Potencia al cuadrado:.
En equipo
y = x2 (3-bit’s)
Entrada/Salida: binaria
PY2
Potencia al cuadrado:.
y = x2
En equipo
(Teclado 9-entradas)
Salida 7-Segmentos
PY3
Medición de la En equipo
Constante de gravedad
g.
PY4
Bin-level control
En equipo
system
(vea y lea información)
UNIDAD IV: FUNCIONES Y COMPUERTAS LÓGICAS
9
% Avance
MODALIDAD PUNTOS
Firma y comentarios
del docente
PY1
Secuenciador En equipo
PY2
Contador bidireccional En equipo
PY#
Conteo
Convertidor de digital ascendente
a analógico (DAC) de
3 bits con resistores UP/Down
ponderados, R, R/2, counter
R/4, RLoad Opción
escalera R-2R. o DAC Individual
en C. I.
PY3
Semáforo de dos vías En equipo
Vea opciones en clase
PY4
Dispenser machine.
En equipo
En equipo
PY4 Marcador de
basquetball 4_displays
UNIDAD V: FUNDAMENTOS DE SISTEMAS DIGITALES
10
% Avance
Fecha de Fecha de
PROYECTO MODALIDAD PUNTOS
entrega 1 entrega 2
Firma y comentarios
del docente
PY1
Letrero (desplegado)
OPCIONES:
7-SEGMENTOS
14-SEGMENTOS Todo grupo
4x MATRIZ 5X7
DIFERENTES
DIMENSIONES CADA
SEMESTRE
PY2
DESPACHADOR DE
UNO A 10 PRODUCTOS
Equipo
(LATAS O CANICAS) A
PETICIÓN DE USUARIO.
USO DEL TECLADO
QWERTY
PY3
IDEM ANTERIOR, USO Equipo

DE UN TECLADO DE
MEMBRANA
PY4
RELOJ BÁSICO: HORAS,

MINUTOS 7-Seg. UN Equipo
LED COMO
SEGUNDERO.
Games. Master Mind. Equipo

Acertar # aleatorio.
Nim 2 variantes. Software
11
Sistemas Numéricos y Códigos
Nombre: SUMADOR COMPLETO DE UN BIT (v.1)
Enunciado:
1) CON TRES INTERRUPTORES A, B Y C, (DE ACCIÓN MOMENTANEA)
SE DESEA CONTROLAR DOS LÁMPARAS X, Y, DE TAL MANERA QUE:
a) SI SE OPRIME UN SOLO INTERRUPTOR A LA VEZ PRENDE LA
LÁMPARA Y (LSD).
b) SI SE OPRIME UN PAR (SIMULTÁNEAMENTE) PRENDE LA
LÁMPARA X. (MSB)
c) SI SE OPRIMEN O ACTIVAN LOS 3 INTERRUPTORES
(SIMULTÁNEAMENTE) PRENDE AMBAS LÁMPARAS X, Y.
Sumas que realiza:
Entradas Salidas Entradas Salidas

(0) 0 + 0 + 0 = 00 (1) 1 + 0 + 0 = 01
(2) 0 + 1 + 0 = 01 (3) 0 + 0 + 1 = 01
(4) 1 + 1 + 0 = 10 (5) 1 + 0 + 1 = 10
(6) 0 + 1 + 1 = 10 (7) 1 + 1 + 1 = 11
Proyecto: INDIVIDUAL.
Competencia Específica: Generación de tecnología básica.

Se le sugiere construya sus interruptores. Tiene la opción de hacerlo con
interruptores comerciales, o electromecánicos (reles)
12
El ejemplo (abajo), es un montaje en PVC con dos interruptores rotativos 1P3T X4
y un relevador 2P2T a 12V. (P=polo, T=tiro)
Vista frontal A+B+C=S Vista posterior Vista lateral
Este es un prototipo hecho por el profesor (hace muchos años…)
Nombre: 1-BIT FULL ADDER (v.2)
EN EQUIPO ( 2 O 3 INTEGRANTES)
2) DISEÑE Y COMPRUEBE EL FUNCIONAMIENTO DE UN SUMADOR

COMPLETO DE UN BIT (1-BIT FULL ADDER) IMPLEMETADO CON
COMPUERTAS BÁSICAS NOT, AND, OR. CON CIRCUITOS
INTEGRADOS DE LA FAMILIA TTL O CMOS. ( 74LS04, 74LS08, 74LS32)
CIN
ENTRADAS (3) A 1-bit S0 SALIDAS(2)
B Full S1 (= COUT )
Adder
13
Competencias Específicas, Usar:
Competencias Específicas Usar e identificar las
OR significa conección en paraleo (2 o más interruptores)
AND significa conección en serie (2 o más interruptores)
NOT significa conección en serie con la carga de un switch NC

O bien, un switch NA conectado paralelo con la carga
Referencia: (Link) Digital Electronics -- Basic Logic Gates
14
Nombre: 1-BIT FULL ADDER (v.3)

COMPLETO DE UN BIT (1-BIT FULL ADDER) CON COMPUETAS
UNIVERSALES EXOR , CON INTEGRADOS DE FAMILIA TTL O CMOS.
(74LS86)
Competencias Específicas: Usar compuertas universales XOR or XNOR.
Link: Digital Electronics -- Boolean Algebra and Simplification
Nombre: 1-BIT FULL ADDER (SOFTWARE) (v.4)


COMPLETO DE UN BIT (1-BIT FULL ADDDER) PROGRAMADO CON
CUALQUIER PLATAFORMA. EJEMPLO ARDUINO ( EN LENGUAJE C+)
U OTRA PLACA.)
Competencias específicas: Programación y verificación en placa Arduino.
PLACAS ARDUINO
15
The Arduino language is based on C/C++.
EN CUANTO LE SEA POSIBLE COMPRE UNA PLACA ARDUINO, LA MÁS

RECOMENDABLE ES (QUE ADQUIERA) ARDUINO MEGA 2560 (derecha)
Consulte: http://www.arduino.cc/en/Reference/HomePage [Consulte ya]
PREPRÁCTICAS Y PROYECTOS
EJERCICIO 1.- OBTENGA LA EXPRESIÓN BOOLENA PARA LA SALIDA

S(A,B,C), Y SIMPLIFÍQUELA FACTORIZANDO TÉRMINOS COMUNES.
LAS ENTRADAS SON LOS INTERRUPTORES A, B, C; LOS CUALES TIENEN 6
CONTACTOS CADA UNO, ALGUNOS NORMALMENTE ABIERTOS (N.A.) Y
OTROS NORMALMENTE CERRADOS (N.C.)
SWA SWB SWC
L5 L5
L6
L7 L7
L8
L9
SALIDA (CORRIENTE O VOLTAJE)
16
EJERCICIO 2: ANALICE EL SIGUIENTE CIRCUITO Y HAGA EL PROGRAMA
CORRESPONDIENTE. VERIFIQUELO.
J2
J1 4 3
1 5 X1
V1 Key = A Key = B 100V_100W
120 Vrms
60 Hz
0°
2
Visite estos links.
https://www.wisc-online.com/learn/career-clusters/manufacturing/dig2603/boolean-
theorems-single-variable
http://www.engr.sjsu.edu/caohuut/EE270/Documents/Lecture01.pdf
http://proyectoelectronico.com/
http://proyectoelectronico.com/leds/secuenciador-de-luces-led.html
EJERCICIO 3.- COMPUERTA “OR” verifíque circuito.
17
Key = A
J1
LED2
7 5
J2
U2
1A VCC
1B 4B
1Y 4A
2A 4Y
2B 3B
2Y 3A
GND 3Y
LED3
6 74LS32N
Key = B
1
R1 V1
220Ω 5V
3
2 4
R3 R2 LED1
1kΩ 1kΩ
Si se activa uno u otro interruptor o ambos prende el LED. LED = A + B
Nombre: COMPUERTA LÓGICA DE DOS ENTRADAS UNA SALIDA.
INDIVIDUAL
1) ANALICE EL CIRCUITO SIGUIENTE. HAGA
o A) LA TABLA DE VERDAD
o B) OBTENGA LA ECUACIÓN BOOLEANA.
o C) IDENTIFIQUE EL TIPO DE COMPUERTA
o D) HAGA LA PROGRAMACIÓN CORRESPONDIENTE.
o E) VERIFIQUE EN ARDUINO.
3
R1 V1
1kΩ 12 V
1 Vout
ENTRADAS Q1
R2 Salida
Vin1 4 2
10kΩ
2N2222A
5 R4
Vin2
10kΩ
0 GND
18
Nombre: CONVERTIDOR DE BINARIO A CÓDIGO GRAY DE 4 BIT´S
2) DISEÑE UN CONVERTIDOR DE SISTEMA NUMÉRICO BINARIO A CÓDIGO

GRAY DE 4 BIT´S. ENTRADAS Y SALIDAS BINARIAS.
ENTRADA BINARIA 4 BIT´S SALIDA BINARIA 4 BIT´S
A W
CONVERTIDOR
B DE BINARIO X
4 BIT´S. A
C CÓDIGO GRAY Y
D Z
a) CON CIRCUITERÍA INTEGRADA (HARDWARE)

b) PROGRAMADO en C+ (ARDUINO U OTRO)
c) SIMULADO (MULTISIM, PROTEUS U OTRO)
Nombre: DECODIFICADOR DE BCD A 7-SEGMENTOS,

3) DISEÑE UN DECODIFICADOR DE BCD A 7-SEGMENTOS,

COMPRUEBE CON UN SIMULADOR (MULTISIM,PROTEUS U OTRO)
LA TABLA CORRESPONDIENTE ES LA SIGUIENTE.
ENTRADAS S A L I D A S (SEGMENTOS) a, b, c, d, e, f, g.
ABCD a b c d e f g
0000 1 1 1 1 1 1 0
0001 0 1 1 0 0 0 0
0010 1 1 0 1 1 0 1
0011 1 1 1 1 0 0 1
19
0100 0 1 1 0 0 1 1
0101 1 0 1 1 0 1 1
0110 1 0 1 1 1 1 1
0111 1 1 1 0 0 0 0
1000 1 1 1 1 1 1 1
1001 1 1 1 1 0 1 1
1010 X X X X X X X
…. …. ….. …. …. …. …. ….
1111 X X X X X X X
LAS COMBINACIONES DEL 1010 AL 1111 SON IRRELEVANTES X (DON´T

CARE.) Entrada =1 (Energizada o activada) Salida=1 (LED prendido)
Nombre: FUNCIÓN LÓGICA Z(A,B) ,

OBTENGA.
 LA FUNCIÓN Z(A,B) DEL CIRUITO SIGUIENTE

 SIMPLIFIQUELA.
 PROGRAME
 VERIFIQUE EN ARDUINO.
20
U1A
A 1 U3A
5 U4A
74LS04N 7 Z
2 74LS08N
B U2B 3 U3B 674LS32N
4
74LS04N 74LS08N
Nombre: SUMADOR / RESTADOR DE 4 BIT’S.
4) DISEÑE UN SUMADOR RESTADOR DE DOS PALABRAS DE ENTRADA

DE 4 BITS CADA UNA, CON UNA ENTRADA DE CONTROL C. CON C=1
RESTA: S = A- B. CON C=0 SUMA: S = A + B . VERIFQUE CON
HARDWARE INTEGRADO SUGERIDO 74LS83 ( 4-BITS FULL ADDER),
MÁS COMPUERTAS NECESARIAS PARA EL CONTROL.
DIAGRAMA (ESQUEMA) A BLOQUES.
Cin
ENTRADAS SALIDAS
A So (LSB)
SUMADOR/ S1
RESTADOR S2
B DE 4 BIT´S S3
S4 (= Cout)
CTRL
Cin = Carry in (ACARREO DE ENTRADA)

Cout = Carry out (ACARREO DE SALIDA)
21
A, B, SON ENTRADAS DE 4 BIT´S, ES DECIR, A = [A0, A1, A2 ,A3]
B = [B0, B1, B2 ,B3]
Competencia específica:
Uso del Método Heurístico para el diseño de un sistema digital.
el siguiente diagrama de flujo (que es un algorítmo) le puede ayudar a

visualizar el circuito digital requerido.
la única diferencia es que el circuito físico realiza laoperación en paralelo
(es un combinacional)
DIAGRAMA DE FLUJO
SUMA / RESTA
ENTRADAS
A, B, C
NO
C=0
¿ SI
PROCESO
B = B’
S=A+B S= A+ B
MSB=1 NO ( A < B)
SI (A > B)
S=S+1 S = S’ COMPLEMENTO
Salidas (Respuestas)
Donde:
22
S
A, B OPERANDOS. C = ENTRADA DE CONTROL. B’ COMPLEMENTO B. Most Significant Bit
(MBS)
Debe de utilizar solo 3 paquetes integrados
OPERACIONES QUE REALIZA EL SUMADOR COMPLETO DE 4

BITS:
Cin
A3A2A1A0
+ B3B 2B1B0
Cout S3 S 2S1S0
Nombre: POTENCIA AL CUADRADO:. Y = X2 (3-BIT’s)

1) DISEÑE UN CIRCUITO QUE ELEVE UNA ENTRADA X BINARIA (DE 3

BITS) AL CUADRADO. SALIDA Y (BINARIA.) Y = X2, 0≤ X≤ 7
A) HARDWARE B) SOFTWARE
Nombre: POTENCIA AL CUADRADO:. Y = X2 (9-ENTRADAS)

2) DISEÑE UN CIRCUITO QUE ELEVE UNA ENTRADA X (0≤ X≤ 9),

NUEVE ENTRADAS, EL CERO SE DESPELGA SI NO SE OPRIME
NINGUNA DE LAS 9 TECLAS ETIQUETADAS DEL 1 AL 9. LA SALIDA
Y DESPLEGADA EN E VISUALIZADORES DE 7-SEGMENTOS.
Y = X2, 0 ≤ X ≤ 9 PROGRAMADO.
23
Nombre: CONSTANTE DE GRAVEDAD (MEDIR)
3) DISEÑE UN SISTEMA DIGITAL PARA MEDIR PARA LA GRAVEDAD

TERRESTRE. DESPLEGADO AUTOMÁTICO DE LA CONSTANTE “g”
USO DE SENSORES INFRA ROJOS.
CANICA (U OBJETO QUE CAE)

MVB ASTABLE
EMISOR 1 SENSOR 1 FF Latch

U2B
Set
74S08N Q
Termina Reset
EMISOR 2 SENSOR 2
Conteo
CONTADOR 000 – 999

Salidas en binario
Reset Inicia conteo
Manual
¿Cuál es la máxima altura de la que puede caer su objeto con este
cronómetro?
T = 1 ms (periodo del Multivibrador MVB astable) medirá milisegundos
Altura perpendicular sugerida entre sensores de 50 a 80 centímetros.
Nombre: BIN-LEVEL CONTROL SYSTEM

Tomado del texto: Industrial Electronics. Thomas E.Kissel. Prentice Hall
Haga el programa correspondiente al sistema lógico siguiente.
24
Entradas: Stop, Start a G1. Bin 1 Full al inversor y éste a G4. Bin 1 empty a G2.
Bin 2 Empty a G6 y a G3. Bin 2Full al inversor éste a G3 y G5. From
Output of G1 a G5.
Salidas: Fill Bin 1 solenoid. Alarm Horn. Fill Bin 2 solenoide.
Intermedio: 2-minute timer. Alarm Acknowledgment.
25
Nombre: SECUENCIADOR
 ANALICE EL CIRCUITO
 OBTENGA LAS ECUACIONES DE LAS ENTRADAS DE LOS FLIP
FLOP’s (ECUACIONES DE EXCITACIÓN)
 DIBUJE EL DIAGRAMA DE ESTADOS
 ESQUEMATICE EL DIAGRAMA DE TIEMPOS
 OBTENGA LA VERSIÓN PROGRAMADA.
 VEFIFIQUE EN ARDUINO U OTRA PLATAFORMA
+5V 1
2 U4A
5 2 U3A
2 2 ~1PR
9
U2A U1A 74LS08N
4 4 1J
R1 R2
~1PR ~1PR 1Q 15 R3
220Ω 220Ω
4 1J 1Q 15 4 1J 1Q 15 1 1CLK 220Ω
6 7
CLOCK PULSE 1 1CLK 1 1CLK 16 1K ~1Q 14 8
16 1K ~1Q 14 16 1K ~1Q 14 ~1CLR LED1 LED2
LED3
~1CLR 3 ~1CLR 3 74LS76N
3 74LS76N 3 74LS76N
0
Observe que todos los preset (parte superior del FF) y los clear (parte
inferior) están conectados a “uno lógico” (+5v. No flotando) para que no
actúen o active esas entradas y mal funcione el circuito.
26
Prototipo (Material didáctico construido por el maestro)
IMAGEN. CANDADO ELECTRÓNICO. LA PROPUESTA DEL CIRCUITO

ES UN SIMPLE REGISTRO DE CORRIMIENTO CON UNA ENTRADA DE
DATOS (D) Y UNA ENRADA DE RELOJ (C). EL USUARIO COMÚN NO
SABE DISTINGUIR CUAL BOTÓN ES EL DATO Y CUAL ES EL PULSO
DE RELOJ. EL SISTEMA ACTIVA UN MVB ASTABLE Y SUENA LA
BOCINA CUANDO SE DA LA SECUENCIA (CÓDIGO) CORRECTA.
Nombre: CONTADOR BIDIRECCIONAL

DISEÑE UN CONTADOR BIDIRECCIONAL PARA (UNA SOLA PUERTA

CON DOS SENSORES CONTIGUOS) QUE CUENTE Y DESPLEGUE
EVENTOS ACTUALIZADOS DE ENTRADA Y SALIDA 00-99, DE ITEMS
O DE PERSONAS.
SI ENTRAN ES ASCENDENTE (ACUMULATIVO), SI SALEN ES
DESCENDENTE (SUBSTRACTIVO). USAR SENSORES INFRA-ROJOS O
VISIBLES Y DESPLEGADO EN 7-SEGMENTOS Y PANTALLA LCD.
27
Nombre: SEMÁFORO DE DOS VÍAS.
4) DISEÑE UN SEMÁFOR DE DOS VÍAS, EL VERDE DESTELLA 3
VECES ANTES DE PASAR AL AMBAR. PROTOTIPO A ESCALA
FOCOS DE 60 WATT (VERDE, AMBAR ROJO)
HAGA PRIMERO DEL DIAGRAMA DE TIEMPOS.
Nombre: DISPENSER MACHINE

4 ) DISIGN A CANDY MACHINE CONTROLLER THAT DISPENSES ONLY

TWO TIPES OF CANDIES, ACCEPTS ONLY QUARTERS, ALSO,
ANYTIME THERE IS MONEY IN THE MACHINE, THE COIN RETURN
MAY BE DEPRESSED. FINALLY, THE USER IS HUMAN AND MAY
SPEND CONSIDERABLE TIME IN FRONT OF THE MACHINE TRYING TO
MAKE A DECISION. THE PRICE OF THE CANDIES IS TWO QUARTERS.
RETURN 2 COINS
WAIT WAIT
INSERT INSERT 2nd COIN State

State A State B
C
ONE COIN RETUR
ONE COIN
Select
Product X product
sold ctct
Product Y
STATE DIAGRAM.
PROYECTO ANTERIOR, ADAPTADO DEL TEXTO “DIGITAL DESIGNING WITH

PROGRAMMABLE LOGIC DEVICES”. JOHN W. CARTER. PRENTICE HALL.
P128.
28
IMAGEN DEL PROTOTIPO, CORTESÍA DEL ALUMNO CAMPOS VILLEDA
DAVID Y EQUIPO. UN SERVOMOTOR CONTROLA LA SALIDA DEL
PRODUCTO SELECCIONADO. UN INDICADOR VISUAL (LCD) DESPLEGA EL
NOMBRE DEL PRODUCTO DESPACHADO. (EJEMPLO: CHOCOLATE O
CARAMELO), Señalado con una flecha el LCD (Liquid Crystal Display)
Nombre: MARCADOR DE BASQUETBALL

5) DISEÑE UN TABLERO MARCADOR DE BASQUETBOL, AL MENOS

DOS DÍGITOS PARA CADA EQUIPO (00-99), CON OPCIÓN A
CORREGIR CUANDO LOS PUNTOS SE LE HAYAN DADO AL OTRO
EQUIPO.
ENTRADAS: BOTÓN 1 PARA REGISTRAR CANASTOS DE UN PUNTO,
BOTÓN 2 PARA REGISTRAR CANASTOS DE DOS PUNTOS, BOTÓN 3
PARA REGISTRAR TRES PUNTOS. Y UNO O DOS BOTONES MÁS
PARA HACER LA CORRECCIÓN.
TRANSMISIÓN EN BLUE TOOTH O ULTRASONIDO. INDICADORES
VISUALES DE 50 cm DE ALTO POR 40 cm.
29
Nombre: LETRERO DESPLEGADO

EN EQUIPO (INTEGRANTES TODO EL GRUPO)
1) DIEÑO DE UN LETRERO LUMINOSO 6 INDICADORES VISUALES DE

50 cm POR 40 cm,(DIMENSIONES MÍNIMAS).
PARA DESPLEGAR MENSAJES DE MÁS DE 1000 CARACTERES,
POR CORRIMIENTO IZQUIERDO Y EFECTOS DE DESTELLO.
MULTIPLEXAND0 CADA DISPLAY CON BJT´S.
EL OBJETIVO ES DESPLEGAR NOMBRES COMPLETOS DE LOS

ALUMNOS DEL GRUPO CON LA CALIFICACIÓN OBTENIDA EN
ESTA SIGNATURA, Y UN MENSAJE PARA LA “CARRERA”
BJT DE CTRL 4 DISPLAYS DE 7 SEGMENTOS
En placa, insertados 4 BJT’s(Bipolar Junction Transistor), parte izquierda

inferior, para hacer el multiplexado de cada uno de los 4 indicadores visual
de 7-segmentos (imagen derecha arriba.)
30
A CONTINUACIÓN, ALGUNOS EJEMPLOS DE PROGRAMACIÓN.
/* Programa PARA ARDUINO (EN ESTE CASO MEGA 2560)
“ SUMADOR COMPLETO DE 1 BIT.”

http://arduino.cc/en/Reference/HomePage#.Uxd4ij95NTA
5-III-2014. NOTAS del profesor GAMO
*/
// Declaración de tipos de DATOS

int SalA = 11, // SALIDAS pines 11 y 12
SalB = 12;
int X=2, Y, Z; // Entradas Pines 2, 3 y 4
boolean A, B, C, S0, S1; // Para Conversión a valor lógico
// false= 0 (NO), true = 1 (SI)
// the setup routine runs once when you press reset:

// SE DECLARA ABAJO QUE PINs(=TERMINALES) SERÁN ENTRADAS Y CUÁLES
SALIDAS.
void setup()
{
// initialize the digital pin as an output.
pinMode(SalA, OUTPUT); // LSB = L0
pinMode(SalB, OUTPUT); // MSB = L1
pinMode(X, INPUT); // Entrada X (--> A)
pinMode(3, INPUT); // Entrada Y (--> B)
pinMode(4, INPUT); // Entrada Z (--> C)
31
// Serial.begin(9600); (usada solo para la depuración)
}
// the loop routine runs over and over again forever:

void loop()
{
X=0, Y=0, Z=0; // Entradas al inciar en cero
// Serial.println("Hola");
//LEctrura de las entradas
X=digitalRead(2); //Serial.print(X); Serial.println("-- ");
Y=digitalRead(3); //Serial.print(Y); Serial.println("--- ");
Z=digitalRead(4); //Serial.print(Z); Serial.println("---- ");
// Conversión del valor analógico a BOOLEAN

if (X ==1) A=true; else A =false;
if (Y ==1) B=true; else B =false;
if (Z ==1) C=true; else C =false;
//Serial.print("::B="); Serial.println(B); SE PUEDE USAR PARA DEPURAR
// FUNCION Logica S0 = C'(A B' + A'B) + C ( A'B' + AB)

// ! = NOT, && = AND, || = OR
S0 = !C && ( (A&& !B ) || (!A && B) ) || C && ( (!A && !B || A && B) );
//Serial.print("::S0="); Serial.println(S0);
// FUNCION // Logica S1 = A B + A C + B C
S1 = (A &&B) || (A && C) || (B && C);
//Serial.print("::S1="); Serial.println(S1);
// ABAJO:CONDICIONES para prender el led de salida
if(S0 == true) digitalWrite(SalA, HIGH); else digitalWrite(SalA, LOW);
if (S1==true) digitalWrite(SalB, HIGH); else digitalWrite(SalB, LOW);
delay(50);
// Serial.print('::'); Serial.println(Z); Serial.println('---'); Serial.println(A);

// delay(5000); Un retardo de 5 segundos, se usó solo durante la depuración
}
32
/* “ SUMADOR COMPLETO DE 1 BIT.” (1-Bit Full Adder) Prf. G. Acosta M. v3
Febrero 2018. */
int X, Y, Z; // Entradas. Se decide usar los Pines 2, 3 y 4

boolean S0, S1; // Para operaciones con valor lógico. false= 0 (NO), true = 1 (Si)
void setup()
{
// initialize the digital pin as an output or input.
pinMode(11, OUTPUT); // LSB = L0, Least Significant Bit
pinMode(12, OUTPUT); // MSB = L1, Most Significant Bit
pinMode(2, INPUT); // Entrada X (--> A)
pinMode(3, INPUT); // Entrada Y (--> B)
pinMode(4, INPUT); // Entrada Z (--> C)
}
void loop()
{
X=0, Y=0, Z=0; // Entradas al iniciar en cero. Opcional, son cero al iniciar.
//LEctrura de las entradas
X=digitalRead(2); Y=digitalRead(3); Z=digitalRead(4);
// FUNCION Lógica S0 = C'(A B' + A'B) + C ( A'B' + AB)
// ! = NOT, && = AND, || = OR. Notaciones de Arduino
S0 = !Z && ( (X&& !Y ) || (!X && Y) ) || Z && ( (!X && !Y ||XA && Y) );
// FUNCION Lógica S1 = A B + A C + B C
S1 = (X && Y) || (X && Z) || (Y && Z);
// ABAJO: CONDICIONES para prender el LED correspondiente de salida
if(S0 == true) digitalWrite(11, HIGH); else digitalWrite(11, LOW);
if (S1==true) digitalWrite(12, HIGH); else digitalWrite(12, LOW);
delay(50); //Retardo agregado arbitrariamente. Pruebe sin este
}
33
// COMPARADOR DE 4 BITS
// VERSION UNO. SIN ECUACIONES LÓGICAS(BOOLEANAS)
// Notas Prof. G. Acosta M...... 20-III-2015
//
int sala=10, salb=11, salc=12; // sala <, salb =, salc > : SALIDAS
int A, B, C, D, E, F, G, H, M, N, i;
void setup()
{
pinMode(sala, OUTPUT); pinMode(salb, OUTPUT); pinMode(salc, OUTPUT);
for (i=2; i<10; i++) pinMode(i, INPUT); // ENTRADAS A,B,C,D; E,F, G,
H. A y E =MSB; D y H =LSB.
Serial.begin(9600);
}
void loop()
{
// ABAJO: Lectura del estado actual de LASA ENTRADAS, PINS 2,3,4,5
A=digitalRead(2); B=digitalRead(3); C=digitalRead(4);
D=digitalRead(5);
E=digitalRead(6); F=digitalRead(7); G=digitalRead(8);
H=digitalRead(9);
// abajo: ECUACIONES (LÓGICA ARITMÉTICA) de variables -----
if (A==1) A=8; else A=0; if (B==1) B=4; else B=0; if (C==1) C=2; else
C=0; if (D==1) D=1; else D=0;
N = A + B + C + D; //SUMA LAS ENTRADAS SEGÚN SU PESO. A=MSB; D=LSB.
if (E==1) E=8; else E=0; if (F==1) F=4; else F=0; if (G==1) G=2; else
G=0; if (H==1) H=1; else H=0;
M = E + F + G + H; //SUMA LAS ENTRADAS SEGÚN SU PESO. E=MSB; H=LSB.
// ABAJO: CONDICIONES lógico-ARITMÉTICAS prende salidas
if (N < M) digitalWrite(sala, HIGH); else digitalWrite(sala, LOW);
//menor
if (N == M) digitalWrite(salb, HIGH); else digitalWrite(salb, LOW);
// igual NOTA VERIFICAR ASIGNACIÓN VS COMPARACIÓN
if (N > M) digitalWrite(salc, HIGH); else digitalWrite(salc, LOW); //
mayor
delay(1000); // Retardo opcional de 1 MILISEGUNDO.
// COMPARADOR DE 4 BITS VER 2.

// VERSION DOS. CON ECUACIONES (LÓGICA BOOLEANA)
//
int sala=10, salb=11, salc=12, i; // sala <, salb =, salc > : SALIDAS
boolean A, B, C, D, E, F, G, H; //
boolean w0, w1, w2, w3, x0, x1, x2, x3, w, x, y, y0,y1, y2, y3, P, Q;
void setup()
{
34
for (i=2; i<10; i++) pinMode(i, INPUT); // ENTRADAS A0..A3, B0...B3.
Serial.begin(9600);
}
void loop()
{
// ABAJO: Lectura del estado actual de LASA ENTRADAS, PINS
2,3,4,5...9
D=digitalRead(5);
E=digitalRead(6); F=digitalRead(7); G=digitalRead(8);
H=digitalRead(9);

P=A; Q=E; compara; x0=x; w0=w; y0=y;
P=B; Q=F; compara; x1=x; w1=w; y1=y;
P=C; Q=G; compara; x2=x; w2=w; y2=y;
P=D; Q=H; compara; x3=x; w3=w; y3=y;
if((x0==y0)&& (x1==y1) && (x2==y2) && (x3==y3))digitalWrite(salb,

HIGH); else digitalWrite(salb, LOW)); // igual
if ((A >E) || (B==F)&& (C >G)|| (A==E)&& (C==G)&& (D>H) || (A==E)&&

(B==F) &&(C==G)&& (D>H)|||| digitalWrite(salc, HIGH); else
digitalWrite(salc, LOW));
if ((A3<B3) || (A3==B3)&& (A2 <B2)|| (A3==B3)&& (A2==B2)&& (A1<B1) ||
(A3==B3)&& (A2==B2) &&(A1==B1)&& (A0<B0)|||| digitalWrite(sala, HIGH);
else digitalWrite(sala, LOW));
delay(1000); // Retardo opcional de 1 MILISEGUNDO.

}
void compara()
{
// Ecuación del comparador de 1-bit
w = !P && Q; y = P && !Q;
x= !P && !Q || P && Q;
}
// Decodificador de BCD a 7-segmetos cátodo común..
// VERSION DOS. SIN LÓGICA BOOLEANA...
// VERIFICADO OK
int sala=10, salb=11, salc=12, sald=13, sale=14, salf=15, salg=16;
int A, B, C, D, N, i;
void setup()
{
pinMode(sald, OUTPUT);
pinMode(sale, OUTPUT); pinMode(salf, OUTPUT); pinMode(salg, OUTPUT);
pinMode(2, INPUT); pinMode(3, INPUT); pinMode(4, INPUT); pinMode(5,
INPUT); //ENTRADAS A, B, C, D.
35
// Serial.begin(9600);
}
void loop()
{
// ABAJO: Lectura del estado actual de LASA ENTRADAS, PINS 2,3,4,5
D=digitalRead(5);
if (A==1) A=8; else A=0; if (B==1) B=4; else B=0; if (C==1) C=2; else
C=0; if (D==1) D=1; else D=0;
N = A + B + C + D; //SUMA LAS ENTRADAS SEGÚN SU PESO. A=MSB; D=LSB.
// ABAJO: Lógica para prender los segmentos a, b, c.....g
switch(N)
{
case 0: for (i=10; i<16; i++) digitalWrite(i, HIGH); break;
//prende“0"
//prende“1"
case 2: for (i=10; i<17; i++) {digitalWrite(i, HIGH);
digitalWrite(15, LOW); digitalWrite(12, LOW);} break;
//prende“2"
digitalWrite(16, HIGH);} break; //prende“3"
for (i=15; i<17; i++)digitalWrite(i, HIGH); digitalWrite(12,
HIGH);} break;
digitalWrite(11, LOW); digitalWrite(14, LOW);} break;
digitalWrite(11, LOW);} break;
case 7: for (i=10; i<13; i++) {digitalWrite(i, HIGH);} break;
digitalWrite(14, LOW);} break; //prende“9"
}
delay(1000); // Retardo opcional de 1 SEGUNDO.

for(i=10; i<17; i++) digitalWrite(i, LOW); // borrado de segmentos
[a...g]
}
36
// “ HOLA EL TEC LES DESEA FELICIDAD "
// NOTAS del profr. GAMO 5/VI/2014
// Se definen las variables del tipo "entero" (son localidades físicas de memoria
// mem es tipo caracter, y cade es una cadena de caracteres
char mem; // Variable tipo caracter

int cont=0, cont1=0, conta=0, i=0, pin; // Son contadores e índices
char cade[40]=" HOLA EL TEC LES DESEA FELICIDAD "; // Cadena de caracteres (arreglo, matriz o
void setup()
{ // Se definen lon pins del arduino del 2 al 8 como salidas
for (pin=2; pin <= 8; ++pin) {pinMode(pin, OUTPUT);}
// Serial.begin(9600); se uso en la depuración
//Definimos las entradas analógicas como SALIDA digital para el multiplexado BJT (transistores)
pinMode(A0,OUTPUT); pinMode(A1,OUTPUT); pinMode(A2,OUTPUT); pinMode(A3,OUTPUT);
} // Fin de la función void setup ()
void loop() // Función para iterar en un loop infinito

{
for (conta=0; conta<=200; ++conta) // Saca el contenido de 4 localidades de memoria 200
// veces (opción: conta++)
{ // inicia ciclo for
for(pin=2; pin<=8; pin++) {digitalWrite(pin, LOW);} //Apaga los 7 segmentos
mem = cade[cont+cont1]; //Lee la ubicacion del caracter en la cadena y lo almacena en la
// variable mem
// Serial.println(mem); //delay(100); se uso en depuración
// Abajo, prepara el multiplexado para cada uno de los transistores BJT
if (cont==0) {digitalWrite(A0,HIGH);} if (cont==1) {digitalWrite(A1,HIGH);}
if (cont==2) {digitalWrite(A2,HIGH);} if (cont==3) {digitalWrite(A3,HIGH);}
//Asignamos una letra a cada “display”. Prende cada segmento necesario
switch(mem)
{
case 'H':
digitalWrite(3,HIGH); for (pin=6; pin<=6; pin++) digitalWrite(pin,HIGH);
digitalWrite(4,HIGH); break;
case 'O':
for (pin=2; pin<=7; pin++) digitalWrite(pin,HIGH); break;
37
case 'L':
case 'A':
for (pin=2; pin<=4; pin++) digitalWrite(pin,HIGH);
case 'E':
digitalWrite(2,HIGH); for (pin=5; pin<=8; pin++) digitalWrite(pin,HIGH); break;
case 'T':
for (pin=5; pin<=8; pin++) digitalWrite(pin,HIGH);digitalWrite(5,HIGH); break;
case 'C':
case 'S':
digitalWrite(2,HIGH); digitalWrite(4,HIGH); digitalWrite(5,HIGH);
digitalWrite(7,HIGH); digitalWrite(8,HIGH); break;
case 'D':
for (pin=3; pin<=6; pin++) digitalWrite(pin,HIGH); digitalWrite(8,HIGH); break;
case 'F':
case 'I':
} // cierra la estructua switch...case
delay(5); // Requiere este delay para que se vea bien la letra, sin parpadeo (estabilización)
analogWrite(A0,LOW); analogWrite(A1,LOW);analogWrite(A2,LOW); analogWrite(A3,LOW);
//Apaga multiplexado
cont=cont+1; if (cont > 3) cont=0;
} // Cierra el ciclo for
cont1=cont1 + 1; // Siguiente letra
cont=0; delay(5);
if (cont1 >35) {cont1=0; cont=0;}
}// cierra void loop. FIN DEL PROGRAMA. THE END............
38
/*
SEMAFO DE DOS VÍAS : Alumnos: MOY + DANY* + ANGEL (22-V-2014)
Depura profr. GAMO
*/
// give it a name: Se declara la variable led y led_rojo del tipo entero

int led = 13,
led_rojo = 11,
retardo = 1000; // I SEGUNDO = 1000 mS
// the setup routine runs once when you press reset:

void setup()
{
pinMode(led, OUTPUT);
pinMode(12, OUTPUT);
}
// the loop routine runs over and over again forever:

void loop()
{
digitalWrite(led, HIGH); // Led verde1 pin 13;
digitalWrite(15, HIGH); // pin 15 rojo2 prende
delay(3*retardo); // dura 3 segundos prendido el led verde
digitalWrite(led, LOW); // apaga led verde1 pin 13
digitalWrite(12, HIGH); // prende el led ambar1
delay(retardo); // dura 1 segundos
digitalWrite(12, LOW); // apaga led ambar1
digitalWrite(15, LOW); // apaga rojo2
digitalWrite(led_rojo, HIGH); // prende rojo1
digitalWrite(16, HIGH); // prende verde 2)
delay(3*retardo); digitalWrite(16, LOW); //Apaga verde 2
digitalWrite(17, HIGH); // prende abar 2
delay(retardo); digitalWrite(17, LOW); //Apaga ambar 2
digitalWrite(led_rojo, LOW); // Apaga rojo2
}
39
EJERCICIO.
ANALICE Y DETERMINE LO QUE SE OBTIENE DE SALIDA EN EL PROGRAMA
SIGUIENTE.
//"The only way to do great work is to love what you do.

//If you haven’t found it yet, keep looking. Don’t settle" - Steve Jobs
int cont=0, i, j=0, retardo = 50;
void setup()
{
for (cont=3; cont<10; cont++) pinMode(cont,OUTPUT); // pin 3 --> segmento a...
//pin 9 --> segmento g
cont=0;
Serial.begin(9600); // Para usar el monitor serial al DEPURAR EL PROGRAMA
}
// the loop routine runs over and over again forever:(se repite en bucle infinito)
void loop()
{
for (i=3; i<=9; i++)digitalWrite(i,LOW);
while (j<=10)
{
for (i=3; i<=8; i++)
{
digitalWrite(i,HIGH); delay(retardo);digitalWrite(i,LOW);
delay(retardo);
}
retardo=retardo-5; j++;
}
j=0; retardo=50;
switch(cont)
{
case 0:
digitalWrite(9,LOW); break;
case 1:
digitalWrite(3,LOW); digitalWrite(4,HIGH); digitalWrite(5,HIGH);
40
digitalWrite(6,LOW); digitalWrite(7,LOW); digitalWrite(8,LOW);
case 2:
digitalWrite(3,HIGH); digitalWrite(4,HIGH); digitalWrite(5,LOW);
digitalWrite(6,HIGH); digitalWrite(7,HIGH); digitalWrite(8,LOW);
case 3:
digitalWrite(6,HIGH); digitalWrite(7,LOW); digitalWrite(8,LOW);
case 4:
digitalWrite(3,LOW); digitalWrite(4,HIGH); digitalWrite(5,HIGH);
digitalWrite(6,LOW); digitalWrite(7,LOW); digitalWrite(8,HIGH);
case 5:
digitalWrite(3,HIGH); digitalWrite(4,LOW); digitalWrite(5,HIGH);
case 6:
case 7:
digitalWrite(6,LOW); digitalWrite(7,LOW); digitalWrite(8,LOW);
case 8:
case 9:
}
Serial.println (cont); cont++; // incrementa contador
if (cont >=10) cont=0; Serial.println("---"); j=1; delay(800); }
41
EN HOJAS LIMPIAS REALICE DETALLADA Y ORDENADAMENTE EL PROCEDIMIENTO DE
TODA OPERACIÓN, Y ESCRIBA EN ESTA HOJO LOS RESULTADOS.
UNIDAD I. SISTEMAS NUMÉRICOS Y CÓDIGOS

P1) ESCRIBA LA TABLA DEL 9 DEL SISTEMA DECIMAL (BASE DIEZ) .
DECIMAL A) BASE 6 B) BASE 16 DECIMAL A) BASE 6 B) BASE 16
9X1= 9  9x6=54 
9X2=18 9X7=63
9X3=27 9X8=72
9X4=36 9X9=81
9X5=45 9X10=90
P2) SISTEMA EN BASE 3. HAGA LA SUMA: 120 + 102+ 222+144+12 =
P3) a) SISTEMA BASE 16: RESTE POR COMPLEMENTO A 15; 1947 – 2014 =
b) CÓDIGO BCD 8421; 1521 + 2014 + 1985 =
P4) a) SISTEMA BINARIO: DIVIDA; 1001110001 / 101 HASTA 3 DECIMALES =

b) SISTEMA (TERNARIO) BASE 3: 12021 / 22 =
P5) SISTEMA DECIMAL: EL NÚMERO 21 CONVIÉRTALO A LOS CÓDIGOS.

A) BCD = B) EXCESO 3 = C) ASCCI =
D) PARIDAD PAR. = E) GRAY =
P6) ENCUNTRE LA BASE O RADIX QUE HACE VERDADERAS LAS OPERACIONES

A) 1234 + 5432 = 6666 BASE O RADIX =
B) 41 / 3 = 2 BASE O RADIX =
C) 33/3 = 11 BASE O RADIX =
D) 23 + 44 + 14 + 32 = 223 BASE O RADIX =
E) 302 / 20 = 12.1 BASE O RADIX =
½
F) (41) = 5 BASE O RADIX =
42
ELECTRÓNICA DIGITAL. UNIDAD II. (FUNCIONES Y COMPUERTAS LÓGICAS).
ALUMNO: FECHA:
RESUELVA ORDENADA Y DETALLADAMENTE LOS SIGUIENTES PROBLEMAS.
1) F = (A’B’ + AB)’ + AB. (EL APÓSTROFE INDICA NEGACIÓN O COMPLEMENTO)
2) P = [A’B’C + A’BC’ + A’BC+(A+B)’]’
3) X = π(1, 3, 5, 7) (MAXITÉRMINOS)
4) HAGA EL CIRCUITO LÓGICO DE LA SIGUIENTE FUNCIÓN Z EXCLUSIVAMENTE CON COMPUERTAS

EXOR (=XOR)
(O-EXCLUSIVA)
U1A
A 1 U3A
5 U4A
74LS04N 7 Z
2 74LS08N
B U2B 3 U3B 674LS32N
4
74LS04N 74LS08N
5) Q= ABCDE + (ABCE’ + A’BCE’)(A’+B’+C’+D’+E’)
UNIDAD III
1) Simplifique la función F = (B’ + C + D)(A +B +C’)(B +C´+ D) con

a)Con álgebra de Boole. B) Con K-Maps. C) Quine-McClusky.
2) Diseñe un sistema digital que detecte los números impares del 0 al 31.
3) Diseñe un sistema Digital que detecte los números primos. Entrada binaria de 4 bits.
4) Diseñe una ALU de un Bit con estrada de control C. Para C=0, S = A + B. Para C=1,
S = A – B (salida en complemento a dos). Para C=2, S = A XNOR B. Para C=3, S= A NAND
B con estructura de “PROM”
43
SOLUCIÓN: ELECTRÓNICA DIGITAL UNIDAD 3 (LÓGICA COMBINACIONAL)
MAPAS DE KARNAUGH DE 3 VARIABLES.
MINITÉRMINOS (mi) MAXITÉRMINOS Mi =( mi )’

B’ B B’ B
A’ 0 1 3 2 A’
7 6 4 5
4 5 7 6 3 2 0 1
A A
C’ C C’ C’ C C’
P1 a) Represente en un K-MAP la función: F = Σ (0,3,5,7)
A B’C’ B’C BC BC’

1 0 1 0 Minitérminos
0 1 1 0
b) Utilizando un multiplexor 4:1 y compuertas básicas (AND, OR, NOT)

implemente la función.
La salida del multiplexor es: S = I0 B’C’ + I1 B’C +I2 BC’ + I3 BC
La función es: F = A’B’C’ + A’BC + AB’C + ABC = A’B’C’+ AB’C + BC
Comparando se concluye que: I0 = A’, I1=A, I2=0, I3 =1
44
7404N
U1A
A 1 I0
I1 MUX 6 F
4:1
0 2
I2
1 3
I3
B 4
C 5
P2 a) Represente en un K-MAP la función G = ( A + B + C)’ + A (B + C)

Usando DeMorgan: G = A’B’ C’ + AB + AC
B
1 0 0 0
0 1 1 1
C
b) Implemente esta función exclusivamente con compuertas NAND.
G = A’B’C’ + AB + AC
TEOREMA DeMORGAN: G’ = (A’B’C’ + AB + AC)’ = (A’B’C’)’ (AB)’ ( AC)’
TEOREMA DeMORGAN: [G’ = (A’B’C’)’ (AB)’ ( AC)’]’;
G =[(A’B’C’)’ (AB)’ ( AC)’]’; COMPUERTA NAND S = (XYZ)’
ENTONCES: X= (A’B’C’)’ , Y=(AB)’, Z= ( AC)’.
X U2A
Y G
Z
7410N
U2A U3A U3A

A' A A
X Y Z
B' B C
DE IGUAL FORMA: C' 7410N 7400N 7400N
45
FINALMENTE el circuito es:
13 U6A U4A
A 10
8
7400N
11 7410N
U7A U2A
B 14 G
12
U5A 9
7400N 7410N
15 U8A
C 7
7400N
7400N U3A
7400N
16 U9A U10A
X
Z = X'
DONDE: 7400N EQUIVALE A 7404N INVERSOR.
P3 a) Represente en un K-MAP la función

H = (A + B + C)’ + (A’ + B’)’ + (A’+ C’)’
HAY VARIAS FORMAS. AQUÍ SE ELIGE METER LOS CEROS DE LA FUNCIÓN.
B’ B
0 0 0 0 0 0 0 0 0 0 0  1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 1
C’ C C’
(A + B + C)’ + (A’ + B’)’ + (A’+ C’)’ = A’B’C’ + AB + AC
b) Implemente esta función exclusivamente con compuertas NOR.

H = A’B’C’ + AB + AC
TEOREMA DeMORAN
[H = A’B’C’ + AB + AC]’ H’ = [A’B’C’ + AB + AC]’
H’ = (A’B’C’)’ (AB)’ ( AC)’ = (A+B+C)(A’+B’)(A’+C’)
TEOREMA DeMORAN [ H’ =(A+B+C)(A’+B’)(A’+C’)]’

H = (A+B+C)’ + (A’+B’)’ + (A’ +C’)’ . NOR: S =(X+Y+Z)’
46
EL DIAGRAMA LÓGICO CORRESPONDIENTE S.
21 U16A
A 24 U15A
25
7402N 20
22 U17A 7402N
B U14A U11A 17 U13A
19 H
26
7402N
23 U18A 7402N 7427N 7402N
C 18
U12A
7402N
7427N
27 U19A U20A
=
DONDE. 7402N 7404N
P4 a) Represente en un K-MAP la función J = Σ (0, 1, 2, 3; 4,6; 8, 9, 10, 11; 12, 14)

b) Simplifíquela en minitérminos. C) Simplifíquela en Maxitérminos.
C’ C
1 1 1 1 B’ 0 1 3 2
A’
1 0 0 1 B 4 5 7 6
1 0 0 1 12 13 15 14
A
1 1 1 1 B’ 8 9 11 10
D’ D D’
J = B’ + D’ ( minitérminos); J = (BD)’ (Maxitérminos, de los ceros)
P5 a) Represente en un K-MAP la función:

L = (A +B +C)(A’ + B’ + C)(A’ + B’ + C’)  L = π(0,6,7)
Expresada en minitérminos.  L = Σ (1,2,3,4,5)
47
0 1 1 1
1 1 0 0
b) Simplifíquela por el método (tabular) de Quine-Mc Clusky.

AGRUPANDO EN TABLA:
ABC A B C
G1 1 001 1,3 : 0 -- 1 0 1 2 3 4 5 6 7
2 010 1,5: -- 0 1 A’C * *

4 100 2,3: 0 1 -- B’C * *
A’B * *
G2 3 011 4,5: 1 0 --
AB’ * *
5 101
COMPARANDO, SE OBTIENE: L=A’C+B’C+A’B+AB’ (Tabla izquierda)

B’C es redundante (Tabla derecha). L=A’C + A’B + AB’
P6 Usando la arquitectura interna de una PROM (Bus de direcciones de 3

bits, salida en 8 líneas, matriz de diodos ) “prográmela” para que desplegué
en “display” de 7 segmentos la palabra “DANGER”
SOLUCIÓN EN LA PÁGINA SIGUIENTE.
48
A2
A0 A1
U21A
1
2
7404N
3
U1A
4
7404N 5
U2A D12 6
1N3208
7404N D1 D3
D2 D4 D5 D6 D10
1N3208 D8 D9 D11
1N3208 D13 D14 D15 D16
1N3208 1N3208
1N3208
1N3208D7 1N3208 D17
11 1N32081N3208 1N3208
1N3208
1N3208
1N3208
1N3208
D18
10 1N3208
8 1N3208 13 12 14
16
9 7
1N3208
d
a,f b c e g
Las direcciones 0 y 7 se decidió no usarlas.
a =[2,4,5], b = [1,2,4], c = [1,2,3,4], d = [1,4,5], e = [1,2,3,5,6]
f = [2,4,5], g = [1,2,3,4,5,6] a
1 2 3 4 5 6 (direcciones) f b g
e c
d
49
Wikitronics Digital electronics
http://electronics.wikia.com/wiki/Digital_electronics
Digital electronics are those electronics systems that use a digital signal instead
of an analog signal. Digital electronics are the most common representation of
Boolean algebra and are the basis of all digital circuits for computers, mobile
phones, and numerous other consumer products.
The most common fundamental unit of digital electronics is the logic gate. By
combining numerous logic gates (from tens to hundreds of thousands) more
complex systems can be created. The complex system of digital electronics is
collectively referred to as a digital circuit.
To most electronic engineers, the terms "digital circuit", "digital system" and "logic"
are interchangeable in the context of digital circuits.
Advantages
The usual advantages of digital circuits when compared to analog circuits are:
 Digital systems interface well with computers and are easy to control with
software. It is often possible to add new features to a digital system without
changing hardware, and to do this remotely, just by uploading new software.
Design errors or bugs can be worked-around with a software upgrade, after
the product is in customer hands.
 Information storage can be much easier in digital systems than in analog
ones. In particular, the great noise-immunity of digital systems makes it
possible to store data and retrieve it later without degradation. In an analog
system, aging and wear and tear will degrade the information in storage, but
in a digital system, as long as the wear and tear is below a certain level, the
information can be recovered perfectly.
Robustness
One of the primary advantages of digital electronics stems from it simply being
digital: robustness. The robustness stems from the fact that if the noise is less than
the noise margin then the system performs as if there were no noise at all. This is a
necessary and sufficient property for a circuit to be considered digital. However, if
the noise exceeds this level, the circuit can give unexpected and undesired results
— perhaps catastrophic incorrect results.
Digital signals can thus be regenerated to achieve lossless data transmission,

within certain limits. Analog signal transmission and processing, by contrast,
always introduces noise.
50
Theoretically, there is no data-loss when copying digital data. This is a great
advantage over analog systems, which faithfully reproduce every bit of noise that
makes its way into the signal.
Disadvantages
Digital circuits use more energy than analog circuits to accomplish the same
calculations and signal processing tasks, thus producing more heat as well. In
portable or battery-powered systems this can be a major limiting factor, but in a
situation where power is plentiful, a digital system is often preferred because of all
the advantages listed above, especially that of (re-)programmability and ease of
upgrading without requiring hardware changes.
A particular example is the cellular telephone, which being a battery-powered

portable device, uses a low-power analog front-end to acquire and tune in the radio
signal from the base station. The base station, being in a fixed location with access
to the power grid, can afford to use power-hungry software-defined (digital) radio
techniques that digitize the signal essentially at the antenna (after wideband
filtering and downconversion to intermediate frequency) and performs all
channelization and demodulation via software-driven calculations. Such base
stations can be reprogrammed, potentially via remote control, to process the
signals used in future cellular standards as those standards become available.
Digital circuits are sometimes more expensive, especially in small quantities.
The world in which we live is analog, and signals from this world such as light,
temperature, sound, electrical conductivity, electric and magnetic fields, and
phenomena such as the flow of time, are for most practical purposes continuous
and thus analog quantities rather than discrete digital ones. For a digital system to
do useful things in the real world, translation from the continuous realm to the
discrete digital realm must occur, resulting in quantization errors. This problem can
usually be mitigated by designing the system to store enough digital data to
represent the signal to the desired degree of fidelity. The Nyquist-Shannon
sampling theorem provides an important guideline as to how much digital data is
needed to accurately portray a given analog signal.
Fragility
Digital systems can be fragile, in that if a single piece of digital data is lost or
misinterpreted, the meaning of large blocks of related data can completely change.
This problem can be mitigated by designing the digital system for robustness. For
example, a parity bit or other error-detecting or error-correcting code can be
inserted into the signal path so that if less than a certain fraction of the data is
corrupted, the system can determine that this has occurred and possibly uncorrupt
the data, or ask for the corrupted data to be resent. In a state-machine, the state
transition logic can be designed to catch all unused states and trigger a reset
51
sequence or other error recovery routine. For example, it is standard practice in
embedded software design to fill unused program memory with interrupt
instructions that point to an error recovery routine, to help guard against a failure
that corrupts the microcontroller's instruction pointer which could otherwise cause
random code to be executed.
Analog issues Digital circuits are made from analog components, and care has to
be taken in design so that the analog nature of these underlying components don't
dominate over the desired digital behavior. In particular, attention must be paid to
all noise and timing margins, to parasitic inductances and capacitances, to proper
filtering of power and ground connections, to electromagnetic coupling amongst
datalines, and many other details. Inattention to these can cause intermittent
problems such as "glitches", vanishingly-fast pulses that may trigger some logic but
not others, "runt pulses" that do not reach valid switching (threshold) voltages, or
unexpected ("undecoded") combinations of logic states.
A corollary of the fact that digital circuits are made from analog components is the
fact that digital circuits are slower to perform calculations than analog circuits that
occupy a similar amount of physical space and consume the same amount of
power. However, the digital circuit will perform the calculation with much better
repeatability, due to the high noise immunity of digital circuitry.
Construction
A digital circuit is often constructed from small electronic circuits called logic gates.
Each logic gate represents a function of boolean logic. A logic gate is an
arrangement of electrically controlled switches. The output is an electrical flow or
voltage, that can, in turn, control more logic gates. Logic gates often use the fewest
number of transistors in order to reduce their size, power consumption and cost,
and increase their reliability. Manufactured as integrated circuits, they are the least
expensive implementation when made in large volumes. They are usually designed
by engineers using electronic design automation software (See below for more
information).
Another form of digital circuit is constructed from lookup tables, (many sold as
"programmable logic devices", though other kinds of PLDs exist). Lookup tables
can perform all the same functions as machines based on logic gates, but lookup
tables can be easily reprogrammed without changing the wiring. This means that a
designer can often repair errors without changing the arrangement of wires.
Therefore, in small volume products, programmable logic devices are often the
preferred solution. They are usually designed by engineers using electronic design
automation software (See below for more information).
52
When the volumes are medium to large, and the logic can be slow, or involves
complex algorithms or sequences, often a small microcontroller is programmed to
make an embedded system. These are usually programmed by software
engineers.
When only one digital circuit is needed, and its design is totally customized, as for
a factory production line controller, the conventional solution is a programmable
logic controller, or PLC. These are usually programmed by electricians, using
ladder logic.
Structure of digital systems
Engineers use many methods to minimize logic functions, in order to reduce the
complexity, and thus the number of errors and the expense of digital circuits. The
most widely used method is the application of a minimization algorithm within a
CAD system, although historically, truth tables, Karnaugh Maps, and Boolean
algebra have also been used.
Representations are crucial to an engineer's design of digital circuits. Some

analysis methods only work with particular representations.
The classical way to represent a digital circuit is with an equivalent set of logic
gates. Another way, often with the least electronics, is to construct an equivalent
system of electronic switches (usually transistors). One of the easiest ways is to
simply have a memory containing a truth table. The inputs are fed into the address
of the memory, and the data outputs of the memory become the outputs.
For automated analysis, these representations have digital file formats that can be
processed by computer programs. Most digital engineers are very careful to select
computer programs ("tools") with compatible file formats.
To choose representations, engineers consider types of digital systems. Most

digital systems divide into "combinatorial systems" and "sequential systems".
A combinatorial system always presents the same output when given the same
inputs. It is basically a representation of a set of logic functions, as already
discussed.
A sequential system is a combinatorial system with some of the outputs fed back
as inputs. This makes the digital machine perform a "sequence" of operations. The
simplest sequential system is probably a flip flop, a mechanism that represents a
binary digit or "bit".
53
Sequential systems are often designed as state machines. In this way, engineers
can design a system's gross behavior, and even test it in a simulation, without
considering all the details of the logic functions.
Sequential systems divide into two further subcategories. "Synchronous"

sequential systems change state all at once, when a "clock" signal changes state.
"Asynchronous" sequential systems propagate changes whenever inputs change.
Synchronous sequential systems are made of well-characterized asynchronous
circuits such as flip-flops, that change only when the clock changes, and which
have carefully designed timing margins.
The usual way to implement a synchronous sequential state machine is divide it

into a piece of combinatorial logic and a set of flip flops called a "state register."
Each time a clock signal ticks, the state register captures the feedback generated
from the previous state of the combinatorial logic, and feeds it back as an
unchanging input to the combinatorial part of the state machine. The fastest rate
of the clock is set by the most time-consuming logic calculation in the combinatorial
logic.
The state register is just a representation of a binary number. If the states in the
state machine are numbered (easy to arrange), the logic function is just some logic
that produces the number of the next state.
In comparison, asynchronous systems are very hard to design because all possible
states, in all possible timings must be considered. The usual method is to construct
a table of the minimum and maximum time that each such state can exist, and then
adjust the circuit to minimize the number of such states, and force the circuit to
periodically wait for all of its parts to enter a compatible state. (This is called "self-
resynchronization.") Without such careful design, it is easy to accidentally produce
asynchronous logic that is "unstable", that is, real electronics will have
unpredictable results because of the cumulative delays caused by small variations
in the values of the electronic components. Certain circuits (such as the
synchronizer flip-flops, switch debouncers, and the like which allow external
unsynchronized signals to enter synchronous logic circuits) are inherently
asynchronous in their design and must be analyzed as such.
As of now (2005), almost all digital machines are synchronous designs because it
is much easier to create and verify a synchronous design. However, asynchronous
logic is thought to be superior, if it can be made to work, because its speed is not
constrained by an arbitrary clock; instead, it simply runs at the maximum speed
permitted by the propagation rates of the logic gates from which it is constructed.
Building an asynchronous circuit using faster parts implicitly makes the circuit "go"
faster.
54
More generally, many digital systems are data flow machines. These are usually
designed using synchronous register transfer logic, using hardware description
languages such as VHDL or Verilog.
In register transfer logic, binary numbers are stored in groups of flip flops called
registers. The outputs of each register are a bundle of wires called a "bus" that
carries that number to other calculations. A calculation is simply a piece of
combinatorial logic. Each calculation also has an output bus, and these may be
connected to the inputs of several registers. Sometimes a register will have a
multiplexer on its input, so that it can store a number from any one of several
buses. Alternatively, the outputs of several items may be connected to a bus
through buffers that can turn off the output of all of the devices except one. A
sequential state machine controls when each register accepts new data from its
input.
In the 1980s, some researchers discovered that almost all synchronous register-
transfer machines could be converted to asynchronous designs by using first-in-
first-out synchronization logic. In this scheme, the digital machine is characterized
as a set of data flows. In each step of the flow, an asynchronous "synchronization
circuit" determines when the outputs of that step are valid, and presents a signal
that says, "grab the data" to the stages that use that stage's inputs. It turns out that
just a few relatively simple synchronization circuits are needed.
The most general-purpose register-transfer logic machine is a computer. This is

basically an automatic binary abacus. The control unit of a computer is usually
designed as a microprogram run by a microsequencer. A microprogram is much
like a player-piano roll. Each table entry or "word" of the microprogram commands
the state of every bit that controls the computer. The sequencer then counts, and
the count addresses the memory or combinatorial logic machine that contains the
microprogram. The bits from the microprogram control the arithmetic logic unit,
memory and other parts of the computer, including the microsequencer itself.
In this way, the complex task of designing the controls of a computer is reduced to
a simpler task of programming a relatively independent collection of much simpler
logic machines.
Computer architecture is a specialized engineering activity that tries to arrange the

registers, calculation logic, buses and other parts of the computer in the best way
for some purpose. Computer architects have applied large amounts of ingenuity to
computer design to reduce the cost and increase the speed and immunity to
programming errors of computers. An increasingly common goal is to reduce the
power used in a battery-powered computer system, such as a cell-phone. Many
computer architects serve an extended apprenticeship as microprogrammers.
"Specialized computers" are usually a conventional computer with a special-

purpose microprogram.
55
Automated design tools
To save costly engineering effort, much of the effort of designing large logic
machines has been automated. The computer programs are called "electronic
design automation tools" or just "EDA."
Simple truth table-style descriptions of logic are often optimized with EDA that
automatically produces reduced systems of logic gates or smaller lookup tables
that still produce the desired outputs.
Most practical algorithms for optimizing large logic systems use algebraic
manipulations or binary decision diagrams, and there are promising experiments
with genetic algorithms and annealing optimizations.
To automate costly engineering effort, some EDA can take state tables that
describe state machines and automatically produce a truth table for the
combinatorial part of a state machine. The state table is a piece of text that lists
each state, and the conditions that can exit that state.
It is common for the truth tables of such computer-generated state-machines to be

optimized with logic-minimization software. This is a simple example of how
complex logic machines are broken into simpler parts. Often, real logic systems are
designed as a series of sub-projects, which are combined using a "tool flow". The
tool flow is usually a "script", a simplified computer language that can invoke the
software design tools in the right order.
Tool flows for large logic systems such as microprocessors can be thousands of
commands long, and combine the work of hundreds of engineers.
Writing and debugging tool flows is an established engineering specialty in

companies that produce complex logic machines. The tool flow usually terminates
in a detailed computer file or set of files that describe how to physically construct
the logic machine. Often it consists of instructions to draw the transistors and wires
on an integrated circuit or a printed circuit board.
Parts of tool flows are "debugged" by testing the outputs of simulated logic
machines against expected inputs. The test tools take computer files with sets of
inputs and outputs, and highlight discrepancies between the simulated behavior
and the expected behavior.
These test data are usually called "test vectors." Often, the test vectors are
preserved and used in the factory to test that newly constructed logic machines
work correctly.
56
Design for testability
A large logic machine (say, with more than a hundred logical variables) can have
an astronomical number of possible states. Obviously, in the factory, testing every
state is impractical if testing each state takes a microsecond, and there are more
states than the number of microseconds since the universe began. Unfortunately,
this ridiculous-sounding case is typical.
Fortunately, large logic machines are almost always designed as assemblies of

smaller logic machines. To save time, the smaller sub-machines are isolated by
permanently-installed "design for test" circuitry, and are tested independently.
One common test scheme known as "scan design" moves test bits serially (one
after another) from external test equipment through one or more serial shift
registers known as "scan chains". Serial scans have only one or two wires to carry
the data, and minimize the physical size and expense of the infrequently-used test
logic.
After all the test data bits are in place, the design is reconfigured to be in "normal
mode" and one or more clock pulses are applied, to test for faults (e.g. stuck-at low
or stuck-at high) and capture the test result into flip-flops and/or latches in the scan
shift register(s). Finally, the result of the test is shifted out to the block boundary
and compared against the predicted "good machine" result.
In a board-test environment, serial to parallel testing has been formalized with a

standard called "JTAG" (named after the "Joint Testing Acting Group" that
proposed it).
Another common testing scheme provides a test mode that forces some part of the
logic machine to enter a "test cycle." The test cycle usually exercises large
independent parts of the machine.
Trade-offs (a balancing of factors: pros and cons)
Several numbers determine the practicality of a system of digital logic. Engineers

explored numerous electronic devices to get an ideal combination of speed, low
cost and reliability.
The cost of a logic gate is crucial. In the 1930s, the earliest digital logic systems
were constructed from telephone relays because these were inexpensive and
relatively reliable. After that, engineers always used the cheapest available
electronic switches that could still fulfill the requirements.
The earliest integrated circuits were a happy accident. They were constructed not
to save money, but to save weight, and permit the Apollo Guidance Computer to
control an inertial guidance system for a spacecraft. The first integrated circuit logic
57
gates cost nearly $50 (in 1960 dollars, when an engineer earned $10,000/year). To
everyone's surprise, by the time the circuits were mass-produced, they had
become the least-expensive method of constructing digital logic. Improvements in
this technology have driven all subsequent improvements in cost.
With the rise of integrated circuits, reducing the absolute number of chips used
represented another way to save costs. The goal of a designer is not just to make
the simplest circuit, but to keep the component count down. Sometimes this results
in slightly more complicated designs with respect to the underlying digital logic but
nevertheless reduces the number of components, board size, and even power
consumption.
For example, in some logic families, NAND gates are the simplest digital gate to
build. All other logical operations can be implemented by NAND gates. If a circuit
already required a single NAND gate, and a single chip normally carried four
NAND gates, then the remaining gates could be used to implement other logical
operations like logical and. This could eliminate the need for a separate chip
containing those different types of gates.
The "reliability" of a logic gate describes its mean time between failure (MTBF).
Digital machines often have millions of logic gates. Also, most digital machines are
"optimized" to reduce their cost. The result is that often, the failure of a single logic
gate will cause a digital machine to stop working.
Digital machines first became useful when the MTBF for a switch got above a few
hundred hours. Even so, many of these machines had complex, well-rehearsed
repair procedures, and would be nonfunctional for hours because a tube burned-
out, or a moth got stuck in a relay. Modern transistorized integrated circuit logic
gates have MTBFs of nearly a trillion (1x10^12) hours, and need them because
they have so many logic gates.
The "fan out" describes how many logic inputs can be controlled by a single logic
output. The minimum practical fan out is about five. Modern electronic logic using
CMOS transistors for switches have fanouts near fifty, and can sometimes go
much higher.
The "switching speed" describes how many times per second an inverter (an
electronic representation of a "logical not" function) can change from true to false
and back. Faster logic can accomplish more operations in less time. Digital logic
first became useful when switching speeds got above fifty hertz, because that was
faster than a team of humans operating mechanical calculators. Modern electronic
digital logic routinely switches at five gigahertz (5x109 hertz), and some laboratory
systems switch at more than a terahertz (1x1012 hertz).
58
Non-electronic logic
It is possible to construct non-electronic digital mechanisms. In principle, any

technology capable of representing discrete states and representing logic
operations could be used to build mechanical logic. Danny Hillis, co-author of The
Connection Machine, once built a working computer from Tinker Toys, string, a
brick, and a sharpened pencil, which is supposed to be in the Houston Museum of
Science.
Hydraulic, pneumatic and mechanical versions of logic gates exist and are used in
situations where electricity cannot be used. The first two types are considered
under the heading of fluidics. One application of fluidic logic is in military hardware
that is likely to be exposed to a nuclear electromagnetic pulse (nuclear EMP, or
NEMP) that would destroy any electrical circuits.
Mechanical logic is frequently used in inexpensive controllers, such as those in

washing machines. Famously, the first computer design, by Charles Babbage, was
designed to use mechanical logic. Mechanical logic might also be used in very
small computers that could be built by nanotechnology.
Another example is that if two particular enzymes are required to prevent the
construction of a particular protein, this is the equivalent of a biological "NAND"
gate. The term digital signal is used to refer to more than one concept. It can refer
to discrete-time signals that are digitized, or to the waveform signals in a digital
system.
Discrete-time signals
Template:Main Digital signals are digital representations of discrete-time signals,

which are often derived from analog signals.
An analog signal is a datum that changes over time—say, the temperature at a

given location; the depth of a certain point in a pond; or the amplitude of the
voltage at some node in a circuit—that can be represented as a mathematical
function, with time as the free variable (abscissa) and the signal itself as the
dependent variable (ordinate). A discrete-time signal is a sampled version of an
analog signal: the value of the datum is noted at fixed intervals (for example, every
microsecond) rather than continuously.
If individual time values of the discrete-time signal, instead of being measured

precisely (which would require an infinite number of digits), are approximated to a
certain precision—which, therefore, only requires a specific number of digits—then
the resultant data stream is termed a digital signal. The process of approximating
the precise value within a fixed number of digits, or bits, is called quantization.
59
In conceptual summary, a digital signal is a quantized discrete-time signal; a
discrete-time signal is a sampled analog signal.
In the Digital Revolution, the usage of digital signals has increased significantly.
Many modern media devices, especially the ones that connect with computers use
digital signals to represent signals that were traditionally represented as
continuous-time signals; cell phones, music and video players, personal video
recorders, and digital cameras are examples.
In most applications, digital signals are represented as binary numbers, so their

precision of quantization is measured in bits. Suppose, for example, that we wish
to measure a signal to two significant decimal digits. Since seven bits, or binary
digits, can record 128 discrete values (viz., from 0 to 127), those seven bits are
more than sufficient to express a range of one hundred values.
Waveforms in digital systems
Digital signal: 1) Low level, 2) High level, 3) Rising edge, and 4) Falling edge.
Template:Main
In computer architecture and other digital systems, a waveform that switches

between two voltage levels representing the two states of a Boolean value (0 and
1) is referred to as a digital signal, even though it is an analog voltage waveform,
since it is interpreted in terms of only two levels.
The clock signal is a special digital signal that is used to synchronize digital
circuits. The image shown can be considered the waveform of a clock signal. Logic
changes are triggered either by the rising edge or the falling edge.
60
Logic voltage levels
Hobbyist frequency counter circuit built almost entirely of TTL logic chips.
The two states of a wire are usually represented by some measurement of electric
current: Voltage is the most common, but current is used in some logic families. A
threshold is designed for each logic family. When below that threshold, the wire is
"low," when above "high." Digital circuits establish a "no man's area" or "exclusion
zone" that is wider than the tolerances of the components. The circuits avoid that
area, in order to avoid indeterminate results.
It is usual to allow some tolerance in the voltage levels used; for example, 0 to 2
volts might represent logic 0, and 3 to 5 volts logic 1. A voltage of 2 to 3 volts would
be invalid and would occur only in a fault condition or during a logic level transition,
as most circuits are not purely resistive, and therefore cannot instantly change
voltage levels. However, few logic circuits can detect such a fault, and most will
just choose to interpret the signal randomly as either a 0 or a 1.
The levels represent the binary integers or logic levels of 0 and 1. In active-high
logic, "low" represents binary 0 and "high" represents binary 1. Active-low logic
uses the reverse representation.
https://www.youtube.com/watch?v=c8A_v_hKC7U&list=PLiivzYNnIS6FIUtKiG5-
R3L8Sbx_jRv6B&index=2
61
http://www.ee.usyd.edu.au/tutorials/digital_tutorial/part3/TOC.htm
Sequential Circuits
Introduction
Combinational logic refers to circuits whose output is strictly depended on the

present value of the inputs. As soon as inputs are changed, the information about
the previous inputs is lost, that is, combinational logics circuits have no memory. In
many applications, information regarding input values at a certain instant of time is
required at some future time. Although every digital system is likely to have
combinational circuits, most systems encountered in practice also include memory
elements, which require that the system be described in terms of sequential logic.
Circuits whose outputs depends not only on the present input value but also the
past input value are known as sequential logic circuits. The mathematical model
of a sequential circuit is usually referred to as a sequential machine.
A general block diagram of a sequential circuit is shown below in Figure 1.
Figure 1. Block Diagram of Sequential Circuit.
The diagram consists of combinational circuit to which memory elements are

connected to form a feedback path. The memory elements are devices capable of
storing binary information within them. The combinational part of the circuit
receives two sets of input signals: one is primary (coming from the circuit
environment) and secondary (coming from memory elements). The particular
combination of secondary input variables at a given time is called the present
state of the circuit. The secondary input variables are also know as the state
variables.
62
The block diagram shows that the external outputs in a sequential circuit are a
function not only of external inputs but also of the present state of the memory
elements. The next state of the memory elements is also a function of external
inputs and the present state. Thus a sequential circuit is specified by a time
sequence of inputs, outputs, and internal states.
Quiz 1
These short quizzes are to refresh on what you have learnt so far.
1. A sequential circuit is a digital circuit whose logic True False

states depend on a specified time sequence.
2. Sequential circuits contain only combinational True False

logics.
3. Sequential circuits contain memory and True False

combinational circuits do not.
4. The outputs of a sequential circuit are computed True False

using both the present and past input values.
Synchronous and Asynchronous Operation
Sequential circuits are divided into two main types: synchronous and
asynchronous. Their classification depends on the timing of their signals.
Synchronous sequential circuits change their states and output values at discrete
instants of time, which are specified by the rising and falling edge of a free-running
clock signal. The clock signal is generally some form of square wave as shown in
Figure 2 below.
63
Figure 2. Clock Signal
From the diagram you can see that the clock period is the time between
successive transitions in the same direction, that is, between two rising or two
falling edges. State transitions in synchronous sequential circuits are made to take
place at times when the clock is making a transition from 0 to 1 (rising edge) or
from 1 to 0 (falling edge). Between successive clock pulses there is no change in
the information stored in memory.
The reciprocal of the clock period is referred to as the clock frequency. The clock
width is defined as the time during which the value of the clock signal is equal to 1.
The ratio of the clock width and clock period is referred to as the duty cycle. A
clock signal is said to be active high if the state changes occur at the clock's rising
edge or during the clock width. Otherwise, the clock is said to be active low.
Synchronous sequential circuits are also known as clocked sequential circuits.
The memory elements used in synchronous sequential circuits are usually flip-
flops. These circuits are binary cells capable of storing one bit of information. A flip-
flop circuit has two outputs, one for the normal value and one for the complement
value of the bit stored in it. Binary information can enter a flip-flop in a variety of
ways, a fact which give rise to the different types of flip-flops. For information on
the different types of basic flip-flop circuits and their logical properties, see the
previous tutorial on flip-flops.
In asynchronous sequential circuits, the transition from one state to another is

initiated by the change in the primary inputs; there is no external synchronisation.
The memory commonly used in asynchronous sequential circuits are time-delayed
devices, usually implemented by feedback among logic gates. Thus, asynchronous
sequential circuits may be regarded as combinational circuits with feedback.
Because of the feedback among logic gates, asynchronous sequential circuits
may, at times, become unstable due to transient conditions. The instability problem
imposes many difficulties on the designer. Hence, they are not as commonly used
as synchronous systems.
64
Summary of the Types of Flip-flop Behaviour
Since memory elements in sequential circuits are usually flip-flops, it is worth

summarising the behaviour of various flip-flop types before proceeding further.
All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in
the number of inputs and in the response invoked by different value of input
signals. The four types of flip-flops are defined in Table 1.
Table 1. Flip-flop Types
FLIP-
FLIP-FLOP CHARACTERISTIC CHARACTERISTIC EXCITATION
FLOP
SYMBOL TABLE EQUATION TABLE
NAME
S R Q(next) Q Q(next) S R
0 0 Q 0 0 0 X
Q(next) = S + R'Q
SR 0 1 0 0 1 1 0
SR = 0 1 0 0 1
1 0 1
1 1 ? 1 1 X 0
J K Q(next) Q Q(next) J K
0 0 Q 0 0 0 X
JK 0 1 0 Q(next) = JQ' + K'Q 0 1 1 X
1 0 1 1 0 X 1
1 1 Q' 1 1 X 0
Q Q(next) D
D Q(next) 0 0 0
D 0 0 Q(next) = D 0 1 1
1 1 1 0 0
1 1 1
Q Q(next) T
T Q(next) 0 0 0
T 0 Q Q(next) = TQ' + T'Q 0 1 1
1 Q' 1 0 1
1 1 0
65
pantunfla, sandalia. Flip plop.
http://www.thefreedictionary.com/flip-flop
Each of these flip-flops can be uniquely described by its graphical symbol, its
characteristic table, its characteristic equation or excitation table. All flip-flops have
output signals Q and Q'.
The characteristic table in the third column of Table 1 defines the state of each
flip-flop as a function of its inputs and previous state. Q refers to the present state
and Q(next) refers to the next state after the occurrence of the clock pulse. The
characteristic table for the RS flip-flop shows that the next state is equal to the
present state when both inputs S and R are equal to 0. When R=1, the next clock
pulse clears the flip-flop. When S=1, the flip-flop output Q is set to 1. The equation
mark (?) for the next state when S and R are both equal to 1 designates an
indeterminate next state.
The characteristic table for the JK flip-flop is the same as that of the RS when J
and K are replaced by S and R respectively, except for the indeterminate case.
When both J and K are equal to 1, the next state is equal to the complement of the
present state, that is, Q(next) = Q'.
The next state of the D flip-flop is completely dependent on the input D and
independent of the present state.
The next state for the T flip-flop is the same as the present state Q if T=0 and
complemented if T=1.
The characteristic table is useful during the analysis of sequential circuits when the
value of flip-flop inputs are known and we want to find the value of the flip-flop
output Q after the rising edge of the clock signal. As with any other truth table, we
can use the map method to derive the characteristic equation for each flip-flop,
which are shown in the third column of Table 1.
During the design process we usually know the transition from present state to the
next state and wish to find the flip-flop input conditions that will cause the required
transition. For this reason we will need a table that lists the required inputs for a
given change of state. Such a list is called the excitation table, which is shown in
66
the fourth column of Table 1. There are four possible transitions from present state
to the next state. The required input conditions are derived from the information
available in the characteristic table. The symbol X in the table represents a "don't
care" condition, that is, it does not matter whether the input is 1 or 0.
State Tables and State Diagrams

We have examined a general model for sequential circuits. In this model the effect
of all previous inputs on the outputs is represented by a state of the circuit. Thus,
the output of the circuit at any time depends upon its current state and the input.
These also determine the next state of the circuit. The relationship that exists
among the inputs, outputs, present states and next states can be specified by
either the state table or the state diagram.
State Table
The state table representation of a sequential circuit consists of three sections
labelled present state, next state and output. The present state designates the
state of flip-flops before the occurrence of a clock pulse. The next state shows the
states of flip-flops after the clock pulse, and the output section lists the value of the
output variables during the present state.
State Diagram
In addition to graphical symbols, tables or equations, flip-flops can also be
represented graphically by a state diagram. In this diagram, a state is represented
by a circle, and the transition between states is indicated by directed lines (or arcs)
connecting the circles. An example of a state diagram is shown in Figure 3 below.
67
Figure
3. State
Diagram
The binary number inside each circle identifies the state the circle represents. The
directed lines are labelled with two binary numbers separated by a slash (/). The
input value that causes the state transition is labelled first. The number after the
slash symbol / gives the value of the output. For example, the directed line from
state 00 to 01 is labelled 1/0, meaning that, if the sequential circuit is in a present
state and the input is 1, then the next state is 01 and the output is 0. If it is in a
present state 00 and the input is 0, it will remain in that state. A directed line
connecting a circle with itself indicates that no change of state occurs. The state
diagram provides exactly the same information as the state table and is obtained
directly from the state table.
Example: This example is taken from P. K. Lala, Practical Digital Logic Design and
Testing, Prentice Hall, 1996, p.155.
Consider a sequential circuit shown in Figure 4. It has one input x, one output Z
and two state variables Q1Q2 (thus having four possible present states 00, 01, 10,
11).
68
Figure 4.
A
Sequential
Circuit
The behaviour of the circuit is determined by the following Boolean expressions:
Z = x*Q1
D1 = x' + Q1
D2 = x*Q2' + x'*Q1'
These equations can be used to form the state table. Suppose the present state
(i.e. Q1Q2) = 00 and input x = 0. Under these conditions, we get Z = 0, D1 = 1, and
D2 = 1. Thus the next state of the circuit D1D2 = 11, and this will be the present
state after the clock pulse has been applied. The output of the circuit
corresponding to the present state Q1Q2 = 00 and x = 1 is Z = 0. This data is
entered into the state table as shown in Table 2.
Present
Next State Output
State
x=0 x=1 x=0 x=1
Q1Q2
00 11 01 0 0
01 11 00 0 0
10 10 11 0 1
11 10 10 0 1
Table 2. State table for the sequential circuit in Figure 4.
The state diagram for the sequential circuit in Figure 4 is shown in Figure 5.
69
Figure
5. State
Diagram
of
circuit
in
Figure
4.
State Diagrams of Various Flip-flops

Table 3 shows the state diagrams of the four types of flip-flops.
NAME STATE DIAGRAM
SR
JK
70
D
Table 3. State diagrams of the four types of flip-flops.
You can see from the table that all four flip-flops have the same number of states
and transitions. Each flip-flop is in the set state when Q=1 and in the reset state
when Q=0. Also, each flip-flop can move from one state to another, or it can re-
enter the same state. The only difference between the four types lies in the values
of input signals that cause these transitions.
A state diagram is a very convenient way to visualise the operation of a flip-flop or

even of large sequential components.
Analysis of Sequential Circuits

The behaviour of a sequential circuit is determined from the inputs, the outputs and
the states of its flip-flops. Both the output and the next state are a function of the
inputs and the present state.
The suggested analysis procedure of a sequential circuit is set out in Figure 6

below.
71
We start with the
logic schematic from
which we can derive
excitation equations
for each flip-flop
input. Then, to
obtain next-state
equations, we insert
the excitation
equations into the
characteristic
equations. The
output equations can
be derived from the
schematic, and once
we have our output
and next-state
equations, we can
generate the next-
state and output
tables as well as
state diagrams.
When we reach this
stage, we use either
the table or the state
diagram to develop a
timing diagram
which can be verified
through simulation.
Figure 6. Analysis
procedure of
sequential circuits.
72
Now let's look at some examples, using these procedures to analyse a sequential
circuit.
This example is taken from D. D. Gajski, Principles of Digital Design, Prentice Hall, 1997,
p.230.
Example 1.1. Modulo-4 counter
Derive the state table and state diagram for the sequential circuit shown in Figure
7.
Figure 7.
Logic
schematic
of a
sequential
circuit.
SOLUTION:
STEP 1: First we derive the Boolean expressions for the inputs of each flip-flops
in the schematic, in terms of external input Cnt and the flip-flop outputs Q1 and Q0.
Since there are two D flip-flops in this example, we derive two expressions for D1
and D0:
D0 = Cnt Q0 = Cnt'*Q0 + Cnt*Q0'

D1 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'
These Boolean expressions are called excitation equations since they represent
the inputs to the flip-flops of the sequential circuit in the next clock cycle.
STEP 2: Derive the next-state equations by converting these excitation

equations into flip-flop characteristic equations. In the case of D flip-flops, Q(next) =
D. Therefore the next state equal the excitation equations.
Q0(next) = D0 = Cnt'*Q0 + Cnt*Q0'
73
Q1(next) = D1 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'
STEP 3: Now convert these next-state equations into tabular form called the
next-state table.
Present State Next State

Q1Q0 Cnt = 0 Cnt = 1
00 00 01
01 01 10
10 10 11
11 11 00
Each row is corresponding to a state of the sequential circuit and each column
represents one set of input values. Since we have two flip-flops, the number of
possible states is four - that is, Q1Q0 can be equal to 00, 01, 10, or 11. These are
present states as shown in the table.
For the next state part of the table, each entry defines the value of the sequential
circuit in the next clock cycle after the rising edge of the Clk. Since this value
depends on the present state and the value of the input signals, the next state
table will contain one column for each assignment of binary values to the input
signals. In this example, since there is only one input signal, Cnt, the next-state
table shown has only two columns, corresponding to Cnt = 0 and Cnt = 1.
Note that each entry in the next-state table indicates the values of the flip-flops in
the next state if their value in the present state is in the row header and the input
values in the column header.
Each of these next-state values has been computed from the next-state equations
in STEP 2.
STEP 4: The state diagram is generated directly from the next-state table,
shown in Figure 8.
74
Figure
8. State
diagram
Each arc is labelled with the values of the input signals that cause the transition
from the present state (the source of the arc) to the next state (the destination of
the arc).
In general, the number of states in a next-state table or a state diagram will equal
2m , where m is the number of flip-flops. Similarly, the number of arcs will equal 2m
x 2k , where k is the number of binary input signals. Therefore, in the state diagram,
there must be four states and eight transitions. Following these transition arcs, we
can see that as long as Cnt = 1, the sequential circuit goes through the states in
the following sequence: 0, 1, 2, 3, 0, 1, 2, .... On the other hand, when Cnt = 0, the
circuit stays in its present state until Cnt changes to 1, at which the counting
continues.
Since this sequence is characteristic of modulo-4 counting, we can conclude that

the sequential circuit in Figure 7 is a modulo-4 counter with one control signal, Cnt,
which enables counting when Cnt = 1 and disables it when Cnt = 0.
To see how the states changes corresponding to the input signals Cnt, click on this
image.
Below, we show a timing diagram, representing four clock cycles, which enables us
to observe the behaviour of the counter in greater detail.
75
Figure
9.
Timing
Diagram
In this timing diagram we have assumed that Cnt is asserted in clock cycle 0 at t 0
and is disasserted in clock cycle 3 at time t4. We have also assumed that the
counter is in state Q1Q0 = 00 in the clock cycle 0. Note that on the clock's rising
edge, at t1, the counter will go to state Q1Q0 = 01 with a slight propagation delay;
in cycle 2, after t2, to Q1Q0 = 10; and in cycle 3, after t3 to Q1Q0 = 11. Since Cnt
becomes 0 at t4, we know that the counter will stay in state Q1Q0 = 11 in the next
clock cycle. To see the timing behaviour of the circuit click on this image
.
In Example 1.1 we demonstrated the analysis of a sequential circuit that has no

outputs by developing a next-state table and state diagram which describes only
the states and the transitions from one state to the next. In the next example we
complicate our analysis by adding output signals, which means that we have to
upgrade the next-state table and the state diagram to identify the value of output
signals in each state.
This example is taken from D. D. Gajski, Principles of Digital Design, Prentice Hall, 1997,
p.234.
76
Example 1.2
Derive the next state, the output table and the state diagram for the sequential
circuit shown in Figure 10.
Figure
10. Logic
schematic
of a
sequential
circuit.
SOLUTION:
The input combinational logic in Figure 10 is the same as in Example 1.1, so the
excitation and the next-state equations will be the same as in Example 1.1.
Excitation equations:
D0 = Cnt Q0 = Cnt'*Q0 + Cnt*Q0'

D0 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'
Next-state equations:
Q0(next) = D0 = Cnt'*Q0 + Cnt*Q0'

Q1(next) = D0 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'
In addition, however, we have computed the output equation.
Output equation: Y = Q1Q0
As this equation shows, the output Y will equal to 1 when the counter is in state
Q1Q0 = 11, and it will stay 1 as long as the counter stays in that state.
77
Next-state and output table:
Next State
Present State Output
Cnt=0 Cnt=1
Q1 Q0 Z
00 00 01 0
01 01 10 0
10 10 11 0
11 11 00 1
State diagram:
Figure
11. State
diagram
of
sequential
circuit in
Figure
10.
To see
how the
states
move
from one
to another
click on
the
image.
78
Timing diagram:
Figure 12.
Timing
diagram of
sequential
circuit in
Figure 10.
Click on
the image
to see its
timing
behaviour.
Note that the counter will reach the state Q1Q0 = 11 only in the third clock cycle,
so the output Y will equal 1 after Q0 changes to 1. Since counting is disabled in the
third clock cycle, the counter will stay in the state Q1Q0 = 11 and Y will stay
asserted in all succeeding clock cycles until counting is enabled again.
Design of Sequential Circuits

The design of a synchronous sequential circuit starts from a set of specifications
and culminates in a logic diagram or a list of Boolean functions from which a logic
diagram can be obtained. In contrast to a combinational logic, which is fully
specified by a truth table, a sequential circuit requires a state table for its
specification. The first step in the design of sequential circuits is to obtain a state
table or an equivalence representation, such as a state diagram.
A synchronous sequential circuit is made up of flip-flops and combinational gates.

The design of the circuit consists of choosing the flip-flops and then finding the
combinational structure which, together with the flip-flops, produces a circuit that
fulfils the required specifications. The number of flip-flops is determined from the
number of states needed in the circuit.
The recommended steps for the design of sequential circuits are set out below.
79
For information on state reduction.

This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.235.
80
Example 1.3 We wish to design a synchronous sequential circuit whose state
diagram is shown in Figure 13. The type of flip-flop to be use is J-K.
Figure
13.
State
diagram
From the state diagram, we can generate the state table shown in Table 9. Note
that there is no output section for this circuit. Two flip-flops are needed to represent
the four states and are designated Q0Q1. The input variable is labelled x.
Next State
Present State
x=0 x=1
Q0 Q1
00 00 01
01 10 01
10 10 11
11 11 00
Table 9. State table.
We shall now derive the excitation table and the combinational structure. The table
is now arranged in a different form shown in Table 11, where the present state and
input variables are arranged in the form of a truth table. Remember, the excitable
for the JK flip-flop was derive in Table 1.
81
Table 10. Excitation table for JK flip-flop
Output Transitions Flip-flop inputs
Q Q(next) JK
0  0 0 X
0  1 1 X
1  0 X 1
1  1 X 0
Table 11. Excitation table of the circuit
Flip-flop Inputs
Present State Next State Input
J0K0 J1K1
Q0 Q1 Q0 Q1 X
00 00 0 0X 0X
00 01 1 0X 1X
01 10 0 1X X1
01 01 1 0X X0
10 10 0 X0 0X
10 11 1 X0 1X
11 11 0 X0 X0
11 00 1 X1 X1
In the first row of Table 11, we have a transition for flip-flop Q0 from 0 in the
present state to 0 in the next state. In Table 10 we find that a transition of states
from 0 to 0 requires that input J = 0 and input K = X. So 0 and X are copied in the
first row under J0 and K0 respectively. Since the first row also shows a transition
82
for the flip-flop Q1 from 0 in the present state to 0 in the next state, 0 and X are
copied in the first row under J1 and K1. This process is continued for each row of
the table and for each flip-flop, with the input conditions as specified in Table 10.
The simplified Boolean functions for the combinational circuit can now be derived.
The input variables are Q0, Q1, and x; the output are the variables J0, K0, J1 and
K1. The information from the truth table is plotted on the Karnaugh maps shown in
Figure 14.
Figure 14. Karnaugh Maps
The flip-flop input functions are derived:
J0 = Q1*x' K0 = Q1*x
J1 = x K1 = Q0'*x' + Q0*x = Q0x
Note: the symbol  is exclusive-NOR.
The logic diagram is drawn in Figure 15.
Figure
15. Logic
diagram
of the
sequential
circuit.
83
This example is taken from P. K. Lala, Practical Digital Logic Design and Testing,
Prentice Hall, 1996, p.176.
Example 1.4 Design a sequential circuit whose state tables are specified in
Table 12, using D flip-flops.
Table 12. State table of a sequential circuit.
Present State Next State Output

Q0 Q1 x=0 x=1 x=0 x=1
00 00 01 0 0
01 00 10 0 0
10 11 10 0 0
11 00 01 0 1
Table 13. Excitation table for a D flip-flop.
Output Transitions Flip-flop inputs

QQ(next) D
0
0  0
0  1 1
1  0 0
1  1
1
Next step is to derive the excitation table for the design circuit, which is shown in
Table 14. The output of the circuit is labelled Z.
Flip-flop
Present State Next State Input Output
Inputs
Q0 Q1 Q0 Q1 x Z
D0 D1
00 00 0 0 0 0
00 01 1 0 1 0
01 00 0 0 0 0
01 10 1 1 0 0
10 11 0 1 1 0
84
10 10 1 1 0 0
11 00 0 0 0 0
11 01 1 0 1 1
Table 14. Excitation table
Now plot the flip-flop inputs and output functions on the Karnaugh map to derive
the Boolean expressions, which is shown in Figure 16.
Figure 16. Karnaugh maps
The simplified Boolean expressions are:
D0 = Q0*Q1' + Q0'*Q1*x
D1 = Q0'*Q1'*x + Q0*Q1*x + Q0*Q1'*x'
Z = Q0*Q1*x
Finally, draw the logic diagram.
85
Figure 17. Logic diagram of the sequential circuit.
Design of Counters
A sequential circuit that goes through a prescribed sequence of states upon the
application of input pulses is called a counter. The input pulses, called count
pulses, may be clock pulses. In a counter, the sequence of states may follow a
binary count or any other sequence of states. Counters are found in almost all
equipment containing digital logic. They are used for counting the number of
occurrences of an even and are useful for generating timing sequences to control
operations in a digital system.
Of the various sequences a counter may follow, the straight binary sequence is the
simplest and most straight forward. A counter that follows the binary sequence is
called a binary counter. An n-bit binary counter consists of n flip-flops and can
count in binary from 0 to 2n - 1.
Let's look at some examples of counter designs.
Design of Counters
This example is taken from T. L. Floyd, Digital Fundamentals, Fourth Edition, Macmillan
Publishing, 1990, p.395.
Example 1.5 A counter is first described by a state diagram, which is shows the
sequence of states through which the counter advances when it is clocked. Figure
18 shows a state diagram of a 3-bit binary counter.
Figure 18.
State
diagram of
a 3-bit
binary
counter.
86
The circuit has no inputs other than the clock pulse and no outputs other than its
internal state (outputs are taken off each flip-flop in the counter). The next state of
the counter depends entirely on its present state, and the state transition occurs
every time the clock pulse occurs. Figure 19 shows the sequences of count after
each clock pulse.
Once the sequential circuit is defined by the state diagram, the next step is to
obtain the next-state table, which is derived from the state diagram in Figure 18
and is shown in Table 15.
Table 15. State table

Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
87
Since there are eight states, the number of flip-flops required would be three. Now
we want to implement the counter design using JK flip-flops.
Next step is to develop an excitation table from the state table, which is shown in
Table 16.
Table 16. Excitation table
Output State Transitions Flip-flop inputs

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0X 0X 1X
0 0 1 0 1 0 0X 1X X1
0 1 0 0 1 1 0X X0 1X
0 1 1 1 0 0 1X X1 X1
1 0 0 1 0 1 X0 0X 1X
1 0 1 1 1 0 X0 1X X1
1 1 0 1 1 1 X0 X0 1X
1 1 1 0 0 0 X1 X1 X1
Now transfer the JK states of the flip-flop inputs from the excitation table to
Karnaugh maps to derive a simplified Boolean expression for each flip-flop input.
This is shown in Figure 20.
88
Figure
20.
Karnaugh
maps
The 1s in the Karnaugh maps of Figure 20 are grouped with "don't cares" and the
following expressions for the J and K inputs of each flip-flop are obtained:
J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q1*Q0
The final step is to implement the combinational logic from the equations and
connect the flip-flops to form the sequential circuit. The complete logic of a 3-bit
binary counter is shown in Figure 21.
Figure
21.
Logic
diagram
of a 3-
bit
binary
counter
89
Design of Counters
This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.243.
Example 1.6 Design a counter specified by the state diagram in Example 1.5
using T flip-flops. The state diagram is shown here again in Figure 22.
Figure 22.
State
diagram of
a 3-bit
binary
counter.
The state table will be the same as in Example 1.5.
Now derive the excitation table from the state table, which is shown in Table 17.
Table 17. Excitation table.
Output State Transitions Flip-flop inputs

T2 T1 T0
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
90
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
Next step is to transfer the flip-flop input functions to Karnaugh maps to derive a
simplified Boolean expressions, which is shown in Figure 23.
Figure
23.
Karnaugh
maps
The following expressions are obtained:
T0 = 1; T1 = Q0; T2 = Q1*Q0
Finally, draw the logic diagram of the circuit from the expressions obtained. The
complete logic diagram of the counter is shown in Figure 24.
Figure 24.
Logic
diagram of
3-bit
binary
counter.
To see the timing and state transitions of the counter, click on this image.
91
Now that you have reached the end of the tutorial, you should be able to
understand the basic concept of sequential circuits. You should be able to analyse
and design a basic sequential circuit. Now you can practice some of the exercises
using the analysis and design procedures shown in the examples.
Exercises
You can try some of these exercises which covers the analysis and design of
sequential circuits.
Analysis of Sequential Circuits.

1. Derive a) excitation equations, b) next state equations, c) a state/output table,
and d) a state diagram for the circuit shown in Figure 1.1. Draw the timing diagram
of the circuit.
Figure
1.1

and d) a state diagram for the circuit shown in Figure 1.2.
Figure
1.2

and d) a state diagram for the circuit shown in Figure 1.3.
92
Figure
1.3
4. Derive the state output and state diagran for the sequential circuit shown in
Figure 1.4.
Figure
1.4
5. A sequential circuit uses two D flip-flops as memory elements. The behaviour

of the circuit is described by the following equations:
D1 = Q1 + x'*Q2
D2 = x*Q1' + x'*Q2
Z = x'*Q1*Q2 + x*Q1'*Q2'
Derive the state table and draw the state diagram of the circuit.
Design of Sequential Circuits.

6. Design a sequential circuit specified by Table 6.1, using JK flip-flops.
Table 6.1
Present State Next State Output

Q0 Q1 x=0 x=1 x=0 x=1
00 00 01 0 0
01 00 10 0 0
93
10 11 10 0 0
11 00 01 0 1
7. Design the sequential circuit in question 6, using T flip-flops.
8. Design a mod-5 counter which has the following binary sequence: 0, 1, 2, 3, 4.

Use JK flip-flops.
9. Design a counter that has the following repeated binary sequence: 0, 1, 2, 3,

4, 5, 6, 7. Use RS flip-flops.
10. Design a counter with the following binary sequence: 1, 2, 5, 7 and repeat.
Use JK flip-flops.
11. Design a counter with the following repeated binary sequence: 0, 4, 2, 1, 6.

Use T flip-flops.
12. Design a counter that counts in the sequence 0, 1, 3, 6, 10, 15, using four a)
D, b) SR, c) JK and d) T flip-flops.
DICTIONARY
http://www.thefreedictionary.com/flip-flop
flip-flop (fl p fl p ) n.
1. The movement or sound of repeated flapping.
2. Informal A reversal, as of a stand or position: a foreign policy flip-flop.
3. A backless, often foam rubber sandal held to the foot at the big toe by means of a thong.
4. A backward somersault or handspring.
5. Electronics An electronic circuit or mechanical device capable of assuming either of two stable
states, especially a computer circuit used to store a single bit of information.
v. flip-flopped, flip-flop·ping, flip-flops
v.intr.
1. To move back and forth between two conditions or circumstances, sometimes repeatedly: "The
weather has flip-flopped between sweltering heat and violent storms" (New York Times).
2. To reverse a stand or position: "With the board having flip-flopped over zoning issues in the last
several years, residents are looking to this fall's election for clarity" (Eugene L. Meyer).
3. To execute a backward somersault or handspring.
v.tr.
To move from one position to the reverse or opposite: The coach flip-flopped the linemen.
94
flip -flop per n.
The American Heritage® Dictionary of the English Language, Fourth Edition copyright
©2000 by Houghton Mifflin Company. Updated in 2009. Published by Houghton Mifflin
Company. All rights reserved.
flip-flop n
1. (Gymnastics) a backward handspring
2. (Electronics) Also called: bistable an electronic device or circuit that can assume either of two
stable states by the application of a suitable pulse
3. US a complete change of opinion, policy, etc
4. a repeated flapping or banging noise
5. (Clothing & Fashion) a rubber-soled sandal attached to the foot by a thong between the big toe
and the next toeAlso called (US, Canadian, Austral, and NZ): thong
vb (intr) , -flops, -flopping or -flopped
6. US to make a complete change of opinion, policy, etc
7. to move with repeated flaps
adv
8. with repeated flappings: to go flip-flop.
[C16: reduplication of flip]
Collins English Dictionary – Complete and Unabridged © HarperCollins Publishers 1991,

1994, 1998, 2000, 2003
flip′-flop`
n., v. -flopped, -flop•ping. n.
1. a sudden or unexpected reversal, as of opinion or policy.
2. a backward somersault.
95
3. Also called flip′-flop` cir`cuit. an electronic circuit having two stable conditions, each one
corresponding to one of two alternative input signals.
4. the sound or motion of something flapping.
5. a flat backless shoe or slipper, esp. one of rubber with a thong between the first two toes.
v.i.
6. to perform a flip-flop.
Also, flip′-flap` (for defs. 2, 5, 9, 12), flip′flop` (for def. 6, 7).
[1655–65]
Random House Kernerman Webster's College Dictionary, © 2010 K Dictionaries Ltd. Copyright
2005, 1997, 1991 by Random House, Inc. All rights reserved.
flip-flop
Past participle: flip-flopped
Gerund: flip-flopping
Imperative
flip-flop
Collins English Verb Tables © HarperCollins Publishers 2011

Thesaurus Legend: Synonyms Related Words Antonyms
Noun 1. flip-flop - a decision to reverse an earlier decision
change of mind, turnabout, turnaround, reversal
deciding, decision making - the cognitive process of reaching a decision; "a good
executive must be good at decision making"
afterthought, rethink, second thought, reconsideration - thinking again about a choice

previously made; "he had second thoughts about his purchase"
2. flip-flop - a backless sandal held to the foot by a thong between the

big toe and the second toe
thong
sandal - a shoe consisting of a sole fastened by straps to the foot
96
3. flip-flop - an electronic circuit that can assume either of two stable states
circuit, electric circuit, electrical circuit - an electrical device that provides a path for
electrical current to flow
4. flip-flop - a backward somersault
flip, somersault, somersaulting, summersault, summerset,

somerset - an acrobatic feat in which the feet roll over the head
(either forward or backward) and return
Verb 1. flip-flop - reverse (a direction, attitude, or course of action)
alternate, interchange, tack, switch, flip
change by reversal, reverse, turn - change to the contrary; "The trend was reversed"; "the
tides turned against him"; "public opinion turned when it was revealed that the president
had an affair with a White House intern"
KKKKKKKKKKKKKKKKKKKK
Arduino Board - Kit, placa, protección y más - DigiKey.com.mx
Placas Base Arduino - Precios Increíbles y Mejor calidad
www.miniinthebox.com/Placas_Arduino
http://www.taringa.net/comunidades/arduinga/4518720/Principales-comandos-C-C-de-
Arduino.html
The Arduino language is based on C/C++.
http://www.arduino.cc/en/Reference/HomePage
9. Language Reference https://www.arduino.cc/reference/en/
Arduino programs can be divided in three main parts: structure, values (variables and constants),
and functions.
Principales comandos
(C/C++) de Arduino
Functions
97
Variables Digital I/O
Structure
Constants  pinMode()
 setup()  digitalWrite()
 loop()  HIGH | LOW  digitalRead()
 INPUT | OUTPUT |
Control Structures INPUT_PULLUP Analog I/O
 LED_BUILTIN
 true | false 
 if analogReference()
 integer constants 
 if…else analogRead()
 floating point 
 for analogWrite() - PWM
constants
 switch case
 while Due & Zero only
 do… while Data Types
 break  analogReadResolution()
 continue  void  analogWriteResolution()
 return  boolean
  char
goto Advanced I/O
 unsigned char
Further Syntax  byte
 tone()
 int
 noTone()
 unsigned int
 ; (semicolon)  shiftOut()
 word
 {} (curly braces)  shiftIn()
 long
 // (single line  pulseIn()
 unsigned long
comment)
 short
 /* */ (multi-line Time
 float
comment)
 double
 #define  millis()
 string - char array
 #include  micros()
 String - object
 array  delay()
Arithmetic Operators  delayMicroseconds()
Conversion
 = (assignment Math
operator)
 char()
 + (addition)  min()
 byte()
 - (subtraction)  max()
 int()
 * (multiplication)  abs()
 word()
 / (98ivisión)  constrain()
 long()
 % (modulo)  map()
 float()
 pow()
 sqrt()
Comparison Operators
Variable Scope & Trigonometry
Qualifiers
 == (equal to)
 sin()
 ¡= (not equal to)
98
 < (less 99iv)  cos()
 > (greater 99iv)  variable scope  tan()
 <= (less than or  static
equal to)  volatile Random Numbers
 >= (greater than or  const
equal to)  randomSeed()
Utilities  random()
Boolean Operators
 sizeof() Bits and Bytes
 && (and)  PROGMEM
 || (or)  lowByte()
 ¡ (not)  highByte()
 bitRead()
Pointer Access Operators  bitWrite()
 bitSet()
 * dereference  bitClear()
operator  bit()
 & reference operator
External Interrupts
Bitwise Operators
 attachInterrupt()
 & (bitwise and)  detachInterrupt()
 | (bitwise or)
 ^ (bitwise xor) Interrupts
 ~ (bitwise not)
 << (bitshift left)  interrupts()
 >> (bitshift right)  noInterrupts()
Communication
 Serial
 Stream
Compound Operators
USB (32u4 based boards and

 ++ (increment)
 -- (decrement) Due/Zero only)
 += (compound
addition)  Keyboard
 -= (compound  Mouse
subtraction)
 *= (compound
multiplication)
 /= (compound
99ivisión)
 &= (compound
99
bitwise and)
 |= (compound
bitwise or)
while:
Se ejecuta continuamente hasta que la expresión dentro del paréntesis pasa a ser falsa.
while(operación booleana){
acción
break:
Es usado para salir de los bucles do, for, o while, pasando por alto la condición normal del bucle. Es
usado también para salir de una estructura de control switch.
digitalWrite:
Escribe un valor HIGH (5V o 3.3V) o LOW (0V, tierra) hacia un pin digital.
digitalWrite(PIN, HIGH/LOW)
digitalRead:
Lee el valor de un pin digital especificado (HIGH o LOW).
digitalRead(PIN)
analogRead:
Lee el valor de tensión en el pin analógico especificado. La placa Arduino posee 6 canales (8
canalaes en el Mini y Nano y 16 en el Mega) conectados a un conversor analógico digital de 10
bits. Esto significa que convertirá tensiones entre 0 y 5 voltios a un número entero entre 0 y 1023.
100
Esto proporciona una resolución en la lectura de: 5 voltios / 1024 unidades, es decir, 0.0049 voltios
(4.9 mV) por unidad.
El conversor tarda aproximadamente 100 microsegundos (0.0001 segundos) en leer una entrada
analógica por lo que se puede llevar una tasa de lectura máxima aproximada de 10.000 lecturas
por segundo.
analogRead(PIN)
analogReference:
Configura el voltaje de referencia usado por la entrada analógica. La función analogRead()

devolverá un valor de 1023 para aquella tensión de entrada que sea igual a la tensión de
referencia. Las opciones son:
DEFAULT: Es el valor de referencia analógico que viene por defecto que de 5 voltios en placas
Arduino de y de 3.3 voltios en placas Arduino que funcionen con 3.3 voltios.
INTERNAL: Es una referencia de tensión interna de 1.1 voltios en el ATmega168 o ATmega328 y de
2.56 voltios en el ATmega8.
EXTERNAL: Se usará una tensión de referencia externa que tendrá que ser conectada al pin AREF.
101

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U1A

CIRCUITO FÍSCO (EN PROTOBOARD) CIRCUITO LÓGICO (SÍMBOLOS)

OBSERVE LA IMAGEN. 4 LEDs Rojos (entrada), 4 LEDs Azules (Salida)

4 LED´S ROJOS PARA INDICAR LAS ENTRADAS ACTIVADAS (HIGH,

REVISIÓN 2017- II PROF. G. ACOSTA M.

Prof. Guillermo Acosta Montiel.

1.1 Fundamentos de los sistemas digitales

UNIDAD 2 FUNCIONES Y COMPUERTAS LÓGICAS

UNIDAD III LÓGICA COMBINACIONAL

La información binaria se representa en un sistema digital por cantidades físicas

Competencias genéricas y específicas

Competencias básicas. Son la combinación de destrezas, conocimientos y

Competencias genéricas. Se refieren al conjunto de conocimientos, actitudes,

Competencias específicas. Las competencias específicas se adquieren con la

AL ENTREGAR UN PROYECTO AL PROFESOR SE

UNIDAD I: FUNDAMENTOS DE SISTEMAS DIGITALES

PY1 (1-Bit full adder)

Sumador completo de En equipo

Sumador completo de1 En equipo

(vea y lea información)

UNIDAD IV: FUNCIONES Y COMPUERTAS LÓGICAS

(vea y lea información)

Contador bidireccional En equipo

(vea y lea información)

Semáforo de dos vías En equipo

Vea opciones en clase

(vea y lea información)

IDEM ANTERIOR, USO Equipo

RELOJ BÁSICO: HORAS,

Games. Master Mind. Equipo

Nombre: SUMADOR COMPLETO DE UN BIT (v.1)

Sumas que realiza:

Entradas Salidas Entradas Salidas

Competencia Específica: Generación de tecnología básica.

Vista frontal A+B+C=S Vista posterior Vista lateral

Este es un prototipo hecho por el profesor (hace muchos años…)

Nombre: 1-BIT FULL ADDER (v.2)

2) DISEÑE Y COMPRUEBE EL FUNCIONAMIENTO DE UN SUMADOR

ENTRADAS (3) A 1-bit S0 SALIDAS(2)

Competencias Específicas Usar e identificar las

OR significa conección en paraleo (2 o más interruptores)

AND significa conección en serie (2 o más interruptores)

NOT significa conección en serie con la carga de un switch NC

Referencia: (Link) Digital Electronics -- Basic Logic Gates

3) DISEÑE Y COMPRUEBE EL FUNCIONAMIENTO DE UN SUMADOR

Competencias Específicas: Usar compuertas universales XOR or XNOR.

Link: Digital Electronics -- Boolean Algebra and Simplification

Nombre: 1-BIT FULL ADDER (SOFTWARE) (v.4)

4) DISEÑE Y COMPRUEBE EL FUNCIONAMIENTO DE UN SUMADOR

Competencias específicas: Programación y verificación en placa Arduino.

EN CUANTO LE SEA POSIBLE COMPRE UNA PLACA ARDUINO, LA MÁS

Consulte: http://www.arduino.cc/en/Reference/HomePage [Consulte ya]

EJERCICIO 1.- OBTENGA LA EXPRESIÓN BOOLENA PARA LA SALIDA

SWA SWB SWC

EJERCICIO 3.- COMPUERTA “OR” verifíque circuito.

Si se activa uno u otro interruptor o ambos prende el LED. LED = A + B

2) DISEÑE UN CONVERTIDOR DE SISTEMA NUMÉRICO BINARIO A CÓDIGO

a) CON CIRCUITERÍA INTEGRADA (HARDWARE)

Nombre: DECODIFICADOR DE BCD A 7-SEGMENTOS,

3) DISEÑE UN DECODIFICADOR DE BCD A 7-SEGMENTOS,

LA TABLA CORRESPONDIENTE ES LA SIGUIENTE.

LAS COMBINACIONES DEL 1010 AL 1111 SON IRRELEVANTES X (DON´T

Nombre: FUNCIÓN LÓGICA Z(A,B) ,

 LA FUNCIÓN Z(A,B) DEL CIRUITO SIGUIENTE