Hands-On: Model Development Using Verilog-A: Ahtisham Pampori Nanolab, Indian Institute of Technology Kanpur

Hands-on:
Model Development using

Verilog-A
Ahtisham Pampori
Nanolab, Indian Institute of Technology Kanpur
Contents
An introduction to XYCE and ADMS

Verilog-A Essentials
Resistor – Level 1
Nanolab, Indian Institute of Technology Kanpur 2
What is XYCE?
• According to them:
“Xyce (zīs, rhymes with “spice”) is an open source, SPICE-compatible, high-
performance analog circuit simulator, capable of solving extremely large circuit
problems by supporting large-scale parallel computing platforms.”
• Why XYCE?
One of the few open-source simulators to offer a well documented Verilog-A
integration.
More details at: https://xyce.sandia.gov/

Automatic Device Model Synthesizer (ADMS)
• Quoting Wikipedia:
“ADMS is a public domain software to translate Verilog-A models into C-models
which can be directly read by a number of SPICE simulators”
• ADMS has a commercial analogue: Tiburon Design Automation (owned by
Mentor Graphics) which is used by most of the contemporary SPICE simulators.
• Drawbacks:
▪ ADMS adds a Verilog-A model at compile-time while all commercial simulators do this at
runtime.
▪ ADMS has a limited repertoire for converting Verilog-A constructs.
• A recent forked version is available at: https://github.com/Qucs/ADMS

The “Plan”
.C
Verilog-A Inbuilt
Code ADMS XYCE Device
.h

Summary of steps to add a Verilog-A module to XYCE when
using the provided VM
• Compile Verilog-A code using $HOME/Documents/Veriloga/compile.sh
• Move the .C and .h files to $HOME/Documents/Xyce-6.10/src/DeviceModelPKG/ADMS
• Edit Makefile.am in $HOME/Documents/Xyce-6.10/src/DeviceModelPKG/ADMS and add the names of
the two files.
• Edit N_DEV_RegisterADMSDevices.C and include the header file you just copied and in the body of
the code, enter a line for registering the device.
• Run bootstrap in $HOME/Documents/Xyce-6.10
• Run compile.sh in $HOME/Documents/Xyce_build
• Run make in $HOME/Documents/Xyce_build
• Run sudo make all in $HOME/Documents/Xyce_build
Viola! Device registered!

Detailed steps for building XYCE and registering Verilog-A code can be found at :
https://xyce.sandia.gov/documentation/XyceADMSGuide.html

SPICE examples using XYCE
Series RLC circuit
V1 1 0 SIN(0V 10V 1GHz)

R1 1 2 100k
L1 2 3 1n
C1 3 0 1p
.tran 1ns 10ns

.print tran v(2,3) I(R1)
.end
SPICE examples using XYCE
MOSFET - IdVg MOSFET - IdVd
Vg 2 0 1V Vg 2 0 1V
Vd 5 0 1V Vd 5 0 1V
R1 5 1 1M R1 5 1 1M
M1 1 2 0 0 NM M1 1 2 0 0 NM
.MODEL NM NMOS L=1u W=10u .MODEL NM NMOS L=1u W=10u
.DC Vg 0 5 0.1 Vd 0 10 1 .DC Vd 0 10 0.1 Vg 0 5 1

.print DC V(2) Id(M1) .print DC V(1) Id(M1)
.end .end

Contents

Building Blocks - Comments
Examples of comments in Verilog-A:
▪ Inline Comments:
▪ Block Comments:
Why do I need to comment my code?

Because this is what happens when you don’t!

Building Blocks – Compiler Directives
• Same as preprocessor directives in C.
• Compiler directives are processed before compiling the code.
• Two key directives to know:

▪ ìnclude
▪ `define

Building Blocks – Compiler Directives II
• Both ìnclude and `define simply paste the contents of what lies in
front of them.
• ìnclude works with files i.e. it pastes the contents of the file
mentioned at the location it is invoked.
• Example:
• `define is used to abbreviate long strings or pieces of code by
assigning them a name (this name goes by the jargon “macro”)
• Example:

Building Blocks - Variables
• Two key variables to know:

▪ Integers
– Saved in 32-bit registers.
– Default to zero.
Example:
▪ Reals
– Described by IEEE STD-754-1985 for double precision floating point numbers.
– Saved in 64-bit registers.
– Default to zero.
Example:

Building Blocks - Parameters
• Used to define tunable parameters. Provide a knob for the circuit

designer.
• Two types:
▪ Instance Parameters
▪ Model Parameters
• Syntax:
Parameter [real|integer] name=value ([from|exclude]) (lower:upper)
• Example:

Building Blocks – Natures and Disciplines
Disciplines are used to specify the type of a continuous wire (ex: electrical, mechanical, rotational,
optical, thermal, etc.). Natures are used to describe the signals used in disciplines.
• Nature:
▪ A collection of attributes shared by a class of signals. e.g. A signal can be a voltage, current, charge,
temperature, etc.
▪ The attributes defined in a nature are:
– Units
– Access
– Abstol
– Abstol_Override
– Related Natures: ddt_nature and idt_nature
▪ Example:
nature Current
units = "A";
access = I;
abstol = 1p;
idt_nature = Charge;
endnature

Building Blocks – Natures and Disciplines II
• Disciplines:
▪ A discipline is a type used when declaring analog nodes, ports, or branches.
▪ Logic discipline not valid for Verilog-A
▪ Attributes of disciplines:
– Potential: The nature of the signal
measured across nodes.
– Flow: The nature of the signal
measured through a node pair.

Building Blocks – Modules, nodes, nets, ports and branches
• Module:
▪ Modules define reusable components in Verilog-A. In our case, the module is the device we
are trying to model.
• Node:
▪ A node is an electrically infinitesimal point of interconnection.
▪ Need to define discipline.
• Net:
▪ Nodes within a module are called nets.
▪ Need to define discipline.
• Ports:
▪ Nets which lie at the boundary of the module and let it communicate with other modules.
▪ Need to define discipline as well as directionality.
• Branch:
▪ A branch is a path between two nets.
▪ The branch derives its discipline from the net it is connected to.

Building Blocks – Modules, nodes, nets, ports and branches II
Module
Nets
Branch
Ports
= Nodes
Building Blocks - Access functions, contributions and
assignments
• Access functions, as the name suggests, are used to access potential
and flux signals between/on nets, ports or branches.
• Examples of access functions:
• Contribution statements (<+) are used to assign potential and flux

signals between/on nets, ports or branches.
• Assignment statements (=) are used to assign values to variables.

Contents

Resistor Level 1
res1
Instance Parameters: L,W

p n
Model Parameters: RHOS

Contents

Resistor Level 2
• Model description
Source: Gennady Gildenblat, Compact Modeling - Principles, Techniques and Applications

Resistor Level 2
• Analog Functions
• Parameter Bounds

Contents

Resistor Level 3
• Model description

Resistor Level 3
• $temperature function:
• Implementation of polynomial using pow():
• An efficient method: Horner’s Rule.

Contents

Resistor Level 4
• Using macros.
• Macros are supposed to be single lines of code
• Escaping newline.
• Can make a macro span multiple lines for legibility by properly escaping
newline characters.
• A discussion about efficiency: Macros v/s Functions
▪ Functions: Lead to stack-frames and call stacks which involve memory
allocation (slow processes).
▪ Macros: Significantly faster than functions. However, type resolution is absent.
If we define `square(a) a*a
`square(5) is 5*5=25
However, `square(1+4) is 1+4*1+4 = 9!!

Contents

Resistor Level 5
• Self heating
res1
Branch
te
rth ith
p n
A thermal
An electrical discipline net
discipline port

Recommended reading
• https://nanohub.org/resources/20580/download/2014.02.21-
Coram-NEEDS.pdf
• How to (and how not to) write a compact model in Verilog-A –
Geoffrey Coram
• Best Practices for Compact Modeling in Verilog-A - IEEE JEDS 2015

Thank You
Questions

Hands-On: Model Development Using Verilog-A: Ahtisham Pampori Nanolab, Indian Institute of Technology Kanpur

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Hands-on:

Model Development using

An introduction to XYCE and ADMS

More details at: https://xyce.sandia.gov/

Nanolab, Indian Institute of Technology Kanpur 4

Nanolab, Indian Institute of Technology Kanpur 5

Viola! Device registered!

Nanolab, Indian Institute of Technology Kanpur 6

Series RLC circuit

V1 1 0 SIN(0V 10V 1GHz)

.tran 1ns 10ns

MOSFET - IdVg MOSFET - IdVd

.DC Vg 0 5 0.1 Vd 0 10 1 .DC Vd 0 10 0.1 Vg 0 5 1

Nanolab, Indian Institute of Technology Kanpur 8

An introduction to XYCE and ADMS

Examples of comments in Verilog-A:

Why do I need to comment my code?

Nanolab, Indian Institute of Technology Kanpur 10

Nanolab, Indian Institute of Technology Kanpur 11

• Same as preprocessor directives in C.

• Compiler directives are processed before compiling the code.

• Two key directives to know:

Nanolab, Indian Institute of Technology Kanpur 12

Nanolab, Indian Institute of Technology Kanpur 13

• Two key variables to know:

Nanolab, Indian Institute of Technology Kanpur 14

• Used to define tunable parameters. Provide a knob for the circuit

Nanolab, Indian Institute of Technology Kanpur 15

Nanolab, Indian Institute of Technology Kanpur 16

Nanolab, Indian Institute of Technology Kanpur 17

Nanolab, Indian Institute of Technology Kanpur 18

• Contribution statements (<+) are used to assign potential and flux

Nanolab, Indian Institute of Technology Kanpur 20

An introduction to XYCE and ADMS

Instance Parameters: L,W

Nanolab, Indian Institute of Technology Kanpur 22

An introduction to XYCE and ADMS

Source: Gennady Gildenblat, Compact Modeling - Principles, Techniques and Applications

Nanolab, Indian Institute of Technology Kanpur 24

Nanolab, Indian Institute of Technology Kanpur 25

An introduction to XYCE and ADMS

Nanolab, Indian Institute of Technology Kanpur 27

• An efficient method: Horner’s Rule.

Nanolab, Indian Institute of Technology Kanpur 28

An introduction to XYCE and ADMS

Nanolab, Indian Institute of Technology Kanpur 30

An introduction to XYCE and ADMS

Nanolab, Indian Institute of Technology Kanpur 32

Nanolab, Indian Institute of Technology Kanpur 33

Nanolab, Indian Institute of Technology Kanpur 34

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