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Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2005)
0-7695-2456-7/05-$20.00 © 2005 IEEE
3. 802.16 and OFDM Overview
FEC Interleaving IFFT GI
3.1. OFDM Fundamentals Coder + mapping Addition
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2005)
0-7695-2456-7/05-$20.00 © 2005 IEEE
stored on ROMs. Finally data are stored on a FIFO
component to pass to next stage, as shown at Fig. 3.
4.2. Inter-leaver
Parallel butterfly algorithms for IFFT are the most The conformance with Sdt 802.16 [7] could be
suitable for OFDM [9], this work uses a radix-4 validated by running a simulation at MatLab using test
butterfly generated by the Xilinx IP core Generator. data provided by the standard. Using this high level
Data arrives to IFFT module at 16 MHz, but it works tool simplifies all prototyping process contrasting with
three times slower than the main clock which was set a VHDL based testbench validation approach which
at 80 MHz, for this reason the incoming data is up- would require more prototyping time and effort. All
sampled by 5 and then down-sampled by 3, thus specified modulation schemes (QPSK, 16-QAM and
additional logic is required to mark the data as valid or 64-QAM) were tested at base band frequency (20
not, and then pass it to the IFFT block. MHz), no channel model were used, neither DDS or
The IFFT block takes 768 cycles to perform the DDC were performed at this time.
transform (256 times 3), the results are stored into four The model was targeted to a Virtex 2 xc2v3000-
FIFO blocks; two of them store the real and 4fg676, the result was that all mentioned modules
imaginary coefficients of the 256 points transform; the requires around 18% of the available resources, while
other two FIFO stores the last 64 real and imaginary the Maximum Frequency estimated was 98.376 MHz,
coefficients that will be used as cyclic prefix, in order which is enough for the requirement of 80 MHz
to have an 320 points symbol at the end. The architecture to generate 20 MHz (OFDM Symbol
architecture of this module is shown at Fig. 5. frequency specified at 802.11a) and 16 MHz clocks.
Detailed area results are shown at Tables 1. These
results were obtained using Xilinx´s ISE 6.3i tool.
Since this work implements 802.16, it needs more
resources than the presented at similar works for
802.11. Contrasting 802.11 needs 64 points FFT while
802.16 needs at least 256 points FFT. Now if it is
considered that 802.11 takes around 12% of the same
device, It can be said that a device similar to the Virtex
2 xc2v3000-4fg676, could be configured either as
802.11 or 802.16 modulator.
Since 802.16 implementations are not reported, it is
helpful to compare some modules with similar works,
for instance, this work IFFT takes 768 cycles to
perform the transform while the ASIC DSP proposed
at [10] would take 2056. The results from the IFFT are
buffered to a dual port memory at [5], this work uses a
Fig. 3. PSK or QAM mapping model. FIFO structure to store results and cyclic prefix which
is a simple way to produce the prefix adding stage.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2005)
0-7695-2456-7/05-$20.00 © 2005 IEEE
Mentioned related works use fixed configuration of standards into one configurable architecture to support
the system to be implemented, this work supports all SDR and 4G.
possible QAM or PSK alphabets. This work has been
tested with a ¼ cyclic prefix, but it could be switched Acknowledgments
to any other supported size.
One of the limitations found while working with This work has been partially supported by
System Generator was the use of only one main clock, CONACyT “National Council for Science and
besides this inconvenient this tool allows a rapid Technology” of México under grant number 181689.
prototyping
References
[1] S. J. Vaughan-Nichols, “OFDM: Back to the Wireless
Future” IEEE Computer, pp. 19–21, Dec. 2002.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2005)
0-7695-2456-7/05-$20.00 © 2005 IEEE