0 Bewertungen0% fanden dieses Dokument nützlich (0 Abstimmungen)
31 Ansichten6 Seiten
This document contains a directory structure that outlines video lessons on various topics in digital logic design. The topics covered include logic functions, minimization, combinational circuit design and synthesis, sequential circuits, and number systems. There are over 200 video files listed across these topics that provide instruction on concepts such as logic gates, Boolean algebra, Karnaugh maps, multiplexers, decoders, flip flops, counters, and number representation systems.
This document contains a directory structure that outlines video lessons on various topics in digital logic design. The topics covered include logic functions, minimization, combinational circuit design and synthesis, sequential circuits, and number systems. There are over 200 video files listed across these topics that provide instruction on concepts such as logic gates, Boolean algebra, Karnaugh maps, multiplexers, decoders, flip flops, counters, and number representation systems.
This document contains a directory structure that outlines video lessons on various topics in digital logic design. The topics covered include logic functions, minimization, combinational circuit design and synthesis, sequential circuits, and number systems. There are over 200 video files listed across these topics that provide instruction on concepts such as logic gates, Boolean algebra, Karnaugh maps, multiplexers, decoders, flip flops, counters, and number representation systems.
│ ├── DLD-10 Counting the number of functions and Neutral functions.mp4 │ ├── DLD-11 Venn diagram representation.mp4 │ ├── DLD-12 Contact representation.mp4 │ ├── DLD-13 Nested function.mp4 │ ├── DLD-14 NAND gate and properties.mp4 │ ├── DLD-15 NOR gate and Properties.mp4 │ ├── DLD-16 EX-OR gate and Properties.mp4 │ ├── DLD-17 EX-NOR gate and Properties.mp4 │ ├── DLD-18 Properties of EX-OR and EX-NOR.mp4 │ ├── DLD-19 Minimum number of gates required for EX-OR and EX-NOR.mp4 │ ├── DLD-1 Basic properties of switching algebra.mp4 │ ├── DLD-20 Functionally Completeness.mp4 │ ├── DLD-21 Example 1 on Functional Completeness.mp4 │ ├── DLD-22 Example 2 on Functional Completeness.mp4 │ ├── DLD-23 Example 3 on Functional Completeness.mp4 │ ├── DLD-24 Example 4 on Functional Completeness.mp4 │ ├── DLD-25 Example 5 on Functional Completeness.mp4 │ ├── DLD-26 Example 6 on Functional Completeness.mp4 │ ├── DLD-27 Self Dual Functions.mp4 │ ├── DLD-28 Number of Self Dual Functions.mp4 │ ├── DLD-29 Self Dual Functions are closed under Complementation.mp4 │ ├── DLD-2 Switching expressions and simplification.mp4 │ ├── DLD-30 Introduction to Electronic gates.mp4 │ ├── DLD-31 Positive and Negative logic systems.mp4 │ ├── DLD-32 Gate 2016 question on EX-OR.mp4 │ ├── DLD-33 Gate 2006 on gray code function.mp4 │ ├── DLD-3 DeMorgans law and simplification.mp4 │ ├── DLD-4 Switching functions.mp4 │ ├── DLD-5 Canonical Sum of Products_2.mp4 │ ├── DLD-6 Canonical Product of sums.mp4 │ ├── DLD-7 Examples of canonical forms.mp4 │ ├── DLD-8 Functional properties.mp4 │ └── DLD-9 Number of Functions.mp4 ├── 2.Minimization │ ├── DLD-10 Minimal SOP Example.mp4 │ ├── DLD-11 Minimal POS.mp4 │ ├── DLD-12 Examples on Minimal POS.mp4 │ ├── DLD-13 Introduction to Don't cares.mp4 │ ├── DLD-14 Examples on don't care set 1.mp4 │ ├── DLD-15 Examples on don't care set 2_1.mp4 │ ├── DLD-15 Examples on don't care set 2.mp4 │ ├── DLD-16 Examples on don't care set 2_2.mp4 │ ├── DLD-17 examples on don't care set 2_3.mp4 │ ├── DLD-18 examples on don't care set 2_4.mp4 │ ├── DLD-19 examples on don't care set 2_5.mp4 │ ├── DLD-1 Intoduction to Minimization of Boolean expressions.mp4 │ ├── DLD-20 examples on dont care set 3.mp4 │ ├── DLD-21 Finding Minimal Expressions.mp4 │ ├── DLD-22 Branching Technique for Minimising Cyclic Functions.mp4 │ ├── DLD-23 Implicant and Prime Implicant Difference.mp4 │ ├── DLD-24 Converting a Function into Self Dual.mp4 │ ├── DLD-25 Combining Functions having Don't Cares.mp4 │ ├── DLD-26 Prime Implicants and Don't Cares.mp4 │ ├── DLD-27 Number of Minimal Expressions.mp4 │ ├── DLD-28 Beautiful Question on Prime Implicant Chart.mp4 │ ├── DLD-29 Variable Entrant Maps(VEM).mp4 │ ├── DLD-2 Irredundant (or) Irreducible Expressions.mp4 │ ├── DLD-30 Minimisation using VEM.mp4 │ ├── DLD-31 Example on VEM.mp4 │ ├── DLD-32 Problem on K-Map.mp4 │ ├── DLD-33 finding the free variables.mp4 │ ├── DLD-34 Relationship between Minimal POS SOP in case of don't cares -- 1.mp4 │ ├── DLD-35 Relationship between Minimal POS SOP in case of don't cares -- 2.mp4 │ ├── DLD-36 Comparing independent variables in minimal SOP and POS.mp4 │ ├── DLD-37 Number of irredundant and minimal expressions.mp4 │ ├── DLD-38 don't cares are never included in the prime Implicant chart.mp4 │ ├── DLD-39 Number of Irredundant and Minimal Expressions.mp4 │ ├── DLD-3 K-Map Introduction.mp4 │ ├── DLD-40 Functions nvolving Functions Example 1.mp4 │ ├── DLD-41 Functions involving Functions example 2.mp4 │ ├── DLD-42 Functions involving Functions Example 3.mp4 │ ├── DLD-4 K map Simplification.mp4 │ ├── DLD-5 Examples on K-Map.mp4 │ ├── DLD-6 Covering Functions.mp4 │ ├── DLD-7 Implicants and Prime Implicants.mp4 │ ├── DLD-8 Essential Prime Implicants.mp4 │ └── DLD-9 Procedure for obtaining Minimal SOP.mp4 ├── 3.Design and Synthesis of Combinational circuits │ ├── 10 DLD- Comparator.mp4 │ ├── 11 DLD- Introduction to MUX.mp4 │ ├── 12 DLD- Proving MUX is functionally complete.mp4 │ ├── 13 DLD- Implementing functions with MUX example 1.mp4 │ ├── 14 DLD- Implementing functions with MUX example 2.mp4 │ ├── 15 DLD- multiplexer with enable input.mp4 │ ├── 16 DLD- relationship between select lines and inputs of a mux.mp4 │ ├── 17 DLD- cascading multiplexers- ex 1.mp4 │ ├── 18 DLD- cascading multiplexers - ex 2.mp4 │ ├── 19 DLD- cascading multiplexers - ex 3.mp4 │ ├── 1 DLD- Introduction to Logic Design.mp4 │ ├── 20 DLD- Expansion of multiplexers.mp4 │ ├── 21 DLD- Assigning select lines while expanding the MUX.mp4 │ ├── 22 DLD- Introduction to Demultiplexer.mp4 │ ├── 23 DLD- introduction to decoder.mp4 │ ├── 24 DLD- implementing functions with decoder example 1.mp4 │ ├── 25 DLD- implementing functions with decoder example 2.mp4 │ ├── 26 DLD- implementing functions with decoder example 3.mp4 │ ├── 27 DLD- converting one code to other code using decoder.mp4 │ ├── 28 DLD- ROM implementation using decoder.mp4 │ ├── 29 DLD- Implementing Functions using only Decoder.mp4 │ ├── 2 DLD- AND-OR OR-AND realization.mp4 │ ├── 30 DLD- Implementing Functions using Decoder + Multiplexer Example 1.mp4 │ ├── 31 DLD- Implementing Functions using Decoder + Multiplexer Example 2.mp4 │ ├── 32 DLD- Decoder with Enable Input.mp4 │ ├── 33 DLD- Constructing 3x8 Decoder using 1x2 Decoder.mp4 │ ├── 34 DLD- Constructing 4x2 Decoder using 1x2 Decoder.mp4 │ ├── 35 DLD- Constructing 6x64 Decoder using 3x8 Decoder.mp4 │ ├── 36 DLD- Expansion of Decoder in general.mp4 │ ├── 37 DLD- Constructing 7x128 Decoder using 3x8 Decoder.mp4 │ ├── 38 DLD- Expansion of Decoders in another way.mp4 │ ├── 39 DLD- Address Expansion of ROM.mp4 │ ├── 3 DLD- Minimum No-of NAND gates example.mp4 │ ├── 40 DLD- Word Expansion of ROM.mp4 │ ├── 41 DLD- Finding the Address ranges of Devices.mp4 │ ├── 42 DLD- Example on Enabling a Device.mp4 │ ├── 43 DLD- Finding the address ranges of Memory Devices.mp4 │ ├── 44 DLD- Introduction to Encoders.mp4 │ ├── 45 DLD- Priority Encoders.mp4 │ ├── 46 DLD- Introduction to Hazards.mp4 │ ├── 47 DLD- Hazards and test vectors.mp4 │ ├── 48 DLD- Examples on Test Vectors.mp4 │ ├── 49 DLD- Half Adder.mp4 │ ├── 4 DLD- NOR- NOR example.mp4 │ ├── 50 DLD- Full Adder.mp4 │ ├── 51 ripple carry adder.mp4 │ ├── 52 DLD- Carry Lookahead Adder.mp4 │ ├── 53 Carry look ahead adder implementation.mp4 │ ├── 54 DLD- Hybrid adder.mp4 │ ├── 55 DLD- Serial adder.mp4 │ ├── 56 DLD- Binary adder_subtractor.mp4 │ ├── 57 BCD Adder.mp4 │ ├── 58 DLD- Invalid combinations for BCD adder.mp4 │ ├── 59 DLD- 2 bit comparator.mp4 │ ├── 5 DLD- Minimum No-of NOR gates Example.mp4 │ ├── 60 3, 4 bit comparators.mp4 │ ├── 61 Analysing all the cases of comparators.mp4 │ ├── 62 Gate 2016 question on multiplener from Ravi on Vimeo.mp4 │ ├── 63 Time complexity of ripple carry adder.mp4 │ ├── 64 Time complexity carry look ahead adder.mp4 │ ├── 6 DLD- Minimum No-of NOR gates Example.mp4 │ ├── 7 DLD- EX-OR and EX-NOR implementation with NOR and NAND gates.mp4 │ ├── 8 DLD- Half adder.mp4 │ └── 9 DLD- Half subtracter.mp4 ├── 4. Sequential Circuits │ ├── 10 DLD- Example on Flipflop 1.mp4 │ ├── 11 DLD- Example on Flipflop 2.mp4 │ ├── 12 DLD- Introduction to Flipflop Inter Conversion.mp4 │ ├── 13 DLD- Inter Conversion of Flipflops Example 1.mp4 │ ├── 14 DLD- Inter Conversion of Flipflops Example 2.mp4 │ ├── 15 DLD- Inter Conversion of Flipflops Example 3.mp4 │ ├── 16 DLD- Inter Conversion of Flipflops Example 4.mp4 │ ├── 17 Inter Conversion of Flipflops Example 5.mp4 │ ├── 18 DLD- Introduction to Counters.mp4 │ ├── 19 DLD- Asynchronous and Synchronous Counters.mp4 │ ├── 1 DLD- Introduction to Sequential Circuits.mp4 │ ├── 20 DLD- Shift Counters.mp4 │ ├── 21 DLD- Mod 2 Ring Counters.mp4 │ ├── 22 DLD- Mod 4 Ring Counters.mp4 │ ├── 23 DLD- Mod 4 Johnson Counter.mp4 │ ├── 24 DLD- Mod 6 Johnson Counter.mp4 │ ├── 25 DLD- Mod 4 Gray Counter using T-FF.mp4 │ ├── 26 DLD- Mod 4 Gray Counter using D-FF.mp4 │ ├── 27 DLD- Mod 4 Gray Counter using 1 D and 1 T flipflop.mp4 │ ├── 28 DLD- Counter using two different FFs.mp4 │ ├── 29 DLD- Model on analysis Counting States and Sequence Generations.mp4 │ ├── 2 DLD- Latch and Flipflop.mp4 │ ├── 30 DLD- Deriving the Clock Frequency.mp4 │ ├── 31 DLD- Self starting and free running.mp4 │ ├── 32 DLD- Example on selfstarting and free running Counters.mp4 │ ├── 33 DLD- Counter using 3 different FFs.mp4 │ ├── 34 DLD- Example on Combinational Circuits and FFs.mp4 │ ├── 35 DLD- Introduction to Asynchronous Counters.mp4 │ ├── 36 DLD- Mod 8 up Counter.mp4 │ ├── 37 DLD- Mod 4 up Counter.mp4 │ ├── 38 DLD- Mod 4 down Counter.mp4 │ ├── 39 DLD- Mod 8 random Counter.mp4 │ ├── 3 DLD- SR Flipflop.mp4 │ ├── 40 DLD- Applications of Flip flops.mp4 │ ├── 41 DLD- 3 bit shift right register.mp4 │ ├── 42 DLD- Example 1 on shift right register.mp4 │ ├── 43 DLD- Example 2 on shift right register.mp4 │ ├── 44 DLD- Binary to gray convertor.mp4 │ ├── 45 DLD- Finding 2's complement.mp4 │ ├── 46 Gate 2001 on counter from Ravi on Vimeo.mp4 │ ├── 47 Gate 2004 on sr-latch from Ravi on Vimeo.mp4 │ ├── 48 Gate 2014 on counter from Ravi on Vimeo.mp4 │ ├── 49 Gate 2015 on sequency generation from Ravi on Vimeo.mp4 │ ├── 4 DLD- Clocked Flipflops.mp4 │ ├── 50 Gate 2015 question on Flip Flops from Ravi on Vimeo.mp4 │ ├── 51 Gate 2016 on sequency genetaion from Ravi on Vimeo.mp4 │ ├── 5 DLD- Positive Level Triggered.mp4 │ ├── 6 DLD- Edge Triggered.mp4 │ ├── 7 DLD- JK Flipflop.mp4 │ ├── 8 DLD- T-Flipflop.mp4 │ └── 9 DLD- D-Flipflop.mp4 ├── 5. Number system │ ├── 10 DLD- Example 7.mp4 │ ├── 11 DLD- Example 8.mp4 │ ├── 12 DLD- Complementary number system.mp4 │ ├── 13 DLD- Why we use complements.mp4 │ ├── 14 DLD- Substraction in diminished radix complement.mp4 │ ├── 15 DLD- Examples on diminished radix complement.mp4 │ ├── 16 DLD- Examples on subtraction in radix complement.mp4 │ ├── 17 DLD- Summary of subtraction using complements incase of unsigned numbers.mp4 │ ├── 18 Signed number representation.mp4 │ ├── 19 Example on signed number representations.mp4 │ ├── 1 Introduction to Number system.mp4 │ ├── 20 Ranges of signed number representations.mp4 │ ├── 21 Examples on Ranges.mp4 │ ├── 22 Sign bit extension.mp4 │ ├── 23 Example on sign bit extension.mp4 │ ├── 24 DLD- Overflow.mp4 │ ├── 25 DLD- Classification of binary codes.mp4 │ ├── 26 8421, Excess-3, 3321 codes.mp4 │ ├── 27 Examples on codes.mp4 │ ├── 28 DLD- BCD addition.mp4 │ ├── 29 Excess-3 addition.mp4 │ ├── 2 DLD- Conversion to base 10.mp4 │ ├── 30 DLD- Gray code.mp4 │ ├── 31 DLD- Binary to gray and vice versa.mp4 │ ├── 32 DLD- Error detection.mp4 │ ├── 33 DLD- Error correction.mp4 │ ├── 34 DLD- Hamming code.mp4 │ ├── 35 DLD- Examples on Hamming code.mp4 │ ├── 36.1 Intro to floationg point representation.mp4 │ ├── 36 Floating point conversions.mp4 │ ├── 37 Floating point representation-1.mp4 │ ├── 38 Floation point representation -2.mp4 │ ├── 39 Flotation point representation example 1.mp4 │ ├── 3 Conversion from base 10.mp4 │ ├── 40 Example 2.mp4 │ ├── 41 Example 3.mp4 │ ├── 43 Intro to IEEE standards.mp4 │ ├── 44 Single precision.mp4 │ ├── 45 Double precision.mp4 │ ├── 46 Example 1 on Single precision.mp4 │ ├── 47Example 2 on single precision.mp4 │ ├── 48 Example 1 on double precision.mp4 │ ├── 49 Example 2 on double precision.mp4 │ ├── 4 DLD- Minimum number of bits required for inter conversion -- ex 1.mp4 │ ├── 50 Example on single and double precision.mp4 │ ├── 51 Gate 2016 on null of integers from Ravi on Vimeo.mp4 │ ├── 52_DLD- Binary multiplication(partial sum method).MP4 │ ├── 53_DLD- Idea behind Booth's algorithm.MP4 │ ├── 54_DLD- Booth's algorithm example.MP4 │ ├── 55_DLD- Booth's algorithm.MP4 │ ├── 56_DLD- Booth algorithm operations flow.MP4 │ ├── 57_DLD- Advanteges and Dis- Advantages of Booth's algorithm.MP4 │ ├── 58_DLD- Example on fractional form.MP4 │ ├── 59_DLD- Example on fractional and implicit forms.MP4 │ ├── 5 Minimum number of bits required for inter conversion -- ex 2.mp4 │ ├── 6 DLD- Example 3.mp4 │ ├── 7 DLD- Example 4.mp4 │ ├── 8 Example 5.mp4 │ └── 9 Example 6.mp4 └── practice qs ├── DL(Minimization)_Q3_W_pdf.PDF ├── DL(Minimization)_s3_W_pdf.PDF ├── DL(Number_System)_Q2_new_W_pdf.PDF ├── DL(Number_System)_s2_new_W_pdf.PDF ├── DL--Q1.pdf ├── dl--S1.pdf ├── DL(Sequential_circuits)__Q3_W_pdf.PDF ├── DL(Sequential_circuits)__s3_1_W_pdf.PDF ├── Practice Question Set 2.pdf ├── Practice Questions Set 3.pdf ├── Solutions to Set 2.pdf └── Solutions to Set 3.pdf