See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/328891315

Fast Delayed Signal Cancellation based PLL for Unbalanced Grid Conditions

Conference Paper · October 2018

CITATIONS READS
0 83

5 authors, including:

David Guajardo Matias Diaz

University of Santiago, Chile University of Santiago, Chile
1 PUBLICATION   0 CITATIONS    39 PUBLICATIONS   151 CITATIONS   

SEE PROFILE SEE PROFILE

Mauricio Espinoza Roberto Cardenas

University of Costa Rica University of Chile
25 PUBLICATIONS   91 CITATIONS    143 PUBLICATIONS   4,437 CITATIONS   

SEE PROFILE SEE PROFILE

Some of the authors of this publication are also working on these related projects:

Desing and implementation of AC/AC modular multilevel converters for wind energy applications View project

Hybrid AC/DC Microgrids View project

All content following this page was uploaded by Matias Diaz on 12 November 2018.

The user has requested enhancement of the downloaded file.

 Fast Delayed Signal Cancellation based PLL for
unbalanced grid conditions
Camilo Contreras, David Guajardo, Matias Diaz, Felix Rojas, Mauricio Espinoza, Roberto Cardenas
Abstract—Frequency identification is one of the most critical
issues for grid-connected power converters, especially when the
grid is unbalanced or distorted. Therefore, this paper proposes
a novel frequency estimator with fast convergence for balance
and unbalanced grid-voltage faults. The proposed algorithm is
based on a Phase Locked Loop (PLL), enhanced with a fast
positive and negative sequence detector. Delayed Signal Cancel-
lation methodology with fast convergence is investigated under
single-phase and two-phase voltage dip. The effectiveness of the
proposed PLL is validated using simulations and experimental
results.
Keywords—Phase Locked Loop, Double Synchronous Ref-
erence Frame, Double Second Order Generalized Integrator,
Delayed Signal Cancellation.
I. I NTRODUCTION
Proper synchronisation is one of the most critical control
tasks for grid-connected power electronics, especially in the
connection of distributed generators which need information
of the amplitude, phase and frequency of the grid-voltages
[1]. As the amount of distributed generation connected to the
grid increases, grid code and standards have become stricter
to prevent grid instability [2], [3]. Therefore, fast and accurate
detection of the grid-frequency is necessary to fulfil grid codes
[4], [5]. To achieve grid-frequency and grid synchronisation,
many different techniques can be employed. The first one is the
zero-crossing method that finds the zero-crossing points of the
grid-voltage to calculate the phase and frequency. However,
this method can only detect the phase information at each
half cycle, which reduces its performance [6]. The angle and
frequency of the grid-voltage can be obtained using filtering
methods implemented in αβ or dq frames, considering that
the filter has to be appropriately designed to avoid undesired
delays and oscillations [7], [8].
The most commonly used grid-frequency estimator are
PLLs implemented in Synchronous Reference Frame (SRF)
[9]. In this case, the grid-voltages are transformed to a dq
reference frame controlling the angular position of this ref-
erence frame. A feedback control loop regulates the quadra-
ture component to zero, and then the direct component will
depict the same phase and frequency than the grid voltage.
SRFPLLs yield to an effective frequency and phase estimation
under balanced grid conditions [1]. However, when the grid
voltage presents harmonic distortion or unbalances, SRF-PLLs
D. Guajardo, C. Contreras, M. Diaz, and F. Rojas are with the Department
of Electrical Engineering, University of Santiago of Chile
M. Espinoza is with the Department of Electrical Engineering, University
of Costa Rica.
R. Cardenas is with the Department of Electrical Engineering, University
of Chile.
becomes deficient due to the presence of a negative sequence
component of the grid voltage. Therefore, different PLL
structures incorporate negative and positive sequence compo-
nents separation. Typical examples are the Dual Synchronous
Reference Frame (DSFR) PLL [10], the Dual Second Order
Generalised Integrator (DSOGI) PLL [2], and the Delayed
Signal Cancellation (DSC) PLL [11]. The main disadvantage
of using DSRF-PLL, DSOGI-PLL and DSC-PLL is that at
least, a significant delay T /4 (5 ms for 50 Hz) is introduced
in the positive and negative sequence components, affecting
the frequency estimation. In digital implementations, the ratio
T /4Ts (where Ts is the sample time) must be an integer,
which is not always feasible [12]. In this context, this paper
proposes a novel PLL structure equipped with a Fast Delayed
Signal Cancellation (FDSC) algorithm. Using the proposed
FDSC-PLL the delay of T /4 can be significantly reduced
and, therefore, the frequency estimation is enhanced. The
effectiveness of the proposed PLL is validated using sim-
ulations and experimental results. The rest of this paper is
organised as follows: Section II first provides an overview of
the conventional PLL systems Then Section III presents the
proposed FDSC-PLL structure. Simulations results are shown
in Section IV and experimental results in Section V. Finally,
Section VI presents conclusions.
II. OVERVIEW OF PLL STRUCTURE FOR UNBALANCE
GRID - VOLTAGE CONDITIONS
In this section the most used PLL structure for unbalance
grid conditions are briefly described.
A. Double Synchronous Reference Frame PLL
This method was introduced as an improvement of the SRF-
PLL [10]. The main limitations of SRF-PLLs lie in the poor
performance when the grid-voltage is unbalanced, or it has
harmonic contamination. In these cases, low bandwidth filters
are used to reject the effects of the harmonics at the output of
the PLL. However, the use of filters slow-down the dynamic
response of the PLL.
The DSRF-PLL identifies the positive and negative se-
quence components. Additionally, it has a decoupling network
that allows cancelling the double frequency oscillations that
are generated in the quadrature voltage vq due to the negative
sequence voltage [10]. Therefore, the bandwidth of the PLL
is not reduced which results in a more accurate identification
of the frequency and most suitable instantaneous phase angle
estimation. In fig. 1, a diagram of DSRF-PLL method is
shown.

Fig. 1: DSRF-PLL.
Fig. 2: DSOGI-PLL.
B. Double Second Order Generalized Integrator PLL
Similarly to the DSRF-PLL, this algorithm is also based on
the separation of sequence components, but it has a better
dynamic response [2]. The DSOGI-PLL is shown in Fig.
2. This algorithm incorporates the generation of quadrature
signals to obtain the positive and negative sequence compo-
nents. Then, the positive sequence component is used to input
a conventional PLL, through which the phase angle φg is
obtained.
C. Delayed Signal Cancellation PLL
This effective method of separation of sequence consists of
a delay of the signal in a quarter of period of the fundamental
frequency. The representation of your estimated sequence
components this method is as follows:
T
p vg (t) + jvg (t − ) digital implementation causes an amplification of the noise
v̂gαβ = 4 (1)
2 vg (t), an expression of vs (t) is proposed.
n vg (t) − jvg (t − T4 )
v̂gαβ = (2)
2
where T is period of the fundamental frequency.
The Delayed Signal Cancellation (DSC-PLL) was until
the moment the method of separation of favourite sequence
due to its dynamic response and of over-modulation before
Fig. 3: DSC-PLL.
imbalances produced in the three-phase Grid. In fig. 3 is shown
a diagram of DSC-PLL.
III. P ROPOSED FDSC-PLL
Fast Delayed Signal Cancellation is proposed as an im-
provement to the DSC-PLL because the main disadvantages
of using DSC-PLL were recorded at the time of digital
p n
implementation, when using v̂gαβ , v̂gαβ generates a significant
delay (5ms for 50 Hz) to create the result. Furthermore, in
this implementation, estimate the delay is made considering
the sampling time Ts being the ratio delay (KTs ) expressed
by:
T
KTs = (3)
4Ts
The previous expression is not always an integer number,
which significantly affects the results obtained from this
method. Another disadvantage of DSC-PLL is the amount of
memory required to store the delayed vector vαβ (t − T4 ). The
conventional DSC-PLL sequence separation method and the
FastDSC-PLL method are affected by harmonic distortion, a
previous filtering process must be performed before applying
the methods above.
Voltage vector is composed of positive- and negative-
sequence components as follows:
p n
v̂gαβ v̂gαβ
z }| { z }| { (4)
vg = v p ejωt+φ1 + v n e−jwt+φ2
In (4) where v p ejωt+φ1 is the positive sequence component
and v n e−jwt+φ2 is the negative sequence component, φ1 and
φ2 are arbitrary phase shift angles. Because of simplicity these
angles are neglected. Using (4), the DSC algorithm can be
written as:
p n
With tensions v̂gαβ , v̂gαβ filtered and considering that the
vs = vg (wt) − e−jφd vg (wt − φd ) (5)
where the delay angle θd in the experimental implementa-
2πT
tion is calculated as θd = N Ts , where N is an integer. Using
(4) in (5) and assuming φ1 = φ2 = 0 , the vector vs is obtained
as:
 200
vs =vgp ejwt +vgn e−jwt

Voltage
100
(6)

(V)
− e−jθd [vgp ej(wt−θd ) +vgn e−j(wt−θd ) ] 0
-100
By simple inspection of (6) it is concluded that the negative
-200
sequence: (a)
200
p vs

Voltage
v̂gαβ = 100
[1 − e−j2θd ]

(V)
0
(7)
p [vg (wt) − e−jθd vg (wt − θd )](1 − ej2θd ) -100
v̂gαβ =
2[1 − cos(2θd )] -200
p (b)
where v̂gαβ .The negative sequence component is cancelled, 200
obtaining the following expression:

Voltage
100

(V)
0
n [vg (wt) − ejθd vg (wt − θd )](1 − e−j2θd ) -100
v̂gαβ = (8)
2[1 − cos(2θd )] -200
0.9 1.0 1.1 1.2 1.3
It can be shown that (7) and (8) are equivalent to (1)and (2) (c)
when θd → 0. The time delay of NTs seconds corresponds
Time(s)
to a delay angle of θd rads. For instance, the delay is T4 56

Frequency
for the conventional DSC which correspond to delay angle
of θd = ω ∗ T /4 = π/2. Notice that the use of θd > π2 is also
(HZ)
50
possible. Using (7) and (8) and separating by αβ-components,
the following expressions are obtained:
44
k1 − k1 cos(2θd ) + k2 sin(2θd ) 0.970 0.980 0.990 1.000 1.010 1.020 1.030
v̂αp = (9) (d)
2[1 − cos(2θd )]
Time (s)
k2 − k2 cos(2θd ) − k1 sin(2θd )
v̂βp = (10) Fig. 4: Response during 50% single phase voltage dip: a)
2[1 − cos(2θd )]
Voltages ABC , b)Voltage αβ+, c)Voltage αβ-, d) Frequency
k3 − k3 cos(2θd ) + k4 sin(2θd ) PLLs
v̂αn = (11) 200
2[1 − cos(2θd )]
100
Voltage

k4 − k4 cos(2θd ) − k3 sin(2θd )
(V)

v̂βn = (12) 0
2[1 − cos(2θd )]
-100
where k1 , k2 , k3 , and k4 stand for: -200
0.9 1.0 1.1 1.2 1.3
θd θd
k1 = vgα − vgα cos(θd ) − vgβ sin(θd ) (13) (a)
Time (s)
θd θd 56
Frequency

k2 = vgβ − vgβ cos(θd ) + vgα sin(θd ) (14)

FDSC-PLL
(HZ)

50 DSC-PLL
θd θd DSOGI-PLL
k3 = vgα − vgα cos(θd ) + vgβ sin(θd ) (15)
44
0.970 0.980 0.990 1.000 1.010 1.020 1.030
θd θd
k4 = vgβ − vgβ cos(θd ) − vgα sin(θd ) (16) (b)
Time (s)
IV. S IMULATION RESULTS
Fig. 5: Response during 50% two-phase voltage dip: a) Voltage
Three PLL are implemented in PLECS for an unbalance ABC, b)Frequency PLLs
three phase circuit, which has the same parameters than the
experimental setup (see Fig. X). The source feed three methods
V. E XPERIMENTAL I MPLEMENTATION
for component sequences separation DSOGI-PLL, DSC-PLL
and FastDSC-PLL. In this case, a single-phase and two-phase The experimental setup is presented in Fig. 7, and it
voltage dip is tested for 200 ms. The voltages αβ+,αβ− comprises a control platform and a power stage. The control
and frequencies for 50% single phase voltage dip is presented platform is composed of a Texas-Instrument Digital Signal
in Fig. (4). The responses of frequencies for 50% two-phase Processor (DSP) connected to an Actel Field Programmable
voltage dip is presented in Fig. (5). Gate Array (FPGA) board. The DSP board used in this
 Fig. 6: Proposed FDSC-PLL.

application is based on a TMS320C67 processor. For data that the overshot obtained with θd = T /20 (FDSC-PLL) is
acquisition purposes, a ten analogue-digital channels board is higher than θd = T /4 (DSC-PLL), but FDSC-PLL is faster
incorporated in the FPGA board. A sampling frequency of than DSC-PLL.
10 kHz is used. Hall-Effect transducers are used to measure
the voltages and currents. The power stage is composed of
a three-phase voltage source connected to an RL load. The
voltage source is emulated using an AC programmable power
source used to generate single and two phases voltage dips.
In the experimental implementation, three methods have been
considered: DSOGI-PLL, DSC-PLL, and FDSC-PLL. The
implementations of the FDSC-PLL method was programmed
with delays of T /4 (conventional DSC) and T /20.
In the experimental implementation, the same faults than in
simulation were tested, as shown in Fig. 8(a) and Fig. 9(a)
In this case, the tests were performed with the same failure
times than the used for the simulation results, where a single-
phase fault is observed in Fig. 8, and a two-phase fault are
illustrated Fig. 9.

𝑇𝑟𝑎𝑛𝑠𝑑𝑢𝑐𝑒𝑟𝑠
𝐻𝑎𝑙𝑙 − 𝐸𝑓𝑒𝑐𝑡

𝑯𝒐𝒔𝒕 𝑷𝑪

𝑪𝒐𝒏𝒕𝒓𝒐𝒍 𝑺𝒚𝒔𝒕𝒆𝒎

Fig. 7: Diagram of the experimental implementation.
The experimental results presented in Fig.8 show that the
overshot is increased as the delay is reduced. This is due to the
derivative implicit in (7)-(8) [12]. For example, Fig.8 shows
Fig. 8: Experimental Results for 50% single-phase voltage
dip: a) Voltages ABC , b)Voltage αβ+, c)Voltage αβ-, d)
Frequency PLLs

Fig. 9: Experimental Results for 50% two-phase voltage dip:
a) Voltage ABC, b)Frequency PLLs
VI. C ONCLUSION
A novel PLL structure based on the FDSC algorithm has
been proposed as a frequency estimator for unbalance grid-
voltage conditions. The proposed FDSC-PLL has been tested
for single-phase and two-phase grid-voltage faults, and it
has been compared with state-of-the-art algorithms such as
DSOGI-PLL and DSC-PLL, with good performance and faster
convergence. However, as anticipated by smaller values of
θd imply more noise and overshoot. Therefore, a trade-off
between noise, overshoot and delay should be considered
according to the application.
[6] F. Blaabjerg, R. Teodorescu, M. Liserre, and A. Timbus, “Overview
of Control and Grid Synchronization for Distributed Power
Generation Systems,” IEEE Transactions on Industrial Electronics,
vol. 53, no. 5, pp. 1398–1409, oct 2006. [Online]. Available:
http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1705631
[7] Sang-Joon Lee, Jun-Koo Kang, and Seung-Ki Sul, “A new phase
detecting method for power conversion systems considering distorted
conditions in power system,” in Conference Record of the 1999 IEEE
Industry Applications Conference. Thirty-Forth IAS Annual Meeting
(Cat. No.99CH36370), vol. 4. IEEE, pp. 2167–2172. [Online].
Available: http://ieeexplore.ieee.org/document/798754/
[8] S. Eren, M. Karimi-Ghartemani, and A. Bakhshai, “Enhancing the three-
phase synchronous reference frame PLL to remove unbalance and har-
monic errors,” IECON Proceedings (Industrial Electronics Conference),
pp. 437–441, 2009.
[9] V. Kaura and V. Blasko, “Operation of a phase locked loop system
under distorted utility conditions,” in IEEE Transactions on Industry
Applications, vol. 33, no. 1. IEEE, 1997, pp. 58–63. [Online].
Available: http://ieeexplore.ieee.org/document/500517/
[10] P. Rodrı́guez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos, and
D. Boroyevich, “Double synchronous reference frame PLL for power
converters control,” in IEEE Transactions on Power Electronics,
vol. 22, no. 2. IEEE, 2007, pp. 584–592. [Online]. Available:
http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1581815
[11] Y. F. Wang, “Fast Harmonic Detection based on Cascaded Delayed
Signal Cancellation PLL,” Computer Engineering, vol. 26, no. 7, pp.
1094–1101, 2011.
[12] R. Cardenas, M. Diaz, F. Rojas, and J. Clare, “Fast Convergence Delayed
Signal Cancellation Method for Sequence Component Separation,” IEEE
Transactions on Power Delivery, vol. 30, no. 4, pp. 2055–2057, aug
2015. [Online]. Available: http://ieeexplore.ieee.org/document/6963423/

ACKNOWLEDGMENT
The support of University of Santiago of Chile through
DICYT Projects 091813DD and 091813DD-RED is kindly
acknowledged. The support provided by Fondecyt Project
1180879 and Basal Project F B0008 is kindly acknowledged.

R EFERENCES
[1] N. Hoffmann, R. Lohde, M. Fischer, F. W. Fuchs, L. Asiminoaei, and
P. B. Thøgersen, “A review on fundamental grid-voltage detection meth-
ods under highly distorted conditions in distributed power-generation
networks,” IEEE Energy Conversion Congress and Exposition: Energy
Conversion Innovation for a Clean Energy Future, ECCE 2011, Pro-
ceedings, pp. 3045–3052, 2011.
[2] P. Rodriguez, A. Luna, M. Ciobotaru, R. Teodorescu, and F. Blaabjerg,
“Advanced grid synchronization system for power converters under
unbalanced and distorted operating conditions,” IECON Proceedings
(Industrial Electronics Conference), no. 2, pp. 5173–5178, 2006.
[3] M. Dı́az, R. Cárdenas, P. Wheeler, J. Clare, and F. Rojas,
“Resonant control system for low-voltage ride-through in wind
energy conversion systems,” IET Power Electronics, vol. 9,
no. 6, pp. 1297–1305, may 2016. [Online]. Available: http://digital-
library.theiet.org/content/journals/10.1049/iet-pel.2015.0488
[4] F. Iov, A. D. Hansen, P. Sørensen, and N. A. Cutululis, “Mapping of
grid faults and grid codes,” Tech. Rep. July, 2007. [Online]. Available:
http://orbit.dtu.dk/files/7703139/ris r 1617.pdf
[5] M. Diaz and R. Cardenas, “Analysis of synchronous and stationary
reference frame control strategies to fulfill LVRT requirements
in Wind Energy Conversion Systems,” in 2014 9th International
Conference on Ecological Vehicles and Renewable Energies,
EVER 2014. IEEE, mar 2014, pp. 1–8. [Online]. Available:
http://ieeexplore.ieee.org/articleDetails.jsp?arnumber=6844121

View publication stats