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→ Semiconductor Current: The current flow in an intrinsic semiconductor is influenced by the density of
energy states which in turn influences the electron density in the conduction band. This current is
highly temperature dependent.
→ A doped semiconductor behaves like a resistor. The resistance of doped semiconductor is known as
“bulk resistance” and it decreases with doping concentration.
→ In the extrinsic semiconductor, the number of holes is not equal to number of electrons. In n‐type
semiconductor density of holes and in p‐type density of electrons decreases due to doping. In N‐type
semiconductor the density of holes is less than that of electrons and in P‐type density of holes is greater
ni2 n2
than that of electrons. np = ni2 , n ≈ N d and p ≈ N a ⇒ p = and n = i .
Nd Na
→ Law of mass action: For a given material, the product of electron and hole concentrations is constant at
a given temperature. If impurity is added to increase n, there will be corresponding decrease in p, so
that the product np remains constant. This is known as law of mass action i.e., nc nh = np = constt .
→ The minimum energy required to break a covalent bond and to remove an electron from the valance
band to conduction band is equal to forbidden energy gap which is 0.72eV for Ge and 1.1eV for Si. At
room temperature 1 or 2 electrons out of 108 may acquire this minimum energy in the case of Ge. But as
Ge crystal contains 1023 atoms/cc so quite a large number of free electrons will be available at room
temperature.
→ Semiconductor has total conductivity because of motion of the free electrons in the conduction band
and motion of the holes in the valance band. However, in a conductor, current flows only due to the
motion of free electrons in the conduction band.
→ The maximum effect of the interatomic interactions is on the valance electrons hence, the energy bands
formed by their energy levels are the widest i.e the valance band is wider than the conduction band.
→ For Si EG (T) = 1.21 − 3.6 × 10−4 T and for Ge EG (T) = 0.785 − 2.23 × 10−4 T
→ Silicon carbide (EG = 3eV) is used as semiconductor, however it is a dielectric.
→ In a crystal an electron travels an average distance ≈10‐8m before it makes a collision and loses a large
amount of the energy which it acquires from an applied electric field. If an electric field E imparts 6eV of
6
energy to an electron the electric field required is given by eE × 10−8 = 6 ⇒ E = ≈ 4 × 108 V / m
1.6 × 10−8
→ In an intrinsic semiconductor, the allowed energy levels are only either in the valance band or in the
conduction band and their presence in the forbidden band is ruled out. But, because of the impurity
atoms, additional allowed energy levels appear in the energy spectrum in the forbidden band and at
very small energy below the conduction band. In Ge, the energy of these new discrete allowed energy
levels is only 0.001eV (0.05eV in Si) below the conduction band. This is the reason why at room
temperature all fifth electrons of the donor are raised into the conduction band.
→ Silicon is preferred over Germanium because the leakage current in Si is less than that of Ge.
→ On increasing the temperature of an extrinsic semiconductor, concentration of minority charge carrier
increases and ultimately at critical temperature the number of holes and electrons becomes equal. Thus
extrinsic semiconductor becomes intrinsic semiconductor. Tc = 850C for Ge, Tc = 2000C for Si.
→ A semiconductor which is electrically neutral has equal amounts of positive and negative charges.
→ Conduction electrons have more mobility than holes because they need less energy to move them.
→ In extrinsic semiconductor the concentration of minority charge carriers depends upon temperature of
the material.
Density of electrons in conduction band and holes in valance band
3/2 3/2
⎛ 2π me* kBT ⎞ ⎛ E − Ec ⎞ ⎛ 2π mh* kBT ⎞ ⎛ E − EF ⎞
nc = n = 2⎜ ⎟ exp ⎜ F ⎟ and nh = p = 2⎜ ⎟ exp ⎜ v ⎟
⎝ h2 ⎠ ⎝ k BT ⎠ ⎝ h2 ⎠ ⎝ k BT ⎠
⎛ Ec + Ev ⎞ 3 ⎛ mh* ⎞ Ec + Ev
And Fermi level is E F = ⎜ ⎟ + kBT log ⎜ * ⎟ if mh = me , then E F =
* *
⎝ 2 ⎠ 2 m
⎝ e⎠ 2
When mh* = me* , then the Fermi level lies exactly half way between the top of valance band and bottom of
In N‐type semiconductor Fermi level lies just below the conduction band however in P‐type semiconductor
Nc N
it lies just above the valence band. E F = E c − kT log e , and E F = E V + kT log e V .
Nd Na
PN junction and Depletion Region
When a PN junction is formed, free electrons and holes migrate across the junction by the process of
diffusion. In this process the electrons crossing the junction from N‐region into the P‐region recombine
with holes in the P‐region very close to the junction and form negative ions. Similarly the holes crossing the
junction from the P‐region into N‐region recombine with electrons in the N‐region very close to the
junction and form positive ions. Consequently mobile charges are neutralized over a very small region of
width 10‐4 cm to 10‐6 cm around the junction. Since this region does not contain mobile charge carriers, it is
called the depletion region, the space charge region or the transition region. In this region the acceptor
atoms in the P‐region becomes negative ions and the donor atoms in the N‐region becomes positive ions.
Thus, an internal potential difference V0 is produced across the junction which is called internal potential
kT ⎛N N ⎞ ⎫
V0 = log e ⎜ a 2 d ⎟ V0 = 0.3V for Ge ⎪
barrier and given by q ⎝ ni ⎠ ⎬
⎪
V0 = 0.7V for Si ⎭
The function of internal potential barrier is to prevent the further migration of electrons and holes. Outside
the depletion region the P and N regions are still electrically neutral. Only inside the depletion region, there
is immobile positive charge on N‐side and immobile negative charge on P‐side.
Transition or space charge capacitance (CT): When a p‐n junction is reversed biased, there exists a
capacitance across it due to the presence of the immobile charges on the two sides of the junction. This
referred to as barrier or transition or space charge capacitance. It decreases with increasing reverse voltage
because under reverse bias the width of depletion region increases which in turn decreases the junction
εA
capacitance CT = where A is the junction cross sectional area and w is the width of the depletion region.
W
This property of PN junction is used in the construction of special type of diodes called varactors diodes. The
value of CT is in PF.
There is another capacitance which is much larger than the transition capacitance CT and is effective when
the junction is forward biased. This capacitance is referred to as diffusion or charge storage capacitance CD
and is proportional to the forward current. It is caused by the space charge stored on both sides of the
junction outside the space charge region. It is defined as the rate of change of injected charge with voltage
dq τ eI
and is given by C D = = where τ is the mean life time of minority carriers. C D > CT always.
dV η kT
Effect of Temperature: On increasing the temperature of the junction the avalanche breakdown
voltage increases.
Effect of Temperature: The magnitude of the Zener breakdown voltage decreases as junction
temperature increases.
→ For an ideal diode potential barrier and forward resistance should be zero.
→ The forward voltage below which forward current is zero and just above which current starts
increasing rapidly is called cutin, threshold, offset or break point voltage.
→ In an unbiased PN junction the junction current at equilibrium is zero because the numbers of majority
and minority charge carriers crossing the junction are equal.
→ In an unbiased PN junction the width of the zone is dependent on the densities of the dopants.
→ The dominant mechanism for the motion of charge carriers in forward and reverse biased silicon
junction are diffusion in forward and drift in reverse bias.
→ PIV is the maximum reverse voltage that can be applied to the PN junction without damaging it. If the
reverse voltage across the junction exceeds its PIV, the junction may be destroyed due to the excessive
heat. PIV is of particular importance in rectifier service.
→ The current in the forward biased PN junction is limited by bulk resistance of the crystal and the
resistance of the ohmic contacts of the P‐ and N‐regions. When the forward voltage becomes greater
than the potential barrier, the current is governed by the ohmic contact resistance and the crystal bulk
resistance. Thus, the current/voltage characteristic becomes approximately a straight line.
→ Forward biased diode behaves as short circuit and the reverse biased diode as open circuit.
→ Barrier potential decreases with increase in the temperature under forward bias as ΔV = −2.5V /0 C .
Because of this change in the barrier potential, the cutin voltage decreases with increase in the
temperature. In reverse biasing the available leakage current depends upon the temperature. For Ge
diode, the leakage current becomes double foe every 100C rise in the temperature while for Si diodes; it
becomes double for every 60C rise in temperature.
→ In an unbiased PN junction, the junction current at equilibrium is zero because then the number of
majority carriers crossing the junction equals the number of minority carriers crossing the junction.
→ In a PN junction not connected in any circuit there is an electric field at the junction directed from N‐
type side to P‐type side.
→ If the wavelength of the electromagnetic radiation is 1,000 nm, find the band gap energy.
12,400 12,400 12,400 12,400
λ = = ⇒ EG = =
E 2 − E1 EG λ 1000
The PIN Diode: A PIN diode is a three region junction diode. It has a high resistivity intrinsic
semiconductor layer sandwiched between two highly doped P and N region. When reverse biased, it acts
like an almost constant capacitance and when forward biased it behaves as a variable resistor. The forward
resistance of the intrinsic region decreases with increasing current. Since its
forward resistance can be changed by varying the bias, it can be used as a modulating
device for AC signals. It is used in microwave switching applications.
→ The high resistance of I region in PIN diode decreases the capacitance. It allows the diode a faster
response time. PIN diode is a three region reverse biased junction diode. High resistance increases the
break down voltage. It is used for detecting laser pulses, in ultrafast switching and logic circuits, as
phase shifter. It is enhances the electron‐hole pair generation and reduces the transit time.
→ PIN diodes acts as ordinary diode up to 100 MHz and above this frequency it ceases to rectify because of
the charge stored in and transit time across the intrinsic region. At microwave frequencies, the diode
behaves as variable frequencies.
Diodes Symbols:
Laser Diodes: Laser action can be achieved in a PN
junction formed by two doped gallium arsenide layers.
The junction is forward biased and the recombination
process produces light as in the LED (incoherent). Above
a certain current threshold the photons moving parallel
to the junction can stimulate emission and initiate laser action.
Light Emitting Diode Structure: LEDs are PN junction devices constructed of gallium arsenide (GaAs),
gallium arsenide phosphide (GaAsP), or gallium phosphide (GaP). Silicon and germanium are not
suitable because those junctions produce heat and no appreciable IR or visible light. The junction in an LED
is forward biased and when electrons cross the junction from the n‐ to the p‐type material, the electron‐
hole recombination process produces some photons in
the IR or visible in a process called electro‐
luminescence. An exposed semiconductor surface can
then emit light.
When a PN junction is forward biased, annihilation of
holes and electrons takes place close to the junction
and some energy is released in the junction. In Ge and Si, this energy is in the form of heat. But it has been
observed that in some other semiconductors (GaAs) the energy is released in the form of radiation. This
phenomenon is known as electro‐luminescence and the diode based on this phenomenon is called light
emitting diode. They are used in pilot lamps, display devices etc. Infrared LED is a potential source for
optical fiber communication.
Electroluminescence in LEDs:
When the applied forward voltage on the diode of the
LED drives the electrons and holes into the active
region between the n‐type and p‐type material, the
energy can be converted into infrared or visible
photons. This implies that the electron‐hole pair drops into a more stable bound state, releasing energy on
the order of electron volts by emission of a photon. The red extreme of the visible spectrum, 700 nm,
requires an energy release of 1.77 eV to provide the quantum energy of the photon. At the other extreme,
400 nm in the violet, 3.1 eV is required.
Tunnel Diode: A conventional P‐N junction diode has an impurity concentration of about 1 part in 108.
With this order of doping, the width of the depletion layer is of the order of 5 microns and the potential
barrier so produced restrains the flow of holes from P to N region and electron from N to P region. If the
concentration of impurity atoms is greatly increased (about 1 part in 103), then the depletion layer becomes
very thin (100A) and the device characteristics are completely changed. Such a diode is called Tunnel diode.
The tunnel diode has a region in its voltage current characteristic where the current decreases with
increased forward voltage, known as its negative resistance region. This characteristic makes the tunnel
diode useful in oscillators and as a microwave amplifier. The unijunction transistor has a similar oscillator
application.
→ Tunnel diode was first manufactured by Dr. Leo Esaki in 1958. If the depletion layer in a PN junction is
very thin, the electrons could penetrate the junction and thus could pass from one side of the depletion
layer to the other with less energy. In tunnel diode the width of the depletion layer is reduced by
increasing the concentration of impurity atoms.
→ Tunnel diode shows a negative resistance for part of its characteristic
and therefore, it is also known as negative resistance device.
→ Tunnel diodes are not good rectifiers, as they have relatively high
leakage current when reverse‐biased.
→ The increase in current from 0 to its peak value in tunnel diode under forward bias is due to tunneling
phenomenon. As the forward bias voltage is further increased beyond VP it reduces the electric field
strength because depletion region becomes less well defined due to diffusion of carriers across the PN
junction. Therefore, tunneling current decreases. Thus, current decreases with increase in applied
voltage between the peak point and the Valley point. If forward voltage is increased beyond VV, the
tunneling affects ceases and current rises because of injection current as in any ordinary junction diode.
→ Tunnel diode, having a negative resistance region, will generate power if operated over this region.
Therefore, a tunnel diode can function as an amplifier, an oscillator or a relaxation oscillator. Tunneling
phenomenon takes place at the speed of light, so, it is used as switching device in computers. Its
switching speed is of the order of nanosecond. Due to its extremely small capacitance and inductance it
is used as microwave oscillator at frequency of about 10 GHz.
→ In varactor diode or variable voltage capacitor (VVC) the capacitance varies with the reverse voltage as
k
C ∝ VR− n or C = if n = 0.5
VR
Varactor Applications:
(i) Automatic frequency control device (ii) Parametric amplifiers (iii) FM modulators
(iv) Harmonic generators (v) Adjustable band pass filter
Schottky diode: A metal‐semiconductor junction diode is called Schottky diode or hot carrier diode. It
consists of a junction between a metal (like platinum, gold, silver etc) and an N‐type doped silicon
semiconductor. Silicon is used because it is easier to fabricate. It has no depletion layer.
Metal‐semiconductor junction is unidirectional and behaves as diode. Schottky
diode has only electrons as majority charge carriers on both sides of the
junction. In Schottky diode, no holes are present in the metal and also there is no depletion layer or charge
storage. Hence Schottky diodes are faster than ordinary diodes. Schottky diode can easily rectify signals of
frequencies exceeding 300 MHz. They are used in high frequency and fast digital circuits. They used in
clipping and clamping circuits.
Optoelectronics: The branch of physics which combines optics with electronics is called s based on
optoelectronics can be divided into two broad categories.
(i) The devices which convert electrical energy into optical radiations are known as emitters such as
LED and Laser diode.
(ii) The devices that convert optical radiations into electrical energy are called photovoltaic devices and
solar cells.
Photoconduction in semiconductors: When radiation falls on a semiconductor, some absorption of light
take place by it and consequently its conductivity increases. This effect is called Photoconductive effect.
When the light of suitable wavelength falls upon a semi conductor and h ν > E g (band gap) then sharp rise in
absorption takes place and some covalent bonds are break to produce electron‐hole pairs. These created
charge carriers decrease the resistance or increase the conductivity of the material. Hence such a material
is called Photo‐conductor of Photo‐resistor.
Cutoff wavelength: For photo‐conduction to take place in an intrinsic semi‐conductor, the minimum
energy of a photon should be equal to the forbidden gap energy.
hc 1.24μ 12400 A
hν = E g (eV ) or λc = = =
E g (eV ) Eg Eg
For Ge, at room temperature, Eg = 0.72ev and therefore, λc = 1.72μm . For Si, Eg = 1.1ev and therefore,
λc = 1.13μm .
Thus, the longest wavelength which can produce photocurrent in Pure Si is about 1.1um and for Ge is 1.7
μm, both of these fall in infrared region. This long wavelength limit can be increased by adding impurities to
the semi conduction material.
Photoconduction Cells: The devices through which light energy can be converted to electrical energy are
called photo‐electric cells. Three different types of photo‐electric cells are:
(i) Photo emissive Cells.
(ii) Photovoltaic cells.
(iii) Photo‐conductive cells.
Photo conductive cell: Photo‐conductive cells are based on the principle that the electrical resistance of
semiconductor materials like selenium, lead sulphide etc decreases when they are exposed to radiation.
Therefore, if such a substance is inserted in the circuit and light is allowed to fall on it, its electrical
resistance will change. Consequently, they will be change of current in the circuit. Commonly used photo
conductive cell is cadmium sulphide cell. They are use in Camera, exposure settings, in aircraft and missile
tracking system in burglar alarm.
Photodiode: A photodiode is essentially a reverse biased PN junction diode which is designed to
respond to photon absorption. When light is allowed to fall on a reverse biased P‐N junction diode,
additional electron‐hole pairs are generated in both P and N regions, which produce very large change in
minority carrier concentration and hence increases the reverse current. The current through the diode
varies almost linearly with the light flux. Hence light can be detected using a reverse biased P‐N junction
diode known as photo diode.
Photovoltaic Cells: When a pair of electrodes is immersed in an electrolyte and light is allowed to incident
on one of them, a potential difference is created between the electrodes. This phenomenon is called photo‐
voltaic effect. Devices based on this effect are called photo‐voltaic cells. Thus, photovoltaic cells are the
devices in which light energy is used to create a potential difference. This potential difference is directly
proportional to the frequency and intensity of incident light.
→ Photo transistor has large base‐collector junction as compared to conventional BJT.
→ MIIM diode: The metalinsulatorinsulatormetal (MIIM) diode is a quantum tunneling device, not
based on semiconductors.
→ Diode Current‐Voltage Equation: ID = IS ( eqV /ηk t ‐ 1) where ID = Diode current in amps, IS = Saturation
D B
current in amps (typically 1 x 10‐12 amps), e = Euler’s constant (~ 2.718281828), q = charge of electron
(1.6 x 10‐19 coulombs), VD = Voltage applied across diode in volts, η = "Nonideality" or "emission"
coefficient (typically between 1 and 2), T = Junction temperature in Kelvin and k = Boltzmann’s constant
(1.38 x 10‐23)
The term kT/q describes the voltage produced within the PN junction due to the action of
temperature, and is called the thermal voltage, or Vt of the junction. At room temperature, this is
about 26 millivolts.
Reverse recovery time: The amount of time taken by a diode to turn off when the voltage across it
alternates from forward‐bias to reverse‐bias polarity. For a typical rectifier diode, reverse recovery time is
in the range of tens of microseconds; for a fast switching diode, it may only be a few nanoseconds.
Snap diode: The snap diode, also known as the step recovery diode is designed for use in high ratio
frequency multipliers up to 20 GHz. When the diode is forward biased, charge is stored in the PN junction.
This charge is drawn out as the diode is reverse biased. The diode looks like a low impedance current
source during forward bias. When reverse bias is applied it still looks like a low impedance source until all
the charge is withdrawn. It then snaps to a high impedance state causing a voltage impulse, rich in
harmonics. An application is a comb generator, a generator of many harmonics.
IMPATT diode: The IMPATT diode is a two terminal PN junction device operating at reverse bias. The
IMPact Avalanche Transit Time diode is a high power radio frequency (RF) generator operating from 3 to
100 GHz.
Gunn diode: The production of periodic fluctuations in the current passed by the material under high
electric field stress is called Gunn effect. GaAS, InP, CaTe and InAS exhibit this property. This effect is only
found in N‐type materials so it is associated with electrons and not with holes.
Diode Clamper
A diode can be used to clamp one side of a sinusoidal signal to near zero.
Peak detector: A peak detector is a series connection
of a diode and a capacitor outputting a DC voltage
equal to the peak value of the applied AC signal.
Voltage multipliers: A voltage multiplier is a
specialized rectifier circuit producing an output which
is theoretically an integer times the AC peak input, for example, 2, 3, or 4 times the AC peak input. Thus, it is
possible to get 200 VDC from a 100 V peak AC source using a doubler, 400 VDC from a quadrupler. A
voltage doubler application is a DC power supply capable of using either a 240 VAC or 120 VAC source.
→ The most basic multiplier is a half‐wave doubler. The full‐wave double is a superior circuit as a doubler.
A tripler is a half‐wave doubler and a conventional rectifier stage (peak detector). A quadrupler is a
pair of half‐wave doublers. A long string of half‐wave doublers is known as a Cockcroft‐Walton
multiplier.
Half Wave Rectifier:
1 2π 1 ⎡ π 2π I
(i) Average DC current Idc = ∫ I d(ωt ) = ∫ Im sin ωt d(ωt ) + ∫ 0. d(ωt )⎤ = m
2π 0 ⎢
2π ⎣ 0 π ⎥
⎦ π
1/2
⎡1 2π ⎤ Im
(ii) RMS value of current: Irms = ⎢
⎣ 2π
∫0
I 2d(ωt )⎥
⎦
=
2
(iv) Ripple factor: Ripple factor in a rectifier circuit is the measure of the AC components in the output.
′
rmsvalue of all AC components Irms I2
γ= = = rms
2
− 1 because Irms
2
′2 + Idc
= Irms 2
(v) PIV: The maximum reverse voltage across the diode is called PIV. In HWR without filter the PIV
across the diode is the maximum transformer voltage Vm. Thus, PIV=Vm
(vi) The frequency of the rectified output or pulses is the same as that of the input voltage. According to
the Fourier analysis of the output voltage waveform of the HWR is given by
Vm ⎡ π 2 2 2 ⎤ ω
Vo = ⎢1 + Sinωt − Cos2ωt − Cos 4ωt − Cos6ωt ......⎥ The frequency of the first AC
π ⎣ 2 1×3 3× 5 5× 7 ⎦ 2π
component is equal to that of the supply voltage.
Full Wave Rectifier:
1 2π 1 ⎡ π 2π 2I
∫ Im sin ωt d(ωt ) + ∫ Im sin(ωt − π ) d(ωt )⎤ = m
2π ⎣⎢ ∫0
(i) Average DC current Idc = I d(ωt ) =
2π 0 π ⎦⎥ π
1/2 1/2
⎡1 2π ⎤ ⎡1 π 2π ⎤ Im
(ii) RMS value of current: Irms = ⎢
⎣ 2π
∫0
I 2d(ωt )⎥
⎦
=⎢
⎣ 2π
∫0
Im2 sin ωt d(ωt ) + ∫ Im2 sin(ωt − π )d(ωt )⎥
π
⎦
=
2
Idc2 RL
(v) Rectifier efficiency: η = DC power supplied tothe load = =
8 8
= 2 = 81.2%
total input AC power I (RL + rf )
2
⎛ r ⎞ π
rms
π 2 ⎜1 + f ⎟
⎝ RL ⎠
(vi) Ripple factor: Ripple factor in a rectifier circuit is the measure of the AC components in the output.
′
rmsvalue of all AC components Irms I2
γ= = = rms
2
− 1 because Irms
2
′2 + Idc2
= Irms
average of DC components Idc Idc
Irms π I2
= so, γ = rms − 1 = 0.482
Idc 2 2 Idc2
′ < Idc
⇒ γ < 1 or Irms
(vii) PIV: The maximum reverse voltage across the diode is called PIV. In HWR without filter the PIV
across the diode is the maximum transformer voltage Vm. Thus, PIV=2Vm
(viii) The frequency of the rectified output or pulses is double as that of the input voltage. According
to the Fourier analysis of the output voltage waveform of the HWR is given by
2Vm ⎡ 2 2 2 ⎤
Vo = ⎢1− Cos2ωt − Cos 4ωt − Cos6ωt ......⎥ In this case the frequency of the first AC
π ⎣ 1×3 3× 5 5× 7 ⎦
component is two times the supply voltage.
→ In a full wave rectifier employing shunt capacitor filter, the diode current flows in short pulses.
→ A regulated power supply consists of (i) a power transformer (ii) a full wave rectifier (iii) a smoothing
filter (iv) a voltage regulator circuit.
→ A commercial power supply has a voltage regulation of 1%.
Filter Circuits: In order to remove the AC components from the output voltage of the rectifier so that a
steady DC output voltage is obtained, a smoothing filter is connected between the rectifier and the load.
(i) Capacitor or shunt capacitor filter: In this filter circuit a capacitor
C is connected parallel to the load as shown in figure. The reactance
1
of the capacitor is very small as compared to the load RL at
ωC
frequency of AC and is infinite for DC. Thus, the AC components find a low reactance path through
the capacitor and mostly bypassed however, the DC components are blocked. Ripple
1
γ= this shows that ripple varies inversely with load resistance RL and capacitance C. the
4 3 f RLC
ripple factor can be reduced by either increasing C or by increasing load resistance.
(ii) Series inductor of choke filter: When an inductor coil of resistance R and inductance L is
connected in series between the rectifier and load then, it offers high
ripple factor will decrease when RL is decreased and L is increased.
(iii) The LSection or inductor or choke input filter: When an
inductor of inductance L is connected in series with the output of the
rectifier and the capacitor C is connected across the load as shown
in figure, the circuit is called L‐section filter. Since the first component of the filter circuit is the
choke hence, it is also called choke input filter.
In this filter, the series inductor L passes the DC components from the rectifier output but
introduces a high reactance path for AC. The AC components that remain after passing through L are
by passed by the shunt capacitor C which offers a low reactance to them but an infinite resistance to
DC. Thus, the output across the load possesses less AC components or the lower ripple factor. The
1
ripple factor of the rectifier with this filter is given by γ = . Thus, the ripple factor is
6 2 ω 2 LC
independent of the load resistance and decreasing with increasing value of L and C. Critical value of
R
the filter input choke is LC =
942
(ix) The πsection or capacitor input filter: When higher
output voltage at light load is desired, an input capacitor is
added to L‐section filter to form a π‐section filter. The use of
a π‐section filter provides an output voltage that approaches the peak value of the AC potential of
the source, the ripple being very small.
2
The ripple factor of the rectifier with this filter is given by γ = . Thus, if C1 and C2 are in
RL C1 C2 L(4π f )3
5700
microfarad, L in Henrys, RL in ohms and f = 50 Hz, then γ = the ripple factor is independent of the
RL C 1 C 2 L
load resistance and decreasing with increasing value of L and C.
Positive and Negative Series Clippers: The circuit which clipped‐off the positive portion of the input
waveform is called positive clipper as shown in figure 1. In this circuit the diode remains in reverse biased
for the positive half cycle of the input and in forward biased for the negative half cycle. The circuit which
clipped‐off the negative portion of the input waveform is called positive clipper as shown in figure 2. In this
circuit the diode remains in reverse biased for the negative half cycle of the input and in forward biased for
the positive half cycle.
Biased Series Positive and Negative Clippers: Figures 3 and 4 show the relevant circuit along with the
input and output waveforms of biased series positive and negative clippers respectively.
Positive parallel and Negative parallel Clippers: The circuits of positive and negative parallel clippers
are shown in figure 5 and 6 respectively. In positive parallel clipper the diode is forward biased during +ive
half cycle and reverse biased during –ive half cycle. On the other hand in negative parallel clipper the diode
is reverse biased during +ive half cycle and forward biased during –ive half cycle. When diode is forward it
conducts and maximum potential drops across resistance R and so output becomes zero. On the other hand
when diode is reverse biased it does not conduct and output becomes equal to signal voltage.
Bipolar Junction Transistor
→ Collector is made wider than emitter and base because it increases the junction width which in turn
decreases the junction capacitance and hence increases the breakdown voltage.
→ During transistor operation, much heat is produced at the collector junction therefore collector is
made wider to dissipate the heat. A large collector area also prevents excessive recombination of holes
and electrons in the base.
→ As the input circuit has low resistance, therefore a small change in signal voltage causes an appreciable
change in emitter current. This causes almost the same change in the collector current because the
collector circuit is reverse‐biased and has high resistance. Therefore the collector voltage has little
effect on the collector current.
→ The saturation [Both Junction are forward biased] and cut‐off modes [Both are reverse biased] are
used in the switching action of a transistor and in active mode transistor works as an amplifier. In
inverse mode transistors are not operated.
→ If a transistor were operated with emitter and collector interchanged then base current will decrease.
→ The current gain of a CB amplifier is less than 1 and the voltage gain is high. Hence the power gain is
not high.
→ CC amplifier is called emitter follower, because its voltage gain is little less than 1. It means that a
change in the base voltage produces an equal change in the output voltage across the load i.e. the
emitter follows the input signal.
→ Coordinates of Q‐point are IB and IC or IC and VCE.
→ For drawing d. c. equivalent circuit of a transistor, all a. c. sources are treated as short and capacitance
as open.
→ In transistor amplifier input impedance should be high.
→ The voltage gain of a cascade amplifier is equal to the product of the gains of individual stages.
β α
Relation Between α and β: α = ⇒ α < 1 and β = ⇒ β > 1 , IC = β I B + (1 + β ) ICBO or ICEO = (1 + β ) ICBO .
β +1 α +1
Thus, the collector‐emitter leakage current in CE‐mode is (1+β) times larger than that in CB‐mode. Leakage
current is highly temperature dependent and increases with increase in temperature.
Hybrid parameters: V1 = h11 I 1 + h12V 2 , I 2 = h21 I 1 + h22V 2
V1 I2 V1
h11 = = hi = input impedance, h21 = = h f = forward current gain, h12 = = hr = reverse voltage
I1 V2 =0
I1 V2 =0
V2 I 1 =0
I2
ration, h22 = = ho = output admittance
V2 I 1 =0
Positive and Negative feedback
A
→ Positive feedback: Increases the gain, distortion and decreases the stability. A f =
1− βA
→ Negative feedback: Decreases the gain, distortion, noise, output impedance and increases the stability,
A
band width, input impedance and range of uniform amplification. A f = .
1+ βA
→ Negative feedback decreases the lower cut off frequency but increases the upper cut off frequency. Thus
negative feedback increases the band width which is achieved at the cost of reduction in the gain of the
amplifier.
→ Darlington pair is a three terminal device with very high current gain, has a very high input impedance
and also has a very low output impedance.
Class A power amplifier: In class A amplifier, the current flows through the active device for the whole of
the input cycle i. e. angle of conduction is 3600.
Class B power amplifier: In class B amplifier, the collector current flows only during positive half cycle of
the input signal i. e. angle of conduction is 1800.
Class AB power amplifier: This operation is between class A and class B. Here collector current flows for
more than half cycle of input but less than the whole cycle.
Class C power amplifier: In class C amplifier the collector current flows for less than half a cycle of the
input signal.
FET Versus BJT
FET exhibits high input resistance (100 MΩ‐JFET, and 1010 to 1015 Ω in MOSFET) because of it, the input
current is generally negligible. So in a FET the output current and the output voltage are controlled by the
input voltage (Electric field). Thus FET is a voltage‐ controlled device while BJT is current controlled device.
FET is less noisy than BJT because conduction is through n‐type or p‐type semi conductor material. FET has
better thermal stability.
Principle of operation: The thickness and hence the resistance of a conducting channel of a semi
conductor material can be regulated by the application of potential difference at its input terminals and by
the transverse electric field across the reverse biased PN junction formed on its surface.
NChannel JFET Operation
When VGS = 0 and VDS = 0, the depletion region around the junctions remains uniform.
When VDS = 0 and VGS decreased from zero: In this case both PN junctions are reverse biased and hence
the thickness of the depletion region increases. As VGS is decreased the reverse bias‐voltage across the
junction increases. Hence the thickness of the depletion regions will increase till the two depletion regions
make contact with each other. In this condition the channel is said to be cut‐off and value of VGS is called
Cut‐off voltage.
When VGS = 0 and VDS increased: When source is forward then majority
carriers i. e. electrons flow through the channel from S
to D and therefore conventional drain current ID flows
through channel from D to S. Current ID depends.
(i) The number of majority carriers i. e.
conductivity of the channel
(ii) The length of the channel
(iii) Cross‐sectional area A of the channel
(iv) The magnitude of the applied voltage VDS.
Thus channel acts as resistor of
ρl
resistance R =
A
VDS AVDS
ID = = .
R ρl
Because of this resistance of the channel and the applied voltage VDS, there is a gradual increase of positive
potential along the channel as we go from S to D. Thus, the
reverse voltage across PN junctions increases as we go from
S to D and hence the thickness of the depletion region also
increases. Therefore, the channel is wedge‐shaped. As VDS is
increased the cross‐sectional area of the channel will be
reduced. At certain value VP of VDS, the cross‐sectional area at B becomes minimum and the channel is said
to pinched‐off, voltage VP is called pinched‐off voltage.
→ Above the pinched‐off voltage, at a constant value of VDS, ID increases with an increase of VGS. Hence a
JFET is suitable for use as a voltage amplifier.
2
⎛ V ⎞ eN eN
→ I DS = I DSS ⎜ 1 − GS ⎟ ,VP = D a2 ( N − Channel ), VP = A a2 ( P − Channel ) a → half the channel width
⎝ VP ⎠ 2ε 2ε
ΔVDS ΔVDS ΔI D
μ= , rD = , gm =
ΔVGS ID
ΔI D VGS
ΔVGS VDS
→ Tangent to the curve at IDS = IDSS, VGS = 0 will have an intercept at –VP/2 on VGS axis.
→ A JFET behaves as a resistor (Ohmic region), then as a constant current source (Pinched off region) and
finally as a constant voltage source (breakdown region).
→ In MOSFET, substrate is lightly doped and the two highly doped P+ or N+ regions are diffused.
→ In depletion MOSFET, conducting channel exists between drain and source with zero gate bias.
→ The MOSFET which exhibit appreciable channel conductance with zero gate bias are called depletion
MOSFET and those have no channel conductance at zero gate bias are known as enhancement MOSFET.
NChannel Depletion MOSFET: In N‐channel depletion
MOSFET, two highly doped N+ regions are diffused in lightly
doped P‐type substrate. A lightly doped N‐channel is
diffused between source and drain. The length of the
channel is 10‐5 to 2 × 10‐5 m. A thin layer of insulating silicon
dioxide of thickness 10‐7m to 2 × 10‐7m is grown over the
surface. Then a thin layer of metal aluminum is formed over
the layer of SiO2. This metal layer covers the entire channel
region and it forms the gate G. The layer SiO2 acts as a very
good insulator between the surface of the substrate and the
metallic layer. Thus, a parallel plate capacitor is formed in which substrate and metallic layer act as plates
and SiO2 as the dielectric medium.
When VGS = 0 and VDS increased: Then the electrons flow through the channel from S to D and therefore,
conventional drain current flows through the channel from D to S. Since gate G is short‐circuited to the
source, it is at negative potential with respect to the drain. Hence
a positive charge consisting of holes is induced in the channel
through SiO2 layer. The introduction of the positive charge causes
depletion of mobile electrons in the channel. Hence the channel is
wedge‐shaped. Therefore, when VDS increased ID increases and at
a certain value of VDS it becomes practically constant. This value of VDs is called pinch‐off voltage.
When VGS is negative and VDS is increased: The thickness of depletion layer further increases due to
further increase of the induced positive charge.
When VGS is positive and VDS increased: in this case, a negative charge consisting of electrons is induced
in the channel. Thus, the conductivity of the channel
increases and drain current becomes more than that for
VGS = 0. Therefore, with gate at positive potential, the
depletion MOSFET is operated as an enhancement MOSFET.
Enhancement MOSFET:
When VGS = 0 and VDS increased: There is one PN
junction between the source S and the substrate, and other
between the substrate and drain. When D is at a negative
potential with respect to S the drain‐channel PN junction is
reverse biased. Hence the only current which can flow
through this junction is a very small leakage current.
When VDS is negative and VGS is decreased from zero: When the gate
is at negative potential with respect to the source S and the substrate is
connected to the source, the negative charge on G induces an equal
positive charge on the substrate side between the source and the drain
regions. Thus, an electric filed is produced between the source and drain regions. The direction of the field
is perpendicular to the plates of the capacitor. The total induces positive charge consists of holes which are
minority carriers in the N‐type substrate. These holes form an induced P‐type channel between the P‐type
source and the drain regions. In this way the conductivity of the MOSFET is enhance so it name
ENHANCEMENT MOSFET.
→ Although there is no channel in enhancement MOSFET, but still it is called N‐channel or P‐channel
MOSFET. This is because, the thin layer of the substrate touching the metal oxide film and provides
channel for electrons or holes.
→ In FET devices the arrow on the substrate points to the N‐type material and broken vertical line
represents that there is no continuous channel.
→ In enhancement MOSFET, the smallest value of VGS at which the induced channel is formed, so that drain
current ID can flow is called threshold voltage VT.
→ MOSFET utilize the electric field of a capacitor to control the channel current. Depletion MOSFET
conducts normally when VGS = 0 while enhancement MOSFET cut‐off when VGS = 0.
→ The input resistance of FET in the low frequency small region operation is almost infinite.
→ Voltage gain of JFET Av = − μR L /(rd + R L ) = − g mR L
→ A complementary MOSFET (CMOS) is obtained by connecting a p‐channel and an n‐channel MOSFET in
series, with drains tied together and the output is taken at the common drain point. Input is applied at
the common gate terminal formed by connecting the two gates together.
→ Figure of merit of logic circuits = propagation delay time (ns) power (mW)
Operational Amplifiers: An op‐amp is a very high gain differential amplifier with high input impedance
and low output impedance. The typical op‐amp operates with two DC supply voltages‐one positive and
other negative. Op‐amp is basically a difference amplifier whose basic function is to amplify the difference
between two input signals. The advantage of using differential amplifier in OP‐AMP is its rejection
capability of unwanted signals. The basic building block of the analog computer is the operational amplifier.
The Ideal Opamp: Ideal op‐amp has the following characteristics:
(i) Infinite voltage gain
(ii) Infinite input impedance
(iii) Zero output impedance
(iv) Infinite bandwidth, so that any frequency from 0 to ∞ can be amplified without attenuation Zero
(v) Input offset voltage (i.e., exactly zero out if zero in)
(vi) Infinite CMRR, so that the output noise voltage is zero
(vii) Zero drift i .e. characteristics do not drift with temperature.
Inverting opamp: In this mode of operation, the +ve input terminal (non‐inverting) of the amplifier is
grounded and input signal is applied to the inverting (‐ve) through
resistance R1. Rf is the feedback resistor.
Vo Rf
Voltage gain ACL = =−
Vin R1
For equal resistors, it has a gain of ‐1, and is used in digital circuits as an
inverting buffer.
Noninverting opamp: For an ideal op‐amp, the non‐inverting amplifier gain is given by
Rf Vo Rf
Voltage gain Vo = Vin + VR = Vin + Vin ⇒ ACL = =1+
f
R1 Vin R1
Input signal will be integrated properly if the time period T of the signal
is larger than or equal to RC i.e., T ≥ RC
Differentiator: In this circuit, the input resistance is replaced by a capacitor C.
dq d(CVin ) dV dV
I= = = C in so, Vo (t ) = IR2 = −C R2 in Sine → Co sin e , Square → spikes
dt dt dt dt
The input signal will be differentiated properly if the
time period T of the input signal is larger than or equal to
RC i.e., T ≥ RC
⎡ V1 V2 V3 ⎤
Adder amplifier: Vo = −R f ⎢ + + ⎥
⎣ R1 R2 R3 ⎦
Rf
Subtractor: Vo = (V2 − V1 )
R
Comparator:
Input Bias Current: The current flowing into each of the two terminals when they are biased to the same
voltage levels or the average of the currents into the two input terminals with output at zero volts is the
I1 + I2
input bias current. Ibias =
2
Input offset current: The input offset current is the difference of the currents into the two input terminals
with the output at zero volts. Thus, with Vo=0, we have Iio = I1 − I2
Input offset voltage: It is the input voltage which must be applied across the input terminals to obtain zero
output voltage.
Power supply voltage rejection ratio: It is defined as input offset voltage change per volt of supply
ΔVo
voltage change. PSRR =
Vcc
CMRR: The measure of an amplifier to reject common mode signals is called the CMRR. If the differential
gain of the amplifier is Ad and common mode gain is ACM then CMRR = A d / A CM or CMRR = 20log e ( Ad / ACM ) .
ACM = V OCM / V CM where V OCM =output common mode voltage, V CM = input common mode voltage.
Supply Voltage Rejection Ratio: The change in an op‐amp’s input offset voltage Vio caused by variations in
supply voltages is called SVRR i.e., SVRR = ΔV io / ΔV
2π f Vm
Slew rate: SR = V / μs
106
Sample and hold circuits: Figure shows the sample and hold circuit. In this circuit the E‐MOSFET works as
a switch that is controlled by the sample voltage VS, and the capacitor C serves as a storage element. The
signal vin to be sampled is applied to the drain, and sample and hold voltage VS is applied to the gate of the
E‐MOSFET. During the +ive cycle of VS, the E‐MOSFET conducts and acts as a closed switch. This allows
input voltage to charge capacitor C and the voltage across C is the output voltage. On the other hand when
VS is zero, E‐MOSFET is off and acts as open switch. Therefore, the discharge path for the capacitor is only
through op‐amp. Since the input resistance of the op‐amp voltage follower is very high so the voltage across
C is retained. The time period TS of the sample and hold control voltage VS during which the voltage acroos
the C is equal to the input voltage is called sample period. The time period TH of VS during which the
voltage across the capacitor is constant is called hold period.
If voltage across a capacitor
were made to represent the
velocity of an object, the
current through the capacitor
would represent the force
required to accelerate or
decelerate that object, thus
capacitor's capacitance
representing the object's
dV dv
mass: i C = C , F = m .
dt dt
8Where, iC = Instantaneous
current through capacitor, C =
Capacitance in farads, dv/dt=Rate of change of voltage over time, F = Force applied to object, m = Mass of
object, dv/dt= Rate of change of velocity over time
→ In binary number system, a group of four bits is known as nibble and a group of eight bits is known as
byte.
→ In binary notation 0 is used to represent the positive number and 1 is used to represent the negative
number. The 1 at position of MSB indicates that the number is negative and the other bits give its
magnitude.
→ For n‐bit number, the maximum positive number which can be represented in one’s complement
representation is (2n‐1‐1) and the minimum negative number is ‐ (2n‐1‐1).
→ For n‐bit number, the maximum positive number which can be represented in two’s complement
representation is (2n‐1‐1) and the minimum negative number is ‐2n‐1.
→ Gray Code: In gray code each number is differed from the preceding and the succeeding number by a
single bit.
→ BCD also known as 8‐4‐2‐1 code. It is weighted code.
Combinational and Sequential Circuits: The circuits in which the outputs at any instant of time depend
upon the inputs present at that instant of time are called combinational circuits. This means that there is no
memory in these circuits. However, the circuits in which the outputs at any instant of time depend upon the
present inputs as well as past inputs/outputs, are called sequential circuits. A sequential circuit may have
combinational sub‐circuits. A sequential circuit whose behavior depends upon the sequence in which the
input signals change is referred to as an asynchronous sequential circuit. The output will be affected
whenever the inputs change. A sequential circuit whose behavior can be defined from the knowledge of its
signal at discrete instants of time is referred to as synchronous sequential circuit. The output will be
affected whenever the inputs change.
ALU (Arithmetic logic unit) is capable of performing arithmetic as well as logical operations. This is the
heart of microprocessor.
Parity or Error code: When the digital information in the binary form is transmitted from one circuit to
another circuit an error may occur. In complex systems, millions of bits per second are manipulated and it
is desired to have high data integrity. A simple process of improving data integrity in digital system is by
adding one additional bit in the data known as parity bit. This extra bit allows the detection of a simple
error in transmission. By parity we mean the number of 1’s in a digital data which may be even (even
parity) or odd (odd parity). In ASCII code C is coded as 1000011. There are three 1’s in this and we say that
its parity is odd. If we add an extra bit b7, the total number of ones in the 8‐bit code corresponding to C will
be ODD if B7 = 0 and EVEN if b7 = 1.This extra bit is transmitted from the transmitting end along with the
code and the parity of the code is checked at the receiving end and if there is an error in one bit or in an odd
number of bits, it can be detected.
AND operation: A circuit which performs an AND operation is called AND gate. It has N inputs ( N ≥ 2 ) and
one output. AND operation is defined as “the output is 1 if and only if all the inputs are 1”.
OR operation: A circuit which performs OR operation is called OR gate. It has N inputs ( N ≥ 2 ) and one
output. OR operation is defined as “the output of OR gate is 1 if and only if one or more inputs are 1”.
NAND and NOR as Universal gate:
Exclusive OR gate: This logic circuit finds application where two digital signals are to be compared.
De Morgan’s theorem: (i) A + B = A ⋅ B (ii) A ⋅ B ⋅ C = A + B + C
Signed Binary Numbers: If there is 0 at MSB in a binary number then it is termed as positive. On the other
hand if there is 1 at MSB then the number is negative. The number (11000100) represents a negative
number with magnitude (1000100) = 68. In binary one’s complement if one number is positive then other
will be negative.
Two’s complement representation
(i) If 1 is added to 1’s complement of a binary number, the resulting number is known as the 2’s
complement of the binary number.
(ii) If LSB of the number is 1, its 2’s complement is obtained by changing each 0 to 1 and 1 to 0 except the
least significant bit.
(iii) If the LSB of the number is 0, its 2’s complement is obtained by scanning the number from the LSB to
MSB bit by bit and retaining the bits as they are upto and including the occurrence of the first 1 and
complement all other bits. 01100100 → 10011100, 01100111 → 10011001
NOR latch: For NOR latch, low R and low S give the inactive state, the circuit stores and remembers. A low R
and high S represent the set state
while high R and low S give the
reset state. Finally, a high R and
high S produce a race condition.
From the timing diagram of NOR
latch we see that the output Q goes
high when S goes high. Q remains
high after S goes low. Q returns to
low when R goes high and stay
low after R return to low.
NAND latch: For NAND latch, R =
1 and S = 1 becomes the inactive
state; R = 0, S = 0 becomes the race
condition. R = 0 and S = 1
represent the set state and R = 1
and S = 0 gives the reset state.
From timing diagram, we see
that Q goes high whenever R
goes low. Output Q goes low
whenever S goes low.
Clocked SR flipflop:
From the timing diagram we
see that the output Q of clocked
NAND latch is high when S is
high and CLK is high. Output Q
returns to low state when R is
high and CLK goes high.
When the CLK is high the circuit will set if S is high or reset
if R is high. CLK, R and S all high is a race condition.
Dflipflop: If we use
only the middle two
rows of the truth table of
the S‐R flip‐flop or J‐K
flip‐flop, we obtain a D‐
type flip‐flop as shown in figure. Because of the inverter,
data bit D drives the S input of a NAND latch and the
component D drives the R input. Therefore, a high D sets
the latch and low D resets it. In case of clocked D‐flip flop,
low CLK disables the input gates and prevents the latch from changing states. In other words, while CLK is
low, the latch is in the inactive state and the circuit stores or remembers. When CLK is high D controls the
output. A high D sets the latch and low D resets it.
JK flipflop: The J and K inputs are control
inputs; they determine what the circuit will do
on the positive clock edge. When J and K are
low, both input gates are disabled and the
circuit is inactive at all times during the rising
edge of the clock. When J is low and K is high,
the rising clock edge resets the flip flop. When
J is high and K is low, then the rising clock
edge set the flip flop.
From timing diagram, we see that when J is
high and K is low, the rising clock edge sets Q
to high. On the other hand, when J is low and K
is high, the riding clock edge resets Q to low. When J and K both are high simultaneously, the output toggles
on each rising clock edge.
MasterSlave JK FlipFlop: In Master‐
Slave J‐K flip flop the Master is positively
clocked and Slave is negatively clocked.
Thus,
(i) When the clock is high Master is
active and Slave is inactive.
(ii) When the clock is low, the master is
inactive and slave is active.
Ttype flipflop: In a J‐K flip‐flop, if J = K,
the resulting flip‐flop is referred to as a T‐
type flip‐flop. It has only one input,
referred to as T‐input. An S‐R flip‐flop
cannot be converted into a T‐type flip‐flop
since S = R = 1 is not allowed.
Registers: A register is composed of a group of flip‐flops to store a group of bits. For storing an N‐bit word,
the number of flip‐flops required is N (one flip‐flop for each bit).
Register Modes: (i) serial in, serial out (SISO) (ii) serial in, parallel out (SIPO) (ii) parallel in, serial out
(PISO) and (iv) parallel in, parallel out (PIPO)
→ Registers in which data are entered or/ and taken out in serial form are referred to a shift registers,
since bits are shifted in flip‐flops with the occurrence of clock pulses either in the right direction (right‐
shift register) or in the left direction (left‐shift register).
→ A SISO shift register may be used to introduce time delay Δt in digital signals given by Δt = N × 1 where
fC
N is the number of stages and fC is the clock frequency.
→ Data in the serial form can be converted into parallel form by using a SIPO shift register.
→ Data in the parallel form can be converted into serial form by using a PISO shift register.
→ If the serial output of the shift register is connected back to the serial input, then an injected pulse will
keep circulating. This circuit is referred to as a ring counter.
→ Ring counter resembles a shift – left register because the bits are shifted left one position per positive
clock edge.
→ The modulus of a counter is the number of output states it has. A 4‐bit ripple counter has a modulus of
16 because it has 16 distinct states numbered from 0000 to 1111. A 10‐modulus counter will count the
numbers from 0000 to 1001 and on the tenth clock pulse the counter will generate its own clear signal
and the count jumps back to 0000.
D/A converter: (i) weighted‐register D/A converter and (ii) R‐2R ladder D/A converter.
Weightedregister D/A converter:
Figure shows the weighted‐resistor D/A convertor in which op‐amp is connected in inverting mode; it can
also be connected in non‐inverting mode. Since the number of inputs is four, the convertor is called a 4‐bit
convertor. Since there are 16 (24) combinations of binary inputs for b0 through b3 hence an analog output
should have 16 possible corresponding values. When switch b0 is closed (connected to +5V), the voltage
across R is 5V because V2 = V1 = 0V. Therefore the current through R is 5 V/10kΩ = 0.5 mA. However, the
input bias current is negligible hence the current through feedback resistor RF is also 0.5 mA, which in turn
produces an output voltage of ‐1 kΩ 0.5 mA ‐0.5 V. Thus, the op‐amp works as current‐to‐voltage
convertor. Again when the switch b1 is closed and b0 is open, then this connects R/2 to the positive supply
of 5 V causing twice much current 1 mA to flow through RF, which in turn doubles the output voltage.
Thus, the output voltage V0 ‐1 V when switch b1 is closed. Similarly, if both switches b0 and b1 are closed,
the current through RF will be 1.5 mA, which will be converted into output voltage of ‐1.5 V. Thus, when all
⎛ b0 b1 b2 b3 ⎞
switches b0, b1, b2 and b3 are closed then the output will be V0 = −R F ⎜ + + + ⎟ where b0, b1,
⎝ R R /2 R /4 R /8 ⎠
b2 and b3 may either 5V or 0V.
The voltage applied to a register is V(1) if the switch connected to it is in position 1 and V(0) if it is in
position 0. The current I is given by
I = I N −1 + I N −2 + I N −3 + ......... + I2 + I1 + I0
where IN −1 = VN −1 / R , IN −2 = VN −2 / 2R , IN −3 = VN −3 / 22 R ⇒ I0 = V0 / 2N −1 R}
Vn = V (1) if bn = 1 and V (0) if bn = 0
For straight binary input, V(0) = 0 and V(1) = ‐VR, and the output voltage V0 is given by
⎛R R R R R ⎞
(
V 0 = − ( − V R ) ⎜ F b N − 1 + F b N − 2 + 2 F b N − 3 + 3 F b N − 4 + ........... + N −F1 b 0 ⎟ = K 2 N − 1 b N − 1 + 2 N − 2 b N − 2 + 2 N − 3 b N − 3 + ........... + 2 2 b 2 + 2 b 1 + b 0 )
⎝ R 2R 2 R 2 R 2 R ⎠
RF
w h e r e K = N − 1 .V R
2 R
R2R Ladder D/A converter:
FSV(full scale voltage):
VR ⎛ 1 ⎞
e0 = or VR ⎜ 1 − N ⎟
2N ⎝ 2 ⎠
where N = is the number of bits
Re solution :
step size
% resolution = × 100
FSV
1
= N × 100
2 −1
V
or resolution in volts = NR ,
2 R
⎛ Vref R f ⎞
V0 = − ⎜ × N ⎟ × D where
⎝ R 2 ⎠
D = is the decimal value equivalent to binary ,
I out = resolution × D
The output voltage of an N‐bit R‐2R D/A converter is given
⎛ Rf V Rf V Rf V ⎞⎫
Vo = − ⎜ . R3 b0 + . R2 b1 + . R1 b2 ⎟ ⎪
⎝ 3R 2 3R 2 3R 2 ⎠⎪
⎬
⎛ R f ⎞ ⎛ VR ⎞ ⎪
= − ⎜ ⎟ . ⎜ 3 ⎟ ( 4b2 + 2b1 + b0 ) ⎪
⎝ 3R ⎠ ⎝ 2 ⎠ ⎭
⎛ b3 b2 b1 b0 ⎞
by ⇒ Vo = ( 2N −1 bN −1 + 2N −2 bN −2 + .... + 22 b2 + 21 b1 + 20 b0 ) V0 = −R F ⎜ + + + ⎟
⎝ 2R 4R 8R 16R ⎠
where R f = 3R andVR = −2N V .
Shift left register: When Din = 1, Q = 0001, 0011, 0111, 1111 and the stored word remains unchanged as
long as Din = 1. When Din changed to 0, then successive clock pulses produce these register contents, Q =
1110, 1100, 1000,
0000.
Shift right register:
When Din = 1 the first
positive clock edge sets
the left flip flop and the
stored word becomes Q
=1000, the second
rising edge gives Q
=1100, the third edge Q
= 1110 and forth rising
edge gives Q =1111.
Ripple counter: If CLR
goes low, the register
contents becomes Q =
0000. When the first
clock pulse hits the LSB
flip flop, Q0 becomes 1,
so the first output is Q =
0001. When second
pulse arrives, Q0 resets
and carries therefore,
the next output word is
Q = 0010. Thus, in the
similar way we have
Third pulse gives Q
= 0011
Forth pulse gives Q
= 0100
Fifth pulse gives Q = 0101
Sixth pulse gives Q = 0110
Seventh pulse gives Q = 0111.
On the eighth pulse Q0 resets and carries, Q1 resets and carries Q2 resets and caries and Q3 advances to
1. So the output word becomes Q = 1000.
Each flip flop divides the clock frequency by a factor of 2. So it is also known as divide–by–2 circuit.
Since each flip flop divides the clock frequency by 2, n flip flop will divide the clock frequency by 2n.
→ The number of registers required for an N‐bit D/A converter is 2N in the case of R‐2R ladder D/A
converter whereas it is only N in the case of a weighted‐register D/A converter.
→ Resolution: This is the smallest possible change in output voltage as a fraction or percentage of the full‐
scale output range. For an 8‐bit converter there are 28 or 256 possible values of among output voltage,
hence the smallest change in the output voltage is 1/256th of the full‐scale output range. Its resolution is
defined as one part in 255, or 0.4 %.
→ The accuracy of a D/A converter is a measure of the difference between the actual output voltage and
the expected output voltage. It is specified as a percentage of full‐scale or maximum output voltage. If a
D/A converter have 10V full‐scale output voltage and an accuracy of ±0.2%, then the maximum error
for any output voltage will be 0.002 × 10 = 20 mV.
→ The time required for analog output to settle to within 1/2 LSB of the final value after a change in the
digital input is referred to as settling time.
A/D Converters: In a digital‐to‐analog converter, the possible number of digital inputs is fixed. In contrast,
in an analog‐to‐digital converter, the input analog voltage can have any value in a range. But the digital
output can have only 2N discrete values for an N‐bit converter.
(i) Successive approximation A/D converter
(ii) Parallel comparator A/D converter (2N‐1, comparators are required for N‐bit convertor)
(iii) Counting A/D converter
Va N
(iv) Dual slope A/D converter number of count n = ⋅2
VR
→ If the information stored in a memory is lost when electrical power is switched off, the memory is
referred to as a volatile memory. The RAM is a volatile memory. On the other hand, in a non‐volatile
memory, the information once stored remains intact until changed deliberately. All types of ROMs are
non‐volatile memories.
→ Bipolar RAMs utilize BJTs and are manufactured using TTL, ECL or I2L technology. Modern MOS RAMs
are manufactured using NMOS or CMOS technology. Bipolar RAMs are almost static while MOS RAMs
either static or dynamic. Static bipolar RAMs utilize flip flops for storage and each memory cell
requires 6‐8 MOS transistors.
→ MBR → memory buffer register , MDR → memory data register , MAR → memory address register .
→ In EPROM, data can be erased with ultraviolet light. However, in EEPROM data can be erased using
electrical pulses.
→ The access time of a memory is the time it takes to read a stored word after applying address bits. Since
bipolar transistors are faster than MOSFETs, bipolar memories have faster access time than MOS
memories.
→ A/D converter is input device while D/A is the output device. I/O devices are called peripheral
elements. A computer having a microprocessor as its CPU is called a microcomputer.
Signaltonoise ratio: Signal‐to‐noise ratio is an electrical engineering measurement defined as the ratio of
a signal power to the noise power corrupting the signal. Signal‐to‐noise ratio compares the level of a
desired signal (such as music) to the level of background noise. The higher the ratio, the less obtrusive the
background noise is. In engineering, signal‐to‐noise ratio is a term for the power ratio between a signal
(meaningful information) and the background noise:
SNR = Psignal / Pnoise = ( Asignal / Anoise ) where P is average power and A is
2
root mean square (RMS) amplitude.
In decibels, the SNR is, by definition, 10 times the logarithm of the power ratio. If the signal and the noise
are measured across the same impedance then the SNR can be obtained by calculating 20 times the base‐10
⎛ Psignal ⎞ ⎛ A signal ⎞
logarithm of the amplitude ratio: SNR (dB) = 10log10 ⎜ ⎟ = 20log10 ⎜ ⎟ .
P
⎝ noise ⎠ ⎝ A noise ⎠
LockIn Amplifier: Lock‐in amplifiers are used to measure the amplitude and phase of signals buried in
noise. They achieve this by acting as a narrow bandpass filter which removes much of the unwanted noise
while allowing through the signal which is to be measured. All lock‐in amplifiers, whether analogue or
digital, rely on the concept of phase sensitive detection for their operation. Stated simply, phase sensitive
detection refers to the demodulation or rectification of an ac signal by a circuit which is controlled by a
reference waveform derived from the device which caused the signal to be modulated. The phase sensitive
detector effectively responds to signals which are coherent (same frequency and phase) with the reference
waveform and rejects all others The frequency of the signal to be measured and hence the passband region
of the filter is set by a reference signal, which has to be supplied to the lock‐in amplifier along with the
unknown signal. The reference signal must be at the same frequency as the modulation of the signal to be
measured.
A lock‐in amplifier, in common with most AC indicating instruments, provides a DC output proportional to
the AC signal under investigation. The special rectifier, called a phase‐sensitive detector (PSD), which
performs this AC to DC conversion forms the heart of the instrument. It is special in that it rectifies only the
signal of interest while suppressing the effect of noise or interfering components which may accompany
that signal. The detector operates by multiplying two signals together, and the following analysis indicates
how this gives the required outputs.