Circuit Calculation:

In a DC-DC boost converter if we have a DC input voltage we can control the voltage
across the load Vo by controlling the duty cycle D and Vin .

The proposed topology has a gain of G=V0 / Vin = 380/34 = 11.17. To calculate the duty ratio we
use equation 12 from [main paper].
1 1
𝐺(𝐷 > 0.5) = 2(1−𝐷)2
 11.17= 2(1−𝐷)2  D=0.78

Given that the switching frequency fs = 50KHz  Ts = 1/fs = 2x10-5 sec.

𝑇𝑜𝑛
The time where S1 and S2 are ON can be calculated by D =  Ton = D.T = 0.78*2x10-5 =
𝑇
1.56*10-5 sec, and Toff is simply 1-Ton = 0.44*10-5 sec.

Also is important to control the phase shift between the two switches, in order to do that Fig
[xxx][from main paper] shows the switching time for the proposed converter. One period of
time T consist of multiple stages [∆𝑡1, ∆𝑡2, ∆𝑡4, ∆𝑡5] these stage used to turn the switched of
and off, also they are used as parameters for the control signal as we will see later.

Equation [xxx][main paper] used to calculate the time for each stage:

Fig [xxx] Proposed topology switching time

𝑇.(2.𝐷−1) 2∗10−5 (2∗0.78−1)

∆𝑡1 = ∆𝑡4 = = = 0.56*10-5 sec [xxx]
2 2

∆𝑡2 = ∆𝑡5 = 𝑇. (1 − 𝐷) = 2*10-5(1-0.78) = 0.44*10-5 sec [xxx]

∆𝑡3 = ∆𝑡1 + ∆𝑡2 + ∆𝑡4 = (0.56 + 0.44 + 0.56) ∗ 10−5 = 1.56*10-5 sec [xxxx]

Table [xxx] shows the switches states during each stage

 ∆𝑇 S1 S2 ∅
∆𝑡1 ON ON 100.8°
∆𝑡2 ON OFF 79.2°
∆𝑡4 ON ON 100.8°
∆𝑡5 OFF ON 79.2°
Table [xxx] S1,S2 states during 1T
PWM control Signal:

In order to have the desired output voltage, S1 and S2 have to turn on and off at specific time
mentioned in table [xxx]. S1 and S2 are fully controlled by the control signal or gating signal, this
signal is simply a DC voltage signal with amplitude relatively small amplitude here is 1V, Fig[xxx]
is a diagram of the Vcomp1 the gating signal for Switch 1.

Figure [xxx] Vcomp1 the gating signal to control switch 1

To obtain the gating signal to control the switches to turn on and off, PWM technique is used in
the proposed topology.

Figure[xxx] is the topology of PWM

In this model two sawtooth voltage sources with amplitude of 2 volts are used, note: at high
frequency we used Tri voltage source in Psim to obtain sawtooth waveform as in Figure [xxx].

This sawtooth signal is the negative input at the comparator one, for the positive input we use a
simple DC source to generate a DC voltage signal to serve as a reference signal. The comparator
job is to compare the sawtooth signal with the reference signal, as long as the reference signal
has a higher amplitude than the sawtooth signal the output is positive and the switch will turn
ON, after a certain time when the amplitude of the reference signal is less the amplitude of the
sawtooth signal the output of the comparator is zero and the switch will turn off. Figure [xxx]
shows the relationship between the output signal of the comparator and the current across the
switch.

Fig[xxx]

Another important aspect is the value of the reference signal, from figure [xxx] it is clearly
shown that the V comparator signal is controlled by the value of the reference signal which is
calculated by: Vctrl= Vtrimax*D= 1.56 V [xxx] .Figure [xxx] shows the Comparator, sawtooth and
reference signal respectively during a three times period.
Fig [xxx] . The Comparator(RED), sawtooth(BLUE) and reference signal(GREEN) signals during a
three times period

Current Ripples;

In continues conduction mode the current across the inductors L1 and L2 changes according to
the status of the switches, for example, if we look at stage one Fig[xxx] we notice when S1 and S2
are on, the circuit is disconnected from the load, or in other words there is no path for the
current to the load, this state causes the inductors to store energy and the current IL1 and IL2
increases. On stage two, S1 is on and S2 is off, making a path for the current to the load, in this
case the current across the inductors decreases. Based on this analysis we can come up with
values for L1 and L2:
𝑉𝑜(1−𝐷)2 .(2.𝐷−1) 380(1−0.78)2 .(2∗0.78−1)
𝐿1 = ∆𝐼𝐿1 .𝑓𝑠
= 3∗50000
= 68µ Henry

𝑉𝑜(1−𝐷).(2.𝐷−1) 380(1−0.78).(2∗0.78−1)
𝐿2 = 2.∆𝐼𝐿2 .𝑓𝑠
= 2∗3∗50000
= 156µ Henry
Figure [xxx] is the current across L1 and L2 obtained from PSIM:

Fig[]: the current across L1 and L2

Where assuming the input current is 15A [xxx] and current peak to peak ratio across the
inductors is ∆𝐼𝐿1 = ∆𝐼𝐿2 = 20% [xxx].

Capacitors Calculation

In Psim Simulation we have

The peak to peak voltage ripples across the load is due to the variation of voltage across the
capacitors, and it can be calculated from [7-39 ned mohan book]:

𝑉𝑜.𝐷 𝑇𝑠 380∗0.78∗2∗10−5
∆𝑉𝑜 = 𝑅.𝐶
= 278∗165∗10−6
= 0.129 Volt or 0.03% of Vo

Where C here is total capacitance in parallel of C1 and C2 and R =520/380=278 Ω Ohm. ]. Fig[xxx]
shows the values we obtained from PSIM.

The capacitances of the capacitors Coint, Co1 and Co2 can be calculated with a determined
voltage ripple (∆𝑉𝑐),[equation 21 and 22] as
2.𝐼𝑜.(𝑉𝑜𝑖𝑛𝑡 −𝑉𝑖𝑛 ) 2.𝐼𝑜.(𝑉𝑜𝑖𝑛𝑡 −𝑉𝑖𝑛 ) 2∗1.27(77.3−34)
∆𝑉𝑜𝑖𝑛𝑡 = 𝐶𝑜𝑖𝑛𝑡 .𝑓.𝑉𝑖𝑛
>> 𝐶𝑜𝑖𝑛𝑡 = ∆𝑉𝑜𝑖𝑛𝑡 .𝑓.𝑉𝑖𝑛
= 0.61∗50000∗34
= 1060 u Farad

𝐼𝑜.(2𝑉𝐶𝑜1 −𝑉𝑜𝑖𝑛𝑡 )
∆𝑉𝐶1 = ∆𝑉𝐶2 = 2𝐶𝑜1 .𝑓.𝑉𝐶𝑂1
≫

𝐼𝑜.(2𝑉𝐶𝑜1 −𝑉𝑜𝑖𝑛𝑡 ) 1.27∗(2∗175−77.3)

𝐶𝑜1 = 𝐶𝑜2 = 2∆𝑉𝐶1 .𝑓.𝑉𝐶𝑂1
= 2∗0.07∗50000∗175
= 378 farad
FFT analysis:

Using the built in function from PSIM, we were able to calculate the harmonics at the input side
of the circuit. At the input, the harmonics appears at even multiple of the switching frequency,
1.4
and the dominant harmonic is at 100 KHz with a magnitude of 1.4Ampes or 14.2 = 10% of the
fundamental current harmonic. The second harmonics is at 200 KHz with magnitude of 0.1
Amps, Fig [xxx] shows the FFT of the input current.

Fig [] FFT of the input current