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MSc (IT)
SEMESTER-I
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Date : 25/09/2010
1. What are status flags? How they are useful in determining the status of the CPU?
An instruction pipeline is a technique used in the design of computers and other digital
electronic devices to increase their instruction throughput (the number of instructions that can be
executed in a unit of time).
It is a technique for overlapping the execution of several instructions to reduce the execution
time of a set of instructions.
The fundamental idea is to split the processing of a computer instruction into a series of
independent steps, with storage at the end of each step. This allows the computer's control
circuitry to issue instructions at the processing rate of the slowest step, which is much faster than
the time needed to perform all steps at once. The term pipeline refers to the fact that each step is
carrying data at once (like water), and each step is connected to the next (like the links of a pipe.)
An instruction pipeline reads consecutive instructions from memory while previous instructions
are being executed in other segments this causes instruction fetch and execute phases to overlap
and perform simultaneous operations.
One possible digression associated with such a scheme is that an instruction may cause a branch
out of sequence. In that case the pipeline must be emptied and all the instructions that have been
read from memory after the branch instructions must be discarded.
In order to speed up the operation of a computer system beyond what is possible with sequential
execution, methods must be found to perform more than one task at a time. One method for
gaining significant speedup with modest hardware cost is the technique of pipelining. In this
technique, A task is broken down into multiple steps, and independent processing units are
assigned to each step. Once a task has completed its initial step, another task may enter that step
while the original task moves on to the following step. The process is much like an assembly
line, with a different task in progress at each stage. In theory, a pipeline which breaks a process
into N steps could achieve an N-fold increase in processing speed. Due to various practical
problems, the actual gain may be significantly less.
Pipelining is most suited for tasks in which essentially the same sequence of steps must be
repeated many times for different data.
Instruction processing
The first step in applying pipelining techniques to instruction processing is to divide the task into
steps that may be performed with independent hardware. The most obvious division is between
the FETCH cycle (fetch and interpret instructions) and the EXECUTE cycle (access operands
and perform operation). If these two activities are to run simultaneously, they must use
independent registers and processing circuits, including independent access to memory (separate
MAR and MBR).
It is possible to further divide FETCH into fetching and interpreting, but since interpreting is
very fast this is not generally done. To gain the benefits of pipelining it is desirable that each
stage take a comparable amount of time.
A more practical division would split the EXECUTE cycle into three parts: Fetch operands,
perform operation, and store results. A typical pipeline might then have four stages through
which instructions pass, and each stage could be processing a different instruction at the same
time. The result of each stage is passed on to the next stage.
Several difficulties prevent instruction pipelining from being as simple as the above description
suggests. The principal problems are:
TIMING VARIATIONS: Not all stages take the same amount of time. This means that the speed
gain of a pipeline will be determined by its slowest stage. This problem is particularly acute in
instruction processing, since different instructions have different operand requirements and
sometimes vastly different processing time. Moreover, synchronization mechanisms are required
to ensure that data is passed from stage to stage only when both stages are ready.
DATA HAZARDS: When several instructions are in partial execution, a problem arises if they
reference the same data. We must ensure that a later instruction does not attempt to access data
sooner than a preceding instruction, if this will lead to incorrect results. For example, instruction
N+1 must not be permitted to fetch an operand that is yet to be stored into by instruction N.
BRANCHING: In order to fetch the "next" instruction, we must know which one is required. If
the present instruction is a conditional branch, the next instruction may not be known until the
current one is processed.
It is sometimes convenient to supplement the ALU circuit in the CPU with a status register
where status bit condition can be stored for further analysis. Status bits are also called condition-
code bits or flag bits.
The Figure 1 below shows the block diagram of an 8-bit ALU with a 4-bit status register. The
four status bits are symbolized by C, S, Z, and V. The bits are set or cleared as a result of an
operation performed in the ALU.
1. Bit C (carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the carry is 0.
2. Bit S (sign) is set to 1 if the highest-order bit F7 is 1. It is set to 0 if the bit is 0.
3. Bit Z (Zero) is set to 1 if the output of the ALU contains all O’s. It is cleared to 0
otherwise. In other words, Z = 1 if the output is zero and
Z = 0 if the output is not zero.
4. Bit V (overflow) is set to 1 if the exclusive-OR of the last two caries is equal to 1, and
cleared to 0 otherwise. This is the condition for an overflow when negative numbers are
in 2’s complement For the 8-bit ALU, V= 1 if the output greater than +127 or less than -
128.
Example: A
Processor status flag
The 6510 CPU has an internal status register that consists of eight processor status flags, of
which seven are actually used. These flags are set or unset by the processor to give information
about the results of the latest executed machine language command. Many branch commands
for example make heavy use of the flags.
C - Carry: This flag shows when the result of the executed operation exceeds or goes below the
value range of one byte (00-FF)
B - Break: This flag will be set when the processor is stopped due to a BRK command
V - Overflow: Shows when the result exceeds or goes below the value range of one byte (00-FF)
when the carry flag is already set. When executing the BIT command, the overflow flag shows
the sixth bit of thested byte.
Example : B
Flags
The ALU includes five flip-flops, which are set or reset after an operation according to data
conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry
(CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags.The most commonly used flags are
Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions. For example,
after an addition of two numbers, if the sum in the accumulator id larger than eight bits, the flip-
flop uses to indicate a carry -- called the Carry flag (CY) – is set to one. When an arithmetic
operation results in zero, the flip-flop called the Zero(Z) flag is set to one. Let say that the flags
are stored in the 8-bit register so that the programmer can examine these flags (data conditions)
by accessing the register through an instruction.
These flags have critical importance in the decision-making process of the microprocessor.
The conditions (set or reset) of the flags are tested through the software instructions. For
example, the instruction JC (Jump on Carry) is implemented to change the sequence of a
program when CY flag is set. The thorough understanding of flag is essential in writing assembly
language programs.
Example: C
The ADD, INC (Increment), SUB, and DEC (Decrement) instructions have two
requirements:
o If there are two operands, only one operand can be a memory operand.
o If there are two operands, both must be the same size. For example,
add ebx, eax ; Add two registers, result stored in EBX
add eax, [ebx] ; Add register and a doubleword in memory
add [value], 10h ; Add immediate value to a doubleword
3. Carry Flag
4. Overflow Condition
When two signed 2's complement numbers are added, the overflow flag OF indicates one
of the following:
1. both operands are positive and the result is negative, or
2. both operands are negative and the result is positive.
When two unsigned numbers are added, the carry flag CF indicates an overflow, that is,
o there is a carry out of the leftmost (most significant) bit.
Computers don't know the difference between signed and unsigned binary numbers.
(OF) overflow flag indicates that result is too large to fit in the 8-bit destination operand:
o The sum of two positive signed operands exceeds 127.
o The difference of two negative operands is less than -128.
(CF) carry flag indicates that the sum of two unsigned operands exceeded 255.
(SF) sign flag indicates that result goes below 0.
LAHF instruction loads lower byte of the EFLAGS register into AH register.
The lowest 8 bits of the flags are transferred:
o Sign
o Zero
o Auxiliary Carry
o Parity
o Carry
Instruction format:
lahf
SAHF restores the value of lower byte flags. Format:
sahf
The NEG instruction negates a value by finding 2's complement of its single operand.
This simply means multiply operand by -1.
When a positive value is negated the result is negative.
Name:Hailay Kidu Teklehaimanot
September 25/2010 Page 10
A negative value will become positive.
Zero remains zero.
For example,
mov al, -1 ; Load register
neg al ; AL now has 1
SHL is very useful for computing powers of 2 and multiplication by 2, since each time
binary number is shifted left, its numeric value doubles.